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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP4; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECKBE5 6define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2) {7; CHECK-LABEL: vmovn32_trunc1:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vmovnt.i32 q0, q110; CHECK-NEXT: bx lr11;12; CHECKBE-LABEL: vmovn32_trunc1:13; CHECKBE: @ %bb.0: @ %entry14; CHECKBE-NEXT: vrev64.32 q2, q115; CHECKBE-NEXT: vrev64.32 q1, q016; CHECKBE-NEXT: vmovnt.i32 q1, q217; CHECKBE-NEXT: vrev64.16 q0, q118; CHECKBE-NEXT: bx lr19entry:20 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>21 %out = trunc <8 x i32> %strided.vec to <8 x i16>22 ret <8 x i16> %out23}24 25define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc2(<4 x i32> %src1, <4 x i32> %src2) {26; CHECK-LABEL: vmovn32_trunc2:27; CHECK: @ %bb.0: @ %entry28; CHECK-NEXT: vmovnt.i32 q1, q029; CHECK-NEXT: vmov q0, q130; CHECK-NEXT: bx lr31;32; CHECKBE-LABEL: vmovn32_trunc2:33; CHECKBE: @ %bb.0: @ %entry34; CHECKBE-NEXT: vrev64.32 q2, q035; CHECKBE-NEXT: vrev64.32 q3, q136; CHECKBE-NEXT: vmovnt.i32 q3, q237; CHECKBE-NEXT: vrev64.16 q0, q338; CHECKBE-NEXT: bx lr39entry:40 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>41 %out = trunc <8 x i32> %strided.vec to <8 x i16>42 ret <8 x i16> %out43}44 45define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc3(<4 x i32> %src1) {46; CHECK-LABEL: vmovn32_trunc3:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: vmovnt.i32 q0, q049; CHECK-NEXT: bx lr50;51; CHECKBE-LABEL: vmovn32_trunc3:52; CHECKBE: @ %bb.0: @ %entry53; CHECKBE-NEXT: vrev64.32 q1, q054; CHECKBE-NEXT: vmovnt.i32 q1, q155; CHECKBE-NEXT: vrev64.16 q0, q156; CHECKBE-NEXT: bx lr57entry:58 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> undef, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>59 %out = trunc <8 x i32> %strided.vec to <8 x i16>60 ret <8 x i16> %out61}62 63define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc1_viabitcast(<4 x i32> %src1, <4 x i32> %src2) {64; CHECK-MVE-LABEL: vmovn32_trunc1_viabitcast:65; CHECK-MVE: @ %bb.0: @ %entry66; CHECK-MVE-NEXT: .pad #1667; CHECK-MVE-NEXT: sub sp, #1668; CHECK-MVE-NEXT: vmov.f32 s8, s269; CHECK-MVE-NEXT: mov r0, sp70; CHECK-MVE-NEXT: vmov.f32 s9, s671; CHECK-MVE-NEXT: vmov.f32 s10, s372; CHECK-MVE-NEXT: vmov.f32 s11, s773; CHECK-MVE-NEXT: vstrh.32 q2, [r0, #8]74; CHECK-MVE-NEXT: vmov.f32 s8, s075; CHECK-MVE-NEXT: vmov.f32 s9, s476; CHECK-MVE-NEXT: vmov.f32 s10, s177; CHECK-MVE-NEXT: vmov.f32 s11, s578; CHECK-MVE-NEXT: vstrh.32 q2, [r0]79; CHECK-MVE-NEXT: vldrw.u32 q0, [r0]80; CHECK-MVE-NEXT: add sp, #1681; CHECK-MVE-NEXT: bx lr82;83; CHECK-MVEFP-LABEL: vmovn32_trunc1_viabitcast:84; CHECK-MVEFP: @ %bb.0: @ %entry85; CHECK-MVEFP-NEXT: .pad #1686; CHECK-MVEFP-NEXT: sub sp, #1687; CHECK-MVEFP-NEXT: mov r0, sp88; CHECK-MVEFP-NEXT: vmov.f32 s8, s289; CHECK-MVEFP-NEXT: vmov.f32 s9, s690; CHECK-MVEFP-NEXT: vmov.f32 s10, s391; CHECK-MVEFP-NEXT: vmov.f32 s11, s792; CHECK-MVEFP-NEXT: vstrh.32 q2, [r0, #8]93; CHECK-MVEFP-NEXT: vmov.f32 s8, s094; CHECK-MVEFP-NEXT: vmov.f32 s9, s495; CHECK-MVEFP-NEXT: vmov.f32 s10, s196; CHECK-MVEFP-NEXT: vmov.f32 s11, s597; CHECK-MVEFP-NEXT: vstrh.32 q2, [r0]98; CHECK-MVEFP-NEXT: vldrw.u32 q0, [r0]99; CHECK-MVEFP-NEXT: add sp, #16100; CHECK-MVEFP-NEXT: bx lr101;102; CHECKBE-LABEL: vmovn32_trunc1_viabitcast:103; CHECKBE: @ %bb.0: @ %entry104; CHECKBE-NEXT: .pad #16105; CHECKBE-NEXT: sub sp, #16106; CHECKBE-NEXT: vrev64.32 q2, q1107; CHECKBE-NEXT: vrev64.32 q1, q0108; CHECKBE-NEXT: mov r0, sp109; CHECKBE-NEXT: vmov.f32 s0, s6110; CHECKBE-NEXT: vmov.f32 s1, s10111; CHECKBE-NEXT: vmov.f32 s2, s7112; CHECKBE-NEXT: vmov.f32 s3, s11113; CHECKBE-NEXT: vstrh.32 q0, [r0, #8]114; CHECKBE-NEXT: vmov.f32 s0, s4115; CHECKBE-NEXT: vmov.f32 s1, s8116; CHECKBE-NEXT: vmov.f32 s2, s5117; CHECKBE-NEXT: vmov.f32 s3, s9118; CHECKBE-NEXT: vstrh.32 q0, [r0]119; CHECKBE-NEXT: vldrb.u8 q1, [r0]120; CHECKBE-NEXT: vrev64.8 q0, q1121; CHECKBE-NEXT: add sp, #16122; CHECKBE-NEXT: bx lr123entry:124 %b1 = bitcast <4 x i32> %src1 to <8 x i16>125 %b2 = bitcast <4 x i32> %src2 to <8 x i16>126 %s = shufflevector <8 x i16> %b1, <8 x i16> %b2, <16 x i32> <i32 0, i32 1, i32 8, i32 9, i32 2, i32 3, i32 10, i32 11, i32 4, i32 5, i32 12, i32 13, i32 6, i32 7, i32 14, i32 15>127 %b3 = bitcast <16 x i16> %s to <8 x i32>128 %out = trunc <8 x i32> %b3 to <8 x i16>129 ret <8 x i16> %out130}131 132 133define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc1(<8 x i16> %src1, <8 x i16> %src2) {134; CHECK-LABEL: vmovn16_trunc1:135; CHECK: @ %bb.0: @ %entry136; CHECK-NEXT: vmovnt.i16 q0, q1137; CHECK-NEXT: bx lr138;139; CHECKBE-LABEL: vmovn16_trunc1:140; CHECKBE: @ %bb.0: @ %entry141; CHECKBE-NEXT: vrev64.16 q2, q1142; CHECKBE-NEXT: vrev64.16 q1, q0143; CHECKBE-NEXT: vmovnt.i16 q1, q2144; CHECKBE-NEXT: vrev64.8 q0, q1145; CHECKBE-NEXT: bx lr146entry:147 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>148 %out = trunc <16 x i16> %strided.vec to <16 x i8>149 ret <16 x i8> %out150}151 152define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc2(<8 x i16> %src1, <8 x i16> %src2) {153; CHECK-LABEL: vmovn16_trunc2:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vmovnt.i16 q1, q0156; CHECK-NEXT: vmov q0, q1157; CHECK-NEXT: bx lr158;159; CHECKBE-LABEL: vmovn16_trunc2:160; CHECKBE: @ %bb.0: @ %entry161; CHECKBE-NEXT: vrev64.16 q2, q0162; CHECKBE-NEXT: vrev64.16 q3, q1163; CHECKBE-NEXT: vmovnt.i16 q3, q2164; CHECKBE-NEXT: vrev64.8 q0, q3165; CHECKBE-NEXT: bx lr166entry:167 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>168 %out = trunc <16 x i16> %strided.vec to <16 x i8>169 ret <16 x i8> %out170}171 172define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc3(<8 x i16> %src1) {173; CHECK-LABEL: vmovn16_trunc3:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vmovnt.i16 q0, q0176; CHECK-NEXT: bx lr177;178; CHECKBE-LABEL: vmovn16_trunc3:179; CHECKBE: @ %bb.0: @ %entry180; CHECKBE-NEXT: vrev64.16 q1, q0181; CHECKBE-NEXT: vmovnt.i16 q1, q1182; CHECKBE-NEXT: vrev64.8 q0, q1183; CHECKBE-NEXT: bx lr184entry:185 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> undef, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>186 %out = trunc <16 x i16> %strided.vec to <16 x i8>187 ret <16 x i8> %out188}189 190 191 192define arm_aapcs_vfpcc <2 x i64> @vmovn64_t1(<2 x i64> %src1, <2 x i64> %src2) {193; CHECK-LABEL: vmovn64_t1:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: vmov.f32 s2, s4196; CHECK-NEXT: vmov.f32 s3, s5197; CHECK-NEXT: bx lr198;199; CHECKBE-LABEL: vmovn64_t1:200; CHECKBE: @ %bb.0: @ %entry201; CHECKBE-NEXT: vmov.f32 s2, s4202; CHECKBE-NEXT: vmov.f32 s3, s5203; CHECKBE-NEXT: bx lr204entry:205 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 2>206 ret <2 x i64> %out207}208 209define arm_aapcs_vfpcc <2 x i64> @vmovn64_t2(<2 x i64> %src1, <2 x i64> %src2) {210; CHECK-LABEL: vmovn64_t2:211; CHECK: @ %bb.0: @ %entry212; CHECK-NEXT: vmov.f32 s6, s0213; CHECK-NEXT: vmov.f32 s7, s1214; CHECK-NEXT: vmov q0, q1215; CHECK-NEXT: bx lr216;217; CHECKBE-LABEL: vmovn64_t2:218; CHECKBE: @ %bb.0: @ %entry219; CHECKBE-NEXT: vmov.f32 s6, s0220; CHECKBE-NEXT: vmov.f32 s7, s1221; CHECKBE-NEXT: vmov q0, q1222; CHECKBE-NEXT: bx lr223entry:224 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 0>225 ret <2 x i64> %out226}227 228define arm_aapcs_vfpcc <2 x i64> @vmovn64_b1(<2 x i64> %src1, <2 x i64> %src2) {229; CHECK-LABEL: vmovn64_b1:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vmov.f32 s2, s6232; CHECK-NEXT: vmov.f32 s3, s7233; CHECK-NEXT: bx lr234;235; CHECKBE-LABEL: vmovn64_b1:236; CHECKBE: @ %bb.0: @ %entry237; CHECKBE-NEXT: vmov.f32 s2, s6238; CHECKBE-NEXT: vmov.f32 s3, s7239; CHECKBE-NEXT: bx lr240entry:241 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3>242 ret <2 x i64> %out243}244 245define arm_aapcs_vfpcc <2 x i64> @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2) {246; CHECK-LABEL: vmovn64_b2:247; CHECK: @ %bb.0: @ %entry248; CHECK-NEXT: vmov.f32 s4, s6249; CHECK-NEXT: vmov.f32 s6, s0250; CHECK-NEXT: vmov.f32 s5, s7251; CHECK-NEXT: vmov.f32 s7, s1252; CHECK-NEXT: vmov q0, q1253; CHECK-NEXT: bx lr254;255; CHECKBE-LABEL: vmovn64_b2:256; CHECKBE: @ %bb.0: @ %entry257; CHECKBE-NEXT: vmov.f32 s4, s6258; CHECKBE-NEXT: vmov.f32 s6, s0259; CHECKBE-NEXT: vmov.f32 s5, s7260; CHECKBE-NEXT: vmov.f32 s7, s1261; CHECKBE-NEXT: vmov q0, q1262; CHECKBE-NEXT: bx lr263entry:264 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0>265 ret <2 x i64> %out266}267 268define arm_aapcs_vfpcc <2 x i64> @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2) {269; CHECK-LABEL: vmovn64_b3:270; CHECK: @ %bb.0: @ %entry271; CHECK-NEXT: vmov.f32 s0, s2272; CHECK-NEXT: vmov.f32 s2, s4273; CHECK-NEXT: vmov.f32 s1, s3274; CHECK-NEXT: vmov.f32 s3, s5275; CHECK-NEXT: bx lr276;277; CHECKBE-LABEL: vmovn64_b3:278; CHECKBE: @ %bb.0: @ %entry279; CHECKBE-NEXT: vmov.f32 s0, s2280; CHECKBE-NEXT: vmov.f32 s2, s4281; CHECKBE-NEXT: vmov.f32 s1, s3282; CHECKBE-NEXT: vmov.f32 s3, s5283; CHECKBE-NEXT: bx lr284entry:285 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2>286 ret <2 x i64> %out287}288 289define arm_aapcs_vfpcc <2 x i64> @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2) {290; CHECK-LABEL: vmovn64_b4:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vmov.f32 s6, s2293; CHECK-NEXT: vmov.f32 s7, s3294; CHECK-NEXT: vmov q0, q1295; CHECK-NEXT: bx lr296;297; CHECKBE-LABEL: vmovn64_b4:298; CHECKBE: @ %bb.0: @ %entry299; CHECKBE-NEXT: vmov.f32 s6, s2300; CHECKBE-NEXT: vmov.f32 s7, s3301; CHECKBE-NEXT: vmov q0, q1302; CHECKBE-NEXT: bx lr303entry:304 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 1>305 ret <2 x i64> %out306}307 308 309 310define arm_aapcs_vfpcc <4 x i32> @vmovn32_t1(<4 x i32> %src1, <4 x i32> %src2) {311; CHECK-LABEL: vmovn32_t1:312; CHECK: @ %bb.0: @ %entry313; CHECK-NEXT: vmov.f32 s1, s4314; CHECK-NEXT: vmov.f32 s3, s6315; CHECK-NEXT: bx lr316;317; CHECKBE-LABEL: vmovn32_t1:318; CHECKBE: @ %bb.0: @ %entry319; CHECKBE-NEXT: vrev64.32 q2, q1320; CHECKBE-NEXT: vrev64.32 q1, q0321; CHECKBE-NEXT: vmov.f32 s5, s8322; CHECKBE-NEXT: vmov.f32 s7, s10323; CHECKBE-NEXT: vrev64.32 q0, q1324; CHECKBE-NEXT: bx lr325entry:326 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>327 ret <4 x i32> %out328}329 330define arm_aapcs_vfpcc <4 x i32> @vmovn32_t2(<4 x i32> %src1, <4 x i32> %src2) {331; CHECK-LABEL: vmovn32_t2:332; CHECK: @ %bb.0: @ %entry333; CHECK-NEXT: vmov.f32 s5, s0334; CHECK-NEXT: vmov.f32 s7, s2335; CHECK-NEXT: vmov q0, q1336; CHECK-NEXT: bx lr337;338; CHECKBE-LABEL: vmovn32_t2:339; CHECKBE: @ %bb.0: @ %entry340; CHECKBE-NEXT: vrev64.32 q2, q0341; CHECKBE-NEXT: vrev64.32 q3, q1342; CHECKBE-NEXT: vmov.f32 s13, s8343; CHECKBE-NEXT: vmov.f32 s15, s10344; CHECKBE-NEXT: vrev64.32 q0, q3345; CHECKBE-NEXT: bx lr346entry:347 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 0, i32 6, i32 2>348 ret <4 x i32> %out349}350 351define arm_aapcs_vfpcc <4 x i32> @vmovn32_b1(<4 x i32> %src1, <4 x i32> %src2) {352; CHECK-LABEL: vmovn32_b1:353; CHECK: @ %bb.0: @ %entry354; CHECK-NEXT: vmov.f32 s1, s5355; CHECK-NEXT: vmov.f32 s3, s7356; CHECK-NEXT: bx lr357;358; CHECKBE-LABEL: vmovn32_b1:359; CHECKBE: @ %bb.0: @ %entry360; CHECKBE-NEXT: vrev64.32 q2, q1361; CHECKBE-NEXT: vrev64.32 q1, q0362; CHECKBE-NEXT: vmov.f32 s5, s9363; CHECKBE-NEXT: vmov.f32 s7, s11364; CHECKBE-NEXT: vrev64.32 q0, q1365; CHECKBE-NEXT: bx lr366entry:367 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>368 ret <4 x i32> %out369}370 371define arm_aapcs_vfpcc <4 x i32> @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2) {372; CHECK-LABEL: vmovn32_b2:373; CHECK: @ %bb.0: @ %entry374; CHECK-NEXT: vmov.f32 s4, s5375; CHECK-NEXT: vmov.f32 s6, s7376; CHECK-NEXT: vmov.f32 s5, s0377; CHECK-NEXT: vmov.f32 s7, s2378; CHECK-NEXT: vmov q0, q1379; CHECK-NEXT: bx lr380;381; CHECKBE-LABEL: vmovn32_b2:382; CHECKBE: @ %bb.0: @ %entry383; CHECKBE-NEXT: vrev64.32 q2, q0384; CHECKBE-NEXT: vrev64.32 q0, q1385; CHECKBE-NEXT: vmov.f32 s4, s1386; CHECKBE-NEXT: vmov.f32 s5, s8387; CHECKBE-NEXT: vmov.f32 s6, s3388; CHECKBE-NEXT: vmov.f32 s7, s10389; CHECKBE-NEXT: vrev64.32 q0, q1390; CHECKBE-NEXT: bx lr391entry:392 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2>393 ret <4 x i32> %out394}395 396define arm_aapcs_vfpcc <4 x i32> @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2) {397; CHECK-LABEL: vmovn32_b3:398; CHECK: @ %bb.0: @ %entry399; CHECK-NEXT: vmov.f32 s0, s1400; CHECK-NEXT: vmov.f32 s2, s3401; CHECK-NEXT: vmov.f32 s1, s4402; CHECK-NEXT: vmov.f32 s3, s6403; CHECK-NEXT: bx lr404;405; CHECKBE-LABEL: vmovn32_b3:406; CHECKBE: @ %bb.0: @ %entry407; CHECKBE-NEXT: vrev64.32 q2, q1408; CHECKBE-NEXT: vrev64.32 q1, q0409; CHECKBE-NEXT: vmov.f32 s4, s5410; CHECKBE-NEXT: vmov.f32 s6, s7411; CHECKBE-NEXT: vmov.f32 s5, s8412; CHECKBE-NEXT: vmov.f32 s7, s10413; CHECKBE-NEXT: vrev64.32 q0, q1414; CHECKBE-NEXT: bx lr415entry:416 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6>417 ret <4 x i32> %out418}419 420define arm_aapcs_vfpcc <4 x i32> @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2) {421; CHECK-LABEL: vmovn32_b4:422; CHECK: @ %bb.0: @ %entry423; CHECK-NEXT: vmov.f32 s5, s1424; CHECK-NEXT: vmov.f32 s7, s3425; CHECK-NEXT: vmov q0, q1426; CHECK-NEXT: bx lr427;428; CHECKBE-LABEL: vmovn32_b4:429; CHECKBE: @ %bb.0: @ %entry430; CHECKBE-NEXT: vrev64.32 q2, q0431; CHECKBE-NEXT: vrev64.32 q3, q1432; CHECKBE-NEXT: vmov.f32 s13, s9433; CHECKBE-NEXT: vmov.f32 s15, s11434; CHECKBE-NEXT: vrev64.32 q0, q3435; CHECKBE-NEXT: bx lr436entry:437 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 6, i32 3>438 ret <4 x i32> %out439}440 441define arm_aapcs_vfpcc <4 x i32> @vmovn32_single_t(<4 x i32> %src1) {442; CHECK-LABEL: vmovn32_single_t:443; CHECK: @ %bb.0: @ %entry444; CHECK-NEXT: vmov.f32 s1, s0445; CHECK-NEXT: vmov.f32 s3, s2446; CHECK-NEXT: bx lr447;448; CHECKBE-LABEL: vmovn32_single_t:449; CHECKBE: @ %bb.0: @ %entry450; CHECKBE-NEXT: vrev64.32 q1, q0451; CHECKBE-NEXT: vmov.f32 s5, s4452; CHECKBE-NEXT: vmov.f32 s7, s6453; CHECKBE-NEXT: vrev64.32 q0, q1454; CHECKBE-NEXT: bx lr455entry:456 %out = shufflevector <4 x i32> %src1, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>457 ret <4 x i32> %out458}459 460 461 462 463define arm_aapcs_vfpcc <8 x i16> @vmovn16_t1(<8 x i16> %src1, <8 x i16> %src2) {464; CHECK-LABEL: vmovn16_t1:465; CHECK: @ %bb.0: @ %entry466; CHECK-NEXT: vmovnt.i32 q0, q1467; CHECK-NEXT: bx lr468;469; CHECKBE-LABEL: vmovn16_t1:470; CHECKBE: @ %bb.0: @ %entry471; CHECKBE-NEXT: vrev64.16 q2, q1472; CHECKBE-NEXT: vrev64.16 q1, q0473; CHECKBE-NEXT: vmovnt.i32 q1, q2474; CHECKBE-NEXT: vrev64.16 q0, q1475; CHECKBE-NEXT: bx lr476entry:477 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>478 ret <8 x i16> %out479}480 481define arm_aapcs_vfpcc <8 x i16> @vmovn16_t2(<8 x i16> %src1, <8 x i16> %src2) {482; CHECK-LABEL: vmovn16_t2:483; CHECK: @ %bb.0: @ %entry484; CHECK-NEXT: vmovnt.i32 q1, q0485; CHECK-NEXT: vmov q0, q1486; CHECK-NEXT: bx lr487;488; CHECKBE-LABEL: vmovn16_t2:489; CHECKBE: @ %bb.0: @ %entry490; CHECKBE-NEXT: vrev64.16 q2, q0491; CHECKBE-NEXT: vrev64.16 q3, q1492; CHECKBE-NEXT: vmovnt.i32 q3, q2493; CHECKBE-NEXT: vrev64.16 q0, q3494; CHECKBE-NEXT: bx lr495entry:496 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>497 ret <8 x i16> %out498}499 500define arm_aapcs_vfpcc <8 x i16> @vmovn16_b1(<8 x i16> %src1, <8 x i16> %src2) {501; CHECK-LABEL: vmovn16_b1:502; CHECK: @ %bb.0: @ %entry503; CHECK-NEXT: vmovnb.i32 q1, q0504; CHECK-NEXT: vmov q0, q1505; CHECK-NEXT: bx lr506;507; CHECKBE-LABEL: vmovn16_b1:508; CHECKBE: @ %bb.0: @ %entry509; CHECKBE-NEXT: vrev64.16 q2, q0510; CHECKBE-NEXT: vrev64.16 q3, q1511; CHECKBE-NEXT: vmovnb.i32 q3, q2512; CHECKBE-NEXT: vrev64.16 q0, q3513; CHECKBE-NEXT: bx lr514entry:515 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>516 ret <8 x i16> %out517}518 519define arm_aapcs_vfpcc <8 x i16> @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2) {520; CHECK-MVE-LABEL: vmovn16_b2:521; CHECK-MVE: @ %bb.0: @ %entry522; CHECK-MVE-NEXT: vmov q2, q0523; CHECK-MVE-NEXT: vmov.u16 r0, q1[1]524; CHECK-MVE-NEXT: vmov.16 q0[0], r0525; CHECK-MVE-NEXT: vmov.u16 r0, q2[0]526; CHECK-MVE-NEXT: vmov.16 q0[1], r0527; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]528; CHECK-MVE-NEXT: vmov.16 q0[2], r0529; CHECK-MVE-NEXT: vmov.u16 r0, q2[2]530; CHECK-MVE-NEXT: vmov.16 q0[3], r0531; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]532; CHECK-MVE-NEXT: vmov.16 q0[4], r0533; CHECK-MVE-NEXT: vmov.u16 r0, q2[4]534; CHECK-MVE-NEXT: vmov.16 q0[5], r0535; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]536; CHECK-MVE-NEXT: vmov.16 q0[6], r0537; CHECK-MVE-NEXT: vmov.u16 r0, q2[6]538; CHECK-MVE-NEXT: vmov.16 q0[7], r0539; CHECK-MVE-NEXT: bx lr540;541; CHECK-MVEFP-LABEL: vmovn16_b2:542; CHECK-MVEFP: @ %bb.0: @ %entry543; CHECK-MVEFP-NEXT: vmovx.f16 s4, s4544; CHECK-MVEFP-NEXT: vmovx.f16 s5, s5545; CHECK-MVEFP-NEXT: vmovx.f16 s6, s6546; CHECK-MVEFP-NEXT: vmovx.f16 s7, s7547; CHECK-MVEFP-NEXT: vins.f16 s4, s0548; CHECK-MVEFP-NEXT: vins.f16 s5, s1549; CHECK-MVEFP-NEXT: vins.f16 s6, s2550; CHECK-MVEFP-NEXT: vins.f16 s7, s3551; CHECK-MVEFP-NEXT: vmov q0, q1552; CHECK-MVEFP-NEXT: bx lr553;554; CHECKBE-LABEL: vmovn16_b2:555; CHECKBE: @ %bb.0: @ %entry556; CHECKBE-NEXT: vrev64.16 q2, q0557; CHECKBE-NEXT: vrev64.16 q0, q1558; CHECKBE-NEXT: vmovx.f16 s4, s0559; CHECKBE-NEXT: vmovx.f16 s5, s1560; CHECKBE-NEXT: vmovx.f16 s6, s2561; CHECKBE-NEXT: vmovx.f16 s7, s3562; CHECKBE-NEXT: vins.f16 s4, s8563; CHECKBE-NEXT: vins.f16 s5, s9564; CHECKBE-NEXT: vins.f16 s6, s10565; CHECKBE-NEXT: vins.f16 s7, s11566; CHECKBE-NEXT: vrev64.16 q0, q1567; CHECKBE-NEXT: bx lr568entry:569 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>570 ret <8 x i16> %out571}572 573define arm_aapcs_vfpcc <8 x i16> @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2) {574; CHECK-MVE-LABEL: vmovn16_b3:575; CHECK-MVE: @ %bb.0: @ %entry576; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]577; CHECK-MVE-NEXT: vmov q2, q0578; CHECK-MVE-NEXT: vmov.16 q0[0], r0579; CHECK-MVE-NEXT: vmov.u16 r0, q1[0]580; CHECK-MVE-NEXT: vmov.16 q0[1], r0581; CHECK-MVE-NEXT: vmov.u16 r0, q2[3]582; CHECK-MVE-NEXT: vmov.16 q0[2], r0583; CHECK-MVE-NEXT: vmov.u16 r0, q1[2]584; CHECK-MVE-NEXT: vmov.16 q0[3], r0585; CHECK-MVE-NEXT: vmov.u16 r0, q2[5]586; CHECK-MVE-NEXT: vmov.16 q0[4], r0587; CHECK-MVE-NEXT: vmov.u16 r0, q1[4]588; CHECK-MVE-NEXT: vmov.16 q0[5], r0589; CHECK-MVE-NEXT: vmov.u16 r0, q2[7]590; CHECK-MVE-NEXT: vmov.16 q0[6], r0591; CHECK-MVE-NEXT: vmov.u16 r0, q1[6]592; CHECK-MVE-NEXT: vmov.16 q0[7], r0593; CHECK-MVE-NEXT: bx lr594;595; CHECK-MVEFP-LABEL: vmovn16_b3:596; CHECK-MVEFP: @ %bb.0: @ %entry597; CHECK-MVEFP-NEXT: vmovx.f16 s0, s0598; CHECK-MVEFP-NEXT: vmovx.f16 s1, s1599; CHECK-MVEFP-NEXT: vmovx.f16 s2, s2600; CHECK-MVEFP-NEXT: vmovx.f16 s3, s3601; CHECK-MVEFP-NEXT: vins.f16 s0, s4602; CHECK-MVEFP-NEXT: vins.f16 s1, s5603; CHECK-MVEFP-NEXT: vins.f16 s2, s6604; CHECK-MVEFP-NEXT: vins.f16 s3, s7605; CHECK-MVEFP-NEXT: bx lr606;607; CHECKBE-LABEL: vmovn16_b3:608; CHECKBE: @ %bb.0: @ %entry609; CHECKBE-NEXT: vrev64.16 q2, q1610; CHECKBE-NEXT: vrev64.16 q1, q0611; CHECKBE-NEXT: vmovx.f16 s4, s4612; CHECKBE-NEXT: vmovx.f16 s5, s5613; CHECKBE-NEXT: vmovx.f16 s6, s6614; CHECKBE-NEXT: vmovx.f16 s7, s7615; CHECKBE-NEXT: vins.f16 s4, s8616; CHECKBE-NEXT: vins.f16 s5, s9617; CHECKBE-NEXT: vins.f16 s6, s10618; CHECKBE-NEXT: vins.f16 s7, s11619; CHECKBE-NEXT: vrev64.16 q0, q1620; CHECKBE-NEXT: bx lr621entry:622 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>623 ret <8 x i16> %out624}625 626define arm_aapcs_vfpcc <8 x i16> @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2) {627; CHECK-LABEL: vmovn16_b4:628; CHECK: @ %bb.0: @ %entry629; CHECK-NEXT: vmovnb.i32 q0, q1630; CHECK-NEXT: bx lr631;632; CHECKBE-LABEL: vmovn16_b4:633; CHECKBE: @ %bb.0: @ %entry634; CHECKBE-NEXT: vrev64.16 q2, q1635; CHECKBE-NEXT: vrev64.16 q1, q0636; CHECKBE-NEXT: vmovnb.i32 q1, q2637; CHECKBE-NEXT: vrev64.16 q0, q1638; CHECKBE-NEXT: bx lr639entry:640 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>641 ret <8 x i16> %out642}643 644define arm_aapcs_vfpcc <8 x i16> @vmovn16_single_t(<8 x i16> %src1) {645; CHECK-LABEL: vmovn16_single_t:646; CHECK: @ %bb.0: @ %entry647; CHECK-NEXT: vmovnt.i32 q0, q0648; CHECK-NEXT: bx lr649;650; CHECKBE-LABEL: vmovn16_single_t:651; CHECKBE: @ %bb.0: @ %entry652; CHECKBE-NEXT: vrev64.16 q1, q0653; CHECKBE-NEXT: vmovnt.i32 q1, q1654; CHECKBE-NEXT: vrev64.16 q0, q1655; CHECKBE-NEXT: bx lr656entry:657 %out = shufflevector <8 x i16> %src1, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>658 ret <8 x i16> %out659}660 661 662define arm_aapcs_vfpcc <16 x i8> @vmovn8_b1(<16 x i8> %src1, <16 x i8> %src2) {663; CHECK-LABEL: vmovn8_b1:664; CHECK: @ %bb.0: @ %entry665; CHECK-NEXT: vmovnt.i16 q0, q1666; CHECK-NEXT: bx lr667;668; CHECKBE-LABEL: vmovn8_b1:669; CHECKBE: @ %bb.0: @ %entry670; CHECKBE-NEXT: vrev64.8 q2, q1671; CHECKBE-NEXT: vrev64.8 q1, q0672; CHECKBE-NEXT: vmovnt.i16 q1, q2673; CHECKBE-NEXT: vrev64.8 q0, q1674; CHECKBE-NEXT: bx lr675entry:676 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>677 ret <16 x i8> %out678}679 680define arm_aapcs_vfpcc <16 x i8> @vmovn8_b2(<16 x i8> %src1, <16 x i8> %src2) {681; CHECK-LABEL: vmovn8_b2:682; CHECK: @ %bb.0: @ %entry683; CHECK-NEXT: vmovnt.i16 q1, q0684; CHECK-NEXT: vmov q0, q1685; CHECK-NEXT: bx lr686;687; CHECKBE-LABEL: vmovn8_b2:688; CHECKBE: @ %bb.0: @ %entry689; CHECKBE-NEXT: vrev64.8 q2, q0690; CHECKBE-NEXT: vrev64.8 q3, q1691; CHECKBE-NEXT: vmovnt.i16 q3, q2692; CHECKBE-NEXT: vrev64.8 q0, q3693; CHECKBE-NEXT: bx lr694entry:695 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>696 ret <16 x i8> %out697}698 699define arm_aapcs_vfpcc <16 x i8> @vmovn8_t1(<16 x i8> %src1, <16 x i8> %src2) {700; CHECK-LABEL: vmovn8_t1:701; CHECK: @ %bb.0: @ %entry702; CHECK-NEXT: vmovnb.i16 q1, q0703; CHECK-NEXT: vmov q0, q1704; CHECK-NEXT: bx lr705;706; CHECKBE-LABEL: vmovn8_t1:707; CHECKBE: @ %bb.0: @ %entry708; CHECKBE-NEXT: vrev64.8 q2, q0709; CHECKBE-NEXT: vrev64.8 q3, q1710; CHECKBE-NEXT: vmovnb.i16 q3, q2711; CHECKBE-NEXT: vrev64.8 q0, q3712; CHECKBE-NEXT: bx lr713entry:714 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>715 ret <16 x i8> %out716}717 718define arm_aapcs_vfpcc <16 x i8> @vmovn8_t2(<16 x i8> %src1, <16 x i8> %src2) {719; CHECK-LABEL: vmovn8_t2:720; CHECK: @ %bb.0: @ %entry721; CHECK-NEXT: vmov q2, q0722; CHECK-NEXT: vmov.u8 r0, q1[1]723; CHECK-NEXT: vmov.8 q0[0], r0724; CHECK-NEXT: vmov.u8 r0, q2[0]725; CHECK-NEXT: vmov.8 q0[1], r0726; CHECK-NEXT: vmov.u8 r0, q1[3]727; CHECK-NEXT: vmov.8 q0[2], r0728; CHECK-NEXT: vmov.u8 r0, q2[2]729; CHECK-NEXT: vmov.8 q0[3], r0730; CHECK-NEXT: vmov.u8 r0, q1[5]731; CHECK-NEXT: vmov.8 q0[4], r0732; CHECK-NEXT: vmov.u8 r0, q2[4]733; CHECK-NEXT: vmov.8 q0[5], r0734; CHECK-NEXT: vmov.u8 r0, q1[7]735; CHECK-NEXT: vmov.8 q0[6], r0736; CHECK-NEXT: vmov.u8 r0, q2[6]737; CHECK-NEXT: vmov.8 q0[7], r0738; CHECK-NEXT: vmov.u8 r0, q1[9]739; CHECK-NEXT: vmov.8 q0[8], r0740; CHECK-NEXT: vmov.u8 r0, q2[8]741; CHECK-NEXT: vmov.8 q0[9], r0742; CHECK-NEXT: vmov.u8 r0, q1[11]743; CHECK-NEXT: vmov.8 q0[10], r0744; CHECK-NEXT: vmov.u8 r0, q2[10]745; CHECK-NEXT: vmov.8 q0[11], r0746; CHECK-NEXT: vmov.u8 r0, q1[13]747; CHECK-NEXT: vmov.8 q0[12], r0748; CHECK-NEXT: vmov.u8 r0, q2[12]749; CHECK-NEXT: vmov.8 q0[13], r0750; CHECK-NEXT: vmov.u8 r0, q1[15]751; CHECK-NEXT: vmov.8 q0[14], r0752; CHECK-NEXT: vmov.u8 r0, q2[14]753; CHECK-NEXT: vmov.8 q0[15], r0754; CHECK-NEXT: bx lr755;756; CHECKBE-LABEL: vmovn8_t2:757; CHECKBE: @ %bb.0: @ %entry758; CHECKBE-NEXT: vrev64.8 q2, q1759; CHECKBE-NEXT: vrev64.8 q3, q0760; CHECKBE-NEXT: vmov.u8 r0, q2[1]761; CHECKBE-NEXT: vmov.8 q1[0], r0762; CHECKBE-NEXT: vmov.u8 r0, q3[0]763; CHECKBE-NEXT: vmov.8 q1[1], r0764; CHECKBE-NEXT: vmov.u8 r0, q2[3]765; CHECKBE-NEXT: vmov.8 q1[2], r0766; CHECKBE-NEXT: vmov.u8 r0, q3[2]767; CHECKBE-NEXT: vmov.8 q1[3], r0768; CHECKBE-NEXT: vmov.u8 r0, q2[5]769; CHECKBE-NEXT: vmov.8 q1[4], r0770; CHECKBE-NEXT: vmov.u8 r0, q3[4]771; CHECKBE-NEXT: vmov.8 q1[5], r0772; CHECKBE-NEXT: vmov.u8 r0, q2[7]773; CHECKBE-NEXT: vmov.8 q1[6], r0774; CHECKBE-NEXT: vmov.u8 r0, q3[6]775; CHECKBE-NEXT: vmov.8 q1[7], r0776; CHECKBE-NEXT: vmov.u8 r0, q2[9]777; CHECKBE-NEXT: vmov.8 q1[8], r0778; CHECKBE-NEXT: vmov.u8 r0, q3[8]779; CHECKBE-NEXT: vmov.8 q1[9], r0780; CHECKBE-NEXT: vmov.u8 r0, q2[11]781; CHECKBE-NEXT: vmov.8 q1[10], r0782; CHECKBE-NEXT: vmov.u8 r0, q3[10]783; CHECKBE-NEXT: vmov.8 q1[11], r0784; CHECKBE-NEXT: vmov.u8 r0, q2[13]785; CHECKBE-NEXT: vmov.8 q1[12], r0786; CHECKBE-NEXT: vmov.u8 r0, q3[12]787; CHECKBE-NEXT: vmov.8 q1[13], r0788; CHECKBE-NEXT: vmov.u8 r0, q2[15]789; CHECKBE-NEXT: vmov.8 q1[14], r0790; CHECKBE-NEXT: vmov.u8 r0, q3[14]791; CHECKBE-NEXT: vmov.8 q1[15], r0792; CHECKBE-NEXT: vrev64.8 q0, q1793; CHECKBE-NEXT: bx lr794entry:795 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 17, i32 0, i32 19, i32 2, i32 21, i32 4, i32 23, i32 6, i32 25, i32 8, i32 27, i32 10, i32 29, i32 12, i32 31, i32 14>796 ret <16 x i8> %out797}798 799define arm_aapcs_vfpcc <16 x i8> @vmovn8_t3(<16 x i8> %src1, <16 x i8> %src2) {800; CHECK-LABEL: vmovn8_t3:801; CHECK: @ %bb.0: @ %entry802; CHECK-NEXT: vmov.u8 r0, q0[1]803; CHECK-NEXT: vmov q2, q0804; CHECK-NEXT: vmov.8 q0[0], r0805; CHECK-NEXT: vmov.u8 r0, q1[0]806; CHECK-NEXT: vmov.8 q0[1], r0807; CHECK-NEXT: vmov.u8 r0, q2[3]808; CHECK-NEXT: vmov.8 q0[2], r0809; CHECK-NEXT: vmov.u8 r0, q1[2]810; CHECK-NEXT: vmov.8 q0[3], r0811; CHECK-NEXT: vmov.u8 r0, q2[5]812; CHECK-NEXT: vmov.8 q0[4], r0813; CHECK-NEXT: vmov.u8 r0, q1[4]814; CHECK-NEXT: vmov.8 q0[5], r0815; CHECK-NEXT: vmov.u8 r0, q2[7]816; CHECK-NEXT: vmov.8 q0[6], r0817; CHECK-NEXT: vmov.u8 r0, q1[6]818; CHECK-NEXT: vmov.8 q0[7], r0819; CHECK-NEXT: vmov.u8 r0, q2[9]820; CHECK-NEXT: vmov.8 q0[8], r0821; CHECK-NEXT: vmov.u8 r0, q1[8]822; CHECK-NEXT: vmov.8 q0[9], r0823; CHECK-NEXT: vmov.u8 r0, q2[11]824; CHECK-NEXT: vmov.8 q0[10], r0825; CHECK-NEXT: vmov.u8 r0, q1[10]826; CHECK-NEXT: vmov.8 q0[11], r0827; CHECK-NEXT: vmov.u8 r0, q2[13]828; CHECK-NEXT: vmov.8 q0[12], r0829; CHECK-NEXT: vmov.u8 r0, q1[12]830; CHECK-NEXT: vmov.8 q0[13], r0831; CHECK-NEXT: vmov.u8 r0, q2[15]832; CHECK-NEXT: vmov.8 q0[14], r0833; CHECK-NEXT: vmov.u8 r0, q1[14]834; CHECK-NEXT: vmov.8 q0[15], r0835; CHECK-NEXT: bx lr836;837; CHECKBE-LABEL: vmovn8_t3:838; CHECKBE: @ %bb.0: @ %entry839; CHECKBE-NEXT: vrev64.8 q3, q0840; CHECKBE-NEXT: vrev64.8 q0, q1841; CHECKBE-NEXT: vmov.u8 r0, q3[1]842; CHECKBE-NEXT: vmov.8 q2[0], r0843; CHECKBE-NEXT: vmov.u8 r0, q0[0]844; CHECKBE-NEXT: vmov.8 q2[1], r0845; CHECKBE-NEXT: vmov.u8 r0, q3[3]846; CHECKBE-NEXT: vmov.8 q2[2], r0847; CHECKBE-NEXT: vmov.u8 r0, q0[2]848; CHECKBE-NEXT: vmov.8 q2[3], r0849; CHECKBE-NEXT: vmov.u8 r0, q3[5]850; CHECKBE-NEXT: vmov.8 q2[4], r0851; CHECKBE-NEXT: vmov.u8 r0, q0[4]852; CHECKBE-NEXT: vmov.8 q2[5], r0853; CHECKBE-NEXT: vmov.u8 r0, q3[7]854; CHECKBE-NEXT: vmov.8 q2[6], r0855; CHECKBE-NEXT: vmov.u8 r0, q0[6]856; CHECKBE-NEXT: vmov.8 q2[7], r0857; CHECKBE-NEXT: vmov.u8 r0, q3[9]858; CHECKBE-NEXT: vmov.8 q2[8], r0859; CHECKBE-NEXT: vmov.u8 r0, q0[8]860; CHECKBE-NEXT: vmov.8 q2[9], r0861; CHECKBE-NEXT: vmov.u8 r0, q3[11]862; CHECKBE-NEXT: vmov.8 q2[10], r0863; CHECKBE-NEXT: vmov.u8 r0, q0[10]864; CHECKBE-NEXT: vmov.8 q2[11], r0865; CHECKBE-NEXT: vmov.u8 r0, q3[13]866; CHECKBE-NEXT: vmov.8 q2[12], r0867; CHECKBE-NEXT: vmov.u8 r0, q0[12]868; CHECKBE-NEXT: vmov.8 q2[13], r0869; CHECKBE-NEXT: vmov.u8 r0, q3[15]870; CHECKBE-NEXT: vmov.8 q2[14], r0871; CHECKBE-NEXT: vmov.u8 r0, q0[14]872; CHECKBE-NEXT: vmov.8 q2[15], r0873; CHECKBE-NEXT: vrev64.8 q0, q2874; CHECKBE-NEXT: bx lr875entry:876 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 1, i32 16, i32 3, i32 18, i32 5, i32 20, i32 7, i32 22, i32 9, i32 24, i32 11, i32 26, i32 13, i32 28, i32 15, i32 30>877 ret <16 x i8> %out878}879 880define arm_aapcs_vfpcc <16 x i8> @vmovn8_t4(<16 x i8> %src1, <16 x i8> %src2) {881; CHECK-LABEL: vmovn8_t4:882; CHECK: @ %bb.0: @ %entry883; CHECK-NEXT: vmovnb.i16 q0, q1884; CHECK-NEXT: bx lr885;886; CHECKBE-LABEL: vmovn8_t4:887; CHECKBE: @ %bb.0: @ %entry888; CHECKBE-NEXT: vrev64.8 q2, q1889; CHECKBE-NEXT: vrev64.8 q1, q0890; CHECKBE-NEXT: vmovnb.i16 q1, q2891; CHECKBE-NEXT: vrev64.8 q0, q1892; CHECKBE-NEXT: bx lr893entry:894 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>895 ret <16 x i8> %out896}897 898define arm_aapcs_vfpcc <16 x i8> @vmovn8_single_t(<16 x i8> %src1) {899; CHECK-LABEL: vmovn8_single_t:900; CHECK: @ %bb.0: @ %entry901; CHECK-NEXT: vmovnt.i16 q0, q0902; CHECK-NEXT: bx lr903;904; CHECKBE-LABEL: vmovn8_single_t:905; CHECKBE: @ %bb.0: @ %entry906; CHECKBE-NEXT: vrev64.8 q1, q0907; CHECKBE-NEXT: vmovnt.i16 q1, q1908; CHECKBE-NEXT: vrev64.8 q0, q1909; CHECKBE-NEXT: bx lr910entry:911 %out = shufflevector <16 x i8> %src1, <16 x i8> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>912 ret <16 x i8> %out913}914 915 916define arm_aapcs_vfpcc <8 x i16> @vmovn32trunct_undef2(<8 x i16> %a) {917; CHECK-LABEL: vmovn32trunct_undef2:918; CHECK: @ %bb.0: @ %entry919; CHECK-NEXT: bx lr920;921; CHECKBE-LABEL: vmovn32trunct_undef2:922; CHECKBE: @ %bb.0: @ %entry923; CHECKBE-NEXT: bx lr924entry:925 %c1 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %a)926 %c2 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> undef)927 %strided.vec = shufflevector <4 x i32> %c1, <4 x i32> %c2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>928 %out = trunc <8 x i32> %strided.vec to <8 x i16>929 ret <8 x i16> %out930}931 932define arm_aapcs_vfpcc <8 x i16> @vmovn32trunct_undef1(<8 x i16> %a) {933; CHECK-LABEL: vmovn32trunct_undef1:934; CHECK: @ %bb.0: @ %entry935; CHECK-NEXT: vmovnt.i32 q0, q0936; CHECK-NEXT: bx lr937;938; CHECKBE-LABEL: vmovn32trunct_undef1:939; CHECKBE: @ %bb.0: @ %entry940; CHECKBE-NEXT: vrev64.16 q1, q0941; CHECKBE-NEXT: vmovnt.i32 q1, q1942; CHECKBE-NEXT: vrev64.16 q0, q1943; CHECKBE-NEXT: bx lr944entry:945 %c1 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> undef)946 %c2 = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %a)947 %strided.vec = shufflevector <4 x i32> %c1, <4 x i32> %c2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>948 %out = trunc <8 x i32> %strided.vec to <8 x i16>949 ret <8 x i16> %out950}951 952define arm_aapcs_vfpcc <8 x i16> @vmovn16b_undef2(<16 x i8> %a) {953; CHECK-LABEL: vmovn16b_undef2:954; CHECK: @ %bb.0: @ %entry955; CHECK-NEXT: bx lr956;957; CHECKBE-LABEL: vmovn16b_undef2:958; CHECKBE: @ %bb.0: @ %entry959; CHECKBE-NEXT: vrev64.8 q1, q0960; CHECKBE-NEXT: vrev64.16 q0, q1961; CHECKBE-NEXT: bx lr962entry:963 %c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)964 %c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)965 %out = shufflevector <8 x i16> %c1, <8 x i16> %c2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>966 ret <8 x i16> %out967}968 969define arm_aapcs_vfpcc <8 x i16> @vmovn16b_undef1(<16 x i8> %a) {970; CHECK-LABEL: vmovn16b_undef1:971; CHECK: @ %bb.0: @ %entry972; CHECK-NEXT: bx lr973;974; CHECKBE-LABEL: vmovn16b_undef1:975; CHECKBE: @ %bb.0: @ %entry976; CHECKBE-NEXT: vrev64.8 q1, q0977; CHECKBE-NEXT: vrev64.16 q0, q1978; CHECKBE-NEXT: bx lr979entry:980 %c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)981 %c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)982 %out = shufflevector <8 x i16> %c1, <8 x i16> %c2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>983 ret <8 x i16> %out984}985 986define arm_aapcs_vfpcc <8 x i16> @vmovn32_badlanes(<4 x i32> %src1) {987; CHECK-MVE-LABEL: vmovn32_badlanes:988; CHECK-MVE: @ %bb.0: @ %entry989; CHECK-MVE-NEXT: vmov r0, r1, d0990; CHECK-MVE-NEXT: vmov.16 q1[1], r0991; CHECK-MVE-NEXT: vmov r0, s2992; CHECK-MVE-NEXT: vmov.16 q1[3], r1993; CHECK-MVE-NEXT: vmov.16 q1[5], r1994; CHECK-MVE-NEXT: vmov.16 q1[7], r0995; CHECK-MVE-NEXT: vmov q0, q1996; CHECK-MVE-NEXT: bx lr997;998; CHECK-MVEFP-LABEL: vmovn32_badlanes:999; CHECK-MVEFP: @ %bb.0: @ %entry1000; CHECK-MVEFP-NEXT: vmov r1, r2, d01001; CHECK-MVEFP-NEXT: vmov r0, s21002; CHECK-MVEFP-NEXT: vmov.16 q0[1], r11003; CHECK-MVEFP-NEXT: vmov.16 q0[3], r21004; CHECK-MVEFP-NEXT: vmov.16 q0[5], r21005; CHECK-MVEFP-NEXT: vmov.16 q0[7], r01006; CHECK-MVEFP-NEXT: bx lr1007;1008; CHECKBE-LABEL: vmovn32_badlanes:1009; CHECKBE: @ %bb.0: @ %entry1010; CHECKBE-NEXT: vrev64.32 q1, q01011; CHECKBE-NEXT: vmov r0, r1, d21012; CHECKBE-NEXT: vmov r2, s61013; CHECKBE-NEXT: vmov.16 q1[1], r01014; CHECKBE-NEXT: vmov.16 q1[3], r11015; CHECKBE-NEXT: vmov.16 q1[5], r11016; CHECKBE-NEXT: vmov.16 q1[7], r21017; CHECKBE-NEXT: vrev64.16 q0, q11018; CHECKBE-NEXT: bx lr1019entry:1020 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> undef, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 1, i32 7, i32 2>1021 %out = trunc <8 x i32> %strided.vec to <8 x i16>1022 ret <8 x i16> %out1023}1024 1025define arm_aapcs_vfpcc <16 x i8> @vmovn16trunct_undef2(<16 x i8> %a) {1026; CHECK-LABEL: vmovn16trunct_undef2:1027; CHECK: @ %bb.0: @ %entry1028; CHECK-NEXT: bx lr1029;1030; CHECKBE-LABEL: vmovn16trunct_undef2:1031; CHECKBE: @ %bb.0: @ %entry1032; CHECKBE-NEXT: bx lr1033entry:1034 %c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)1035 %c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)1036 %strided.vec = shufflevector <8 x i16> %c1, <8 x i16> %c2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>1037 %out = trunc <16 x i16> %strided.vec to <16 x i8>1038 ret <16 x i8> %out1039}1040 1041define arm_aapcs_vfpcc <16 x i8> @vmovn16trunct_undef1(<16 x i8> %a) {1042; CHECK-LABEL: vmovn16trunct_undef1:1043; CHECK: @ %bb.0: @ %entry1044; CHECK-NEXT: vmovnt.i16 q0, q01045; CHECK-NEXT: bx lr1046;1047; CHECKBE-LABEL: vmovn16trunct_undef1:1048; CHECKBE: @ %bb.0: @ %entry1049; CHECKBE-NEXT: vrev64.8 q1, q01050; CHECKBE-NEXT: vmovnt.i16 q1, q11051; CHECKBE-NEXT: vrev64.8 q0, q11052; CHECKBE-NEXT: bx lr1053entry:1054 %c1 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> undef)1055 %c2 = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)1056 %strided.vec = shufflevector <8 x i16> %c1, <8 x i16> %c2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>1057 %out = trunc <16 x i16> %strided.vec to <16 x i8>1058 ret <16 x i8> %out1059}1060 1061declare <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16>)1062declare <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8>)1063