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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP4 5define arm_aapcs_vfpcc void @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {6; CHECK-LABEL: vmovn32_trunc1:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmovnt.i32 q0, q19; CHECK-NEXT: vstrw.32 q0, [r0]10; CHECK-NEXT: bx lr11entry:12 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>13 %out = trunc <8 x i32> %strided.vec to <8 x i16>14 store <8 x i16> %out, ptr %dest, align 815 ret void16}17 18define arm_aapcs_vfpcc void @vmovn32_trunc2(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {19; CHECK-LABEL: vmovn32_trunc2:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vmovnt.i32 q1, q022; CHECK-NEXT: vstrw.32 q1, [r0]23; CHECK-NEXT: bx lr24entry:25 %strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>26 %out = trunc <8 x i32> %strided.vec to <8 x i16>27 store <8 x i16> %out, ptr %dest, align 828 ret void29}30 31define arm_aapcs_vfpcc void @vmovn32_trunc1_onesrc(<8 x i32> %src1, ptr %dest) {32; CHECK-LABEL: vmovn32_trunc1_onesrc:33; CHECK: @ %bb.0: @ %entry34; CHECK-NEXT: vmovnt.i32 q0, q135; CHECK-NEXT: vstrw.32 q0, [r0]36; CHECK-NEXT: bx lr37entry:38 %strided.vec = shufflevector <8 x i32> %src1, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>39 %out = trunc <8 x i32> %strided.vec to <8 x i16>40 store <8 x i16> %out, ptr %dest, align 841 ret void42}43 44define arm_aapcs_vfpcc void @vmovn32_trunc2_onesrc(<8 x i32> %src1, ptr %dest) {45; CHECK-LABEL: vmovn32_trunc2_onesrc:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vmovnt.i32 q1, q048; CHECK-NEXT: vstrw.32 q1, [r0]49; CHECK-NEXT: bx lr50entry:51 %strided.vec = shufflevector <8 x i32> %src1, <8 x i32> undef, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>52 %out = trunc <8 x i32> %strided.vec to <8 x i16>53 store <8 x i16> %out, ptr %dest, align 854 ret void55}56 57define arm_aapcs_vfpcc void @vmovn16_trunc1(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {58; CHECK-LABEL: vmovn16_trunc1:59; CHECK: @ %bb.0: @ %entry60; CHECK-NEXT: vmovnt.i16 q0, q161; CHECK-NEXT: vstrw.32 q0, [r0]62; CHECK-NEXT: bx lr63entry:64 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>65 %out = trunc <16 x i16> %strided.vec to <16 x i8>66 store <16 x i8> %out, ptr %dest, align 867 ret void68}69 70define arm_aapcs_vfpcc void @vmovn16_trunc2(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {71; CHECK-LABEL: vmovn16_trunc2:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: vmovnt.i16 q1, q074; CHECK-NEXT: vstrw.32 q1, [r0]75; CHECK-NEXT: bx lr76entry:77 %strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>78 %out = trunc <16 x i16> %strided.vec to <16 x i8>79 store <16 x i8> %out, ptr %dest, align 880 ret void81}82 83define arm_aapcs_vfpcc void @vmovn16_trunc1_onesrc(<16 x i16> %src1, ptr %dest) {84; CHECK-LABEL: vmovn16_trunc1_onesrc:85; CHECK: @ %bb.0: @ %entry86; CHECK-NEXT: vmovnt.i16 q0, q187; CHECK-NEXT: vstrw.32 q0, [r0]88; CHECK-NEXT: bx lr89entry:90 %strided.vec = shufflevector <16 x i16> %src1, <16 x i16> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>91 %out = trunc <16 x i16> %strided.vec to <16 x i8>92 store <16 x i8> %out, ptr %dest, align 893 ret void94}95 96define arm_aapcs_vfpcc void @vmovn16_trunc2_onesrc(<16 x i16> %src1, ptr %dest) {97; CHECK-LABEL: vmovn16_trunc2_onesrc:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: vmovnt.i16 q1, q0100; CHECK-NEXT: vstrw.32 q1, [r0]101; CHECK-NEXT: bx lr102entry:103 %strided.vec = shufflevector <16 x i16> %src1, <16 x i16> undef, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>104 %out = trunc <16 x i16> %strided.vec to <16 x i8>105 store <16 x i8> %out, ptr %dest, align 8106 ret void107}108 109 110define arm_aapcs_vfpcc void @vmovn64_t1(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) {111; CHECK-LABEL: vmovn64_t1:112; CHECK: @ %bb.0: @ %entry113; CHECK-NEXT: vmov.f32 s2, s4114; CHECK-NEXT: vmov.f32 s3, s5115; CHECK-NEXT: vstrw.32 q0, [r0]116; CHECK-NEXT: bx lr117entry:118 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 2>119 store <2 x i64> %out, ptr %dest, align 8120 ret void121}122 123define arm_aapcs_vfpcc void @vmovn64_t2(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) {124; CHECK-LABEL: vmovn64_t2:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vmov.f32 s6, s0127; CHECK-NEXT: vmov.f32 s7, s1128; CHECK-NEXT: vstrw.32 q1, [r0]129; CHECK-NEXT: bx lr130entry:131 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 0>132 store <2 x i64> %out, ptr %dest, align 8133 ret void134}135 136define arm_aapcs_vfpcc void @vmovn64_b1(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) {137; CHECK-LABEL: vmovn64_b1:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmov.f32 s2, s6140; CHECK-NEXT: vmov.f32 s3, s7141; CHECK-NEXT: vstrw.32 q0, [r0]142; CHECK-NEXT: bx lr143entry:144 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3>145 store <2 x i64> %out, ptr %dest, align 8146 ret void147}148 149define arm_aapcs_vfpcc void @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) {150; CHECK-LABEL: vmovn64_b2:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vmov.f32 s4, s6153; CHECK-NEXT: vmov.f32 s6, s0154; CHECK-NEXT: vmov.f32 s5, s7155; CHECK-NEXT: vmov.f32 s7, s1156; CHECK-NEXT: vstrw.32 q1, [r0]157; CHECK-NEXT: bx lr158entry:159 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0>160 store <2 x i64> %out, ptr %dest, align 8161 ret void162}163 164define arm_aapcs_vfpcc void @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) {165; CHECK-LABEL: vmovn64_b3:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vmov.f32 s0, s2168; CHECK-NEXT: vmov.f32 s2, s4169; CHECK-NEXT: vmov.f32 s1, s3170; CHECK-NEXT: vmov.f32 s3, s5171; CHECK-NEXT: vstrw.32 q0, [r0]172; CHECK-NEXT: bx lr173entry:174 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2>175 store <2 x i64> %out, ptr %dest, align 8176 ret void177}178 179define arm_aapcs_vfpcc void @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) {180; CHECK-LABEL: vmovn64_b4:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: vmov.f32 s6, s2183; CHECK-NEXT: vmov.f32 s7, s3184; CHECK-NEXT: vstrw.32 q1, [r0]185; CHECK-NEXT: bx lr186entry:187 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 1>188 store <2 x i64> %out, ptr %dest, align 8189 ret void190}191 192 193 194define arm_aapcs_vfpcc void @vmovn32_t1(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {195; CHECK-LABEL: vmovn32_t1:196; CHECK: @ %bb.0: @ %entry197; CHECK-NEXT: vmov.f32 s1, s4198; CHECK-NEXT: vmov.f32 s3, s6199; CHECK-NEXT: vstrw.32 q0, [r0]200; CHECK-NEXT: bx lr201entry:202 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>203 store <4 x i32> %out, ptr %dest, align 8204 ret void205}206 207define arm_aapcs_vfpcc void @vmovn32_t2(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {208; CHECK-LABEL: vmovn32_t2:209; CHECK: @ %bb.0: @ %entry210; CHECK-NEXT: vmov.f32 s5, s0211; CHECK-NEXT: vmov.f32 s7, s2212; CHECK-NEXT: vstrw.32 q1, [r0]213; CHECK-NEXT: bx lr214entry:215 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 0, i32 6, i32 2>216 store <4 x i32> %out, ptr %dest, align 8217 ret void218}219 220define arm_aapcs_vfpcc void @vmovn32_b1(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {221; CHECK-LABEL: vmovn32_b1:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmov.f32 s1, s5224; CHECK-NEXT: vmov.f32 s3, s7225; CHECK-NEXT: vstrw.32 q0, [r0]226; CHECK-NEXT: bx lr227entry:228 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>229 store <4 x i32> %out, ptr %dest, align 8230 ret void231}232 233define arm_aapcs_vfpcc void @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {234; CHECK-LABEL: vmovn32_b2:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: vmov.f32 s4, s5237; CHECK-NEXT: vmov.f32 s6, s7238; CHECK-NEXT: vmov.f32 s5, s0239; CHECK-NEXT: vmov.f32 s7, s2240; CHECK-NEXT: vstrw.32 q1, [r0]241; CHECK-NEXT: bx lr242entry:243 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2>244 store <4 x i32> %out, ptr %dest, align 8245 ret void246}247 248define arm_aapcs_vfpcc void @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {249; CHECK-LABEL: vmovn32_b3:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: vmov.f32 s0, s1252; CHECK-NEXT: vmov.f32 s2, s3253; CHECK-NEXT: vmov.f32 s1, s4254; CHECK-NEXT: vmov.f32 s3, s6255; CHECK-NEXT: vstrw.32 q0, [r0]256; CHECK-NEXT: bx lr257entry:258 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6>259 store <4 x i32> %out, ptr %dest, align 8260 ret void261}262 263define arm_aapcs_vfpcc void @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) {264; CHECK-LABEL: vmovn32_b4:265; CHECK: @ %bb.0: @ %entry266; CHECK-NEXT: vmov.f32 s5, s1267; CHECK-NEXT: vmov.f32 s7, s3268; CHECK-NEXT: vstrw.32 q1, [r0]269; CHECK-NEXT: bx lr270entry:271 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 6, i32 3>272 store <4 x i32> %out, ptr %dest, align 8273 ret void274}275 276 277 278 279define arm_aapcs_vfpcc void @vmovn16_t1(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {280; CHECK-LABEL: vmovn16_t1:281; CHECK: @ %bb.0: @ %entry282; CHECK-NEXT: vmovnt.i32 q0, q1283; CHECK-NEXT: vstrw.32 q0, [r0]284; CHECK-NEXT: bx lr285entry:286 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>287 store <8 x i16> %out, ptr %dest, align 8288 ret void289}290 291define arm_aapcs_vfpcc void @vmovn16_t2(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {292; CHECK-LABEL: vmovn16_t2:293; CHECK: @ %bb.0: @ %entry294; CHECK-NEXT: vmovnt.i32 q1, q0295; CHECK-NEXT: vstrw.32 q1, [r0]296; CHECK-NEXT: bx lr297entry:298 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>299 store <8 x i16> %out, ptr %dest, align 8300 ret void301}302 303define arm_aapcs_vfpcc void @vmovn16_b1(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {304; CHECK-LABEL: vmovn16_b1:305; CHECK: @ %bb.0: @ %entry306; CHECK-NEXT: vmovnb.i32 q1, q0307; CHECK-NEXT: vstrw.32 q1, [r0]308; CHECK-NEXT: bx lr309entry:310 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>311 store <8 x i16> %out, ptr %dest, align 8312 ret void313}314 315define arm_aapcs_vfpcc void @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {316; CHECK-MVE-LABEL: vmovn16_b2:317; CHECK-MVE: @ %bb.0: @ %entry318; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]319; CHECK-MVE-NEXT: vmov.16 q2[0], r1320; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]321; CHECK-MVE-NEXT: vmov.16 q2[1], r1322; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]323; CHECK-MVE-NEXT: vmov.16 q2[2], r1324; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]325; CHECK-MVE-NEXT: vmov.16 q2[3], r1326; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]327; CHECK-MVE-NEXT: vmov.16 q2[4], r1328; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]329; CHECK-MVE-NEXT: vmov.16 q2[5], r1330; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]331; CHECK-MVE-NEXT: vmov.16 q2[6], r1332; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]333; CHECK-MVE-NEXT: vmov.16 q2[7], r1334; CHECK-MVE-NEXT: vstrw.32 q2, [r0]335; CHECK-MVE-NEXT: bx lr336;337; CHECK-MVEFP-LABEL: vmovn16_b2:338; CHECK-MVEFP: @ %bb.0: @ %entry339; CHECK-MVEFP-NEXT: vmovx.f16 s4, s4340; CHECK-MVEFP-NEXT: vmovx.f16 s5, s5341; CHECK-MVEFP-NEXT: vmovx.f16 s6, s6342; CHECK-MVEFP-NEXT: vmovx.f16 s7, s7343; CHECK-MVEFP-NEXT: vins.f16 s4, s0344; CHECK-MVEFP-NEXT: vins.f16 s5, s1345; CHECK-MVEFP-NEXT: vins.f16 s6, s2346; CHECK-MVEFP-NEXT: vins.f16 s7, s3347; CHECK-MVEFP-NEXT: vstrw.32 q1, [r0]348; CHECK-MVEFP-NEXT: bx lr349entry:350 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>351 store <8 x i16> %out, ptr %dest, align 8352 ret void353}354 355define arm_aapcs_vfpcc void @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {356; CHECK-MVE-LABEL: vmovn16_b3:357; CHECK-MVE: @ %bb.0: @ %entry358; CHECK-MVE-NEXT: vmov.u16 r1, q0[1]359; CHECK-MVE-NEXT: vmov.16 q2[0], r1360; CHECK-MVE-NEXT: vmov.u16 r1, q1[0]361; CHECK-MVE-NEXT: vmov.16 q2[1], r1362; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]363; CHECK-MVE-NEXT: vmov.16 q2[2], r1364; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]365; CHECK-MVE-NEXT: vmov.16 q2[3], r1366; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]367; CHECK-MVE-NEXT: vmov.16 q2[4], r1368; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]369; CHECK-MVE-NEXT: vmov.16 q2[5], r1370; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]371; CHECK-MVE-NEXT: vmov.16 q2[6], r1372; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]373; CHECK-MVE-NEXT: vmov.16 q2[7], r1374; CHECK-MVE-NEXT: vstrw.32 q2, [r0]375; CHECK-MVE-NEXT: bx lr376;377; CHECK-MVEFP-LABEL: vmovn16_b3:378; CHECK-MVEFP: @ %bb.0: @ %entry379; CHECK-MVEFP-NEXT: vmovx.f16 s0, s0380; CHECK-MVEFP-NEXT: vmovx.f16 s1, s1381; CHECK-MVEFP-NEXT: vmovx.f16 s2, s2382; CHECK-MVEFP-NEXT: vmovx.f16 s3, s3383; CHECK-MVEFP-NEXT: vins.f16 s0, s4384; CHECK-MVEFP-NEXT: vins.f16 s1, s5385; CHECK-MVEFP-NEXT: vins.f16 s2, s6386; CHECK-MVEFP-NEXT: vins.f16 s3, s7387; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]388; CHECK-MVEFP-NEXT: bx lr389entry:390 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>391 store <8 x i16> %out, ptr %dest, align 8392 ret void393}394 395define arm_aapcs_vfpcc void @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) {396; CHECK-LABEL: vmovn16_b4:397; CHECK: @ %bb.0: @ %entry398; CHECK-NEXT: vmovnb.i32 q0, q1399; CHECK-NEXT: vstrw.32 q0, [r0]400; CHECK-NEXT: bx lr401entry:402 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>403 store <8 x i16> %out, ptr %dest, align 8404 ret void405}406 407 408define arm_aapcs_vfpcc void @vmovn8_b1(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) {409; CHECK-LABEL: vmovn8_b1:410; CHECK: @ %bb.0: @ %entry411; CHECK-NEXT: vmovnt.i16 q0, q1412; CHECK-NEXT: vstrw.32 q0, [r0]413; CHECK-NEXT: bx lr414entry:415 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>416 store <16 x i8> %out, ptr %dest, align 8417 ret void418}419 420define arm_aapcs_vfpcc void @vmovn8_b2(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) {421; CHECK-LABEL: vmovn8_b2:422; CHECK: @ %bb.0: @ %entry423; CHECK-NEXT: vmovnt.i16 q1, q0424; CHECK-NEXT: vstrw.32 q1, [r0]425; CHECK-NEXT: bx lr426entry:427 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>428 store <16 x i8> %out, ptr %dest, align 8429 ret void430}431 432define arm_aapcs_vfpcc void @vmovn8_t1(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) {433; CHECK-LABEL: vmovn8_t1:434; CHECK: @ %bb.0: @ %entry435; CHECK-NEXT: vmovnb.i16 q1, q0436; CHECK-NEXT: vstrw.32 q1, [r0]437; CHECK-NEXT: bx lr438entry:439 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>440 store <16 x i8> %out, ptr %dest, align 8441 ret void442}443 444define arm_aapcs_vfpcc void @vmovn8_t2(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) {445; CHECK-LABEL: vmovn8_t2:446; CHECK: @ %bb.0: @ %entry447; CHECK-NEXT: vmov.u8 r1, q1[1]448; CHECK-NEXT: vmov.8 q2[0], r1449; CHECK-NEXT: vmov.u8 r1, q0[0]450; CHECK-NEXT: vmov.8 q2[1], r1451; CHECK-NEXT: vmov.u8 r1, q1[3]452; CHECK-NEXT: vmov.8 q2[2], r1453; CHECK-NEXT: vmov.u8 r1, q0[2]454; CHECK-NEXT: vmov.8 q2[3], r1455; CHECK-NEXT: vmov.u8 r1, q1[5]456; CHECK-NEXT: vmov.8 q2[4], r1457; CHECK-NEXT: vmov.u8 r1, q0[4]458; CHECK-NEXT: vmov.8 q2[5], r1459; CHECK-NEXT: vmov.u8 r1, q1[7]460; CHECK-NEXT: vmov.8 q2[6], r1461; CHECK-NEXT: vmov.u8 r1, q0[6]462; CHECK-NEXT: vmov.8 q2[7], r1463; CHECK-NEXT: vmov.u8 r1, q1[9]464; CHECK-NEXT: vmov.8 q2[8], r1465; CHECK-NEXT: vmov.u8 r1, q0[8]466; CHECK-NEXT: vmov.8 q2[9], r1467; CHECK-NEXT: vmov.u8 r1, q1[11]468; CHECK-NEXT: vmov.8 q2[10], r1469; CHECK-NEXT: vmov.u8 r1, q0[10]470; CHECK-NEXT: vmov.8 q2[11], r1471; CHECK-NEXT: vmov.u8 r1, q1[13]472; CHECK-NEXT: vmov.8 q2[12], r1473; CHECK-NEXT: vmov.u8 r1, q0[12]474; CHECK-NEXT: vmov.8 q2[13], r1475; CHECK-NEXT: vmov.u8 r1, q1[15]476; CHECK-NEXT: vmov.8 q2[14], r1477; CHECK-NEXT: vmov.u8 r1, q0[14]478; CHECK-NEXT: vmov.8 q2[15], r1479; CHECK-NEXT: vstrw.32 q2, [r0]480; CHECK-NEXT: bx lr481entry:482 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 17, i32 0, i32 19, i32 2, i32 21, i32 4, i32 23, i32 6, i32 25, i32 8, i32 27, i32 10, i32 29, i32 12, i32 31, i32 14>483 store <16 x i8> %out, ptr %dest, align 8484 ret void485}486 487define arm_aapcs_vfpcc void @vmovn8_t3(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) {488; CHECK-LABEL: vmovn8_t3:489; CHECK: @ %bb.0: @ %entry490; CHECK-NEXT: vmov.u8 r1, q0[1]491; CHECK-NEXT: vmov.8 q2[0], r1492; CHECK-NEXT: vmov.u8 r1, q1[0]493; CHECK-NEXT: vmov.8 q2[1], r1494; CHECK-NEXT: vmov.u8 r1, q0[3]495; CHECK-NEXT: vmov.8 q2[2], r1496; CHECK-NEXT: vmov.u8 r1, q1[2]497; CHECK-NEXT: vmov.8 q2[3], r1498; CHECK-NEXT: vmov.u8 r1, q0[5]499; CHECK-NEXT: vmov.8 q2[4], r1500; CHECK-NEXT: vmov.u8 r1, q1[4]501; CHECK-NEXT: vmov.8 q2[5], r1502; CHECK-NEXT: vmov.u8 r1, q0[7]503; CHECK-NEXT: vmov.8 q2[6], r1504; CHECK-NEXT: vmov.u8 r1, q1[6]505; CHECK-NEXT: vmov.8 q2[7], r1506; CHECK-NEXT: vmov.u8 r1, q0[9]507; CHECK-NEXT: vmov.8 q2[8], r1508; CHECK-NEXT: vmov.u8 r1, q1[8]509; CHECK-NEXT: vmov.8 q2[9], r1510; CHECK-NEXT: vmov.u8 r1, q0[11]511; CHECK-NEXT: vmov.8 q2[10], r1512; CHECK-NEXT: vmov.u8 r1, q1[10]513; CHECK-NEXT: vmov.8 q2[11], r1514; CHECK-NEXT: vmov.u8 r1, q0[13]515; CHECK-NEXT: vmov.8 q2[12], r1516; CHECK-NEXT: vmov.u8 r1, q1[12]517; CHECK-NEXT: vmov.8 q2[13], r1518; CHECK-NEXT: vmov.u8 r1, q0[15]519; CHECK-NEXT: vmov.8 q2[14], r1520; CHECK-NEXT: vmov.u8 r1, q1[14]521; CHECK-NEXT: vmov.8 q2[15], r1522; CHECK-NEXT: vstrw.32 q2, [r0]523; CHECK-NEXT: bx lr524entry:525 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 1, i32 16, i32 3, i32 18, i32 5, i32 20, i32 7, i32 22, i32 9, i32 24, i32 11, i32 26, i32 13, i32 28, i32 15, i32 30>526 store <16 x i8> %out, ptr %dest, align 8527 ret void528}529 530define arm_aapcs_vfpcc void @vmovn8_t4(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) {531; CHECK-LABEL: vmovn8_t4:532; CHECK: @ %bb.0: @ %entry533; CHECK-NEXT: vmovnb.i16 q0, q1534; CHECK-NEXT: vstrw.32 q0, [r0]535; CHECK-NEXT: bx lr536entry:537 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>538 store <16 x i8> %out, ptr %dest, align 8539 ret void540}541