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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <2 x i64> @sext32_0246_0ext(<4 x i32> %src1, i32 %src2) {5; CHECK-LABEL: sext32_0246_0ext:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmov q2[2], q2[0], r0, r08; CHECK-NEXT: vmullb.s32 q1, q0, q29; CHECK-NEXT: vmov q0, q110; CHECK-NEXT: bx lr11entry:12 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>13 %out1 = sext <2 x i32> %shuf1 to <2 x i64>14 %ins = insertelement <4 x i32> poison, i32 %src2, i32 015 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer16 %out2 = sext <2 x i32> %shuf2 to <2 x i64>17 %out = mul <2 x i64> %out1, %out218 ret <2 x i64> %out19}20 21define arm_aapcs_vfpcc <2 x i64> @sext32_0ext_0246(<4 x i32> %src1, i32 %src2) {22; CHECK-LABEL: sext32_0ext_0246:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vmov q2[2], q2[0], r0, r025; CHECK-NEXT: vmullb.s32 q1, q2, q026; CHECK-NEXT: vmov q0, q127; CHECK-NEXT: bx lr28entry:29 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>30 %out1 = sext <2 x i32> %shuf1 to <2 x i64>31 %ins = insertelement <4 x i32> poison, i32 %src2, i32 032 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer33 %out2 = sext <2 x i32> %shuf2 to <2 x i64>34 %out = mul <2 x i64> %out2, %out135 ret <2 x i64> %out36}37 38define arm_aapcs_vfpcc <2 x i64> @sext32_0246_ext0(<4 x i32> %src1, i32 %src2) {39; CHECK-LABEL: sext32_0246_ext0:40; CHECK: @ %bb.0: @ %entry41; CHECK-NEXT: .save {r4, r5, r7, lr}42; CHECK-NEXT: push {r4, r5, r7, lr}43; CHECK-NEXT: vmov r1, s244; CHECK-NEXT: vmov r3, s045; CHECK-NEXT: umull lr, r12, r1, r046; CHECK-NEXT: umull r2, r5, r3, r047; CHECK-NEXT: vmov q0[2], q0[0], r2, lr48; CHECK-NEXT: asrs r2, r0, #3149; CHECK-NEXT: mla r4, r1, r2, r1250; CHECK-NEXT: asrs r1, r1, #3151; CHECK-NEXT: mla r2, r3, r2, r552; CHECK-NEXT: asrs r3, r3, #3153; CHECK-NEXT: mla r1, r1, r0, r454; CHECK-NEXT: mla r0, r3, r0, r255; CHECK-NEXT: vmov q0[3], q0[1], r0, r156; CHECK-NEXT: pop {r4, r5, r7, pc}57entry:58 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>59 %out1 = sext <2 x i32> %shuf1 to <2 x i64>60 %ext = sext i32 %src2 to i6461 %ins = insertelement <2 x i64> poison, i64 %ext, i32 062 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer63 %out = mul <2 x i64> %out1, %shuf264 ret <2 x i64> %out65}66 67define arm_aapcs_vfpcc <2 x i64> @sext32_ext0_0246(<4 x i32> %src1, i32 %src2) {68; CHECK-LABEL: sext32_ext0_0246:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: .save {r4, r5, r7, lr}71; CHECK-NEXT: push {r4, r5, r7, lr}72; CHECK-NEXT: vmov r1, s273; CHECK-NEXT: asrs r4, r0, #3174; CHECK-NEXT: vmov r3, s075; CHECK-NEXT: umull lr, r12, r0, r176; CHECK-NEXT: umull r2, r5, r0, r377; CHECK-NEXT: vmov q0[2], q0[0], r2, lr78; CHECK-NEXT: asrs r2, r1, #3179; CHECK-NEXT: mla r2, r0, r2, r1280; CHECK-NEXT: mla r1, r4, r1, r281; CHECK-NEXT: asrs r2, r3, #3182; CHECK-NEXT: mla r0, r0, r2, r583; CHECK-NEXT: mla r0, r4, r3, r084; CHECK-NEXT: vmov q0[3], q0[1], r0, r185; CHECK-NEXT: pop {r4, r5, r7, pc}86entry:87 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>88 %out1 = sext <2 x i32> %shuf1 to <2 x i64>89 %ext = sext i32 %src2 to i6490 %ins = insertelement <2 x i64> poison, i64 %ext, i32 091 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer92 %out = mul <2 x i64> %shuf2, %out193 ret <2 x i64> %out94}95 96define arm_aapcs_vfpcc <2 x i64> @sext32_1357_0ext(<4 x i32> %src1, i32 %src2) {97; CHECK-LABEL: sext32_1357_0ext:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: vmov q1[2], q1[0], r0, r0100; CHECK-NEXT: vrev64.32 q2, q0101; CHECK-NEXT: vmullb.s32 q0, q2, q1102; CHECK-NEXT: bx lr103entry:104 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>105 %out1 = sext <2 x i32> %shuf1 to <2 x i64>106 %ins = insertelement <4 x i32> poison, i32 %src2, i32 0107 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer108 %out2 = sext <2 x i32> %shuf2 to <2 x i64>109 %out = mul <2 x i64> %out1, %out2110 ret <2 x i64> %out111}112 113define arm_aapcs_vfpcc <2 x i64> @sext32_0ext_1357(<4 x i32> %src1, i32 %src2) {114; CHECK-LABEL: sext32_0ext_1357:115; CHECK: @ %bb.0: @ %entry116; CHECK-NEXT: vrev64.32 q1, q0117; CHECK-NEXT: vmov q2[2], q2[0], r0, r0118; CHECK-NEXT: vmullb.s32 q0, q2, q1119; CHECK-NEXT: bx lr120entry:121 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>122 %out1 = sext <2 x i32> %shuf1 to <2 x i64>123 %ins = insertelement <4 x i32> poison, i32 %src2, i32 0124 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer125 %out2 = sext <2 x i32> %shuf2 to <2 x i64>126 %out = mul <2 x i64> %out2, %out1127 ret <2 x i64> %out128}129 130define arm_aapcs_vfpcc <2 x i64> @sext32_1357_ext0(<4 x i32> %src1, i32 %src2) {131; CHECK-LABEL: sext32_1357_ext0:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: .save {r4, r5, r7, lr}134; CHECK-NEXT: push {r4, r5, r7, lr}135; CHECK-NEXT: vrev64.32 q1, q0136; CHECK-NEXT: vmov r1, s6137; CHECK-NEXT: vmov r3, s4138; CHECK-NEXT: umull lr, r12, r1, r0139; CHECK-NEXT: umull r2, r5, r3, r0140; CHECK-NEXT: vmov q0[2], q0[0], r2, lr141; CHECK-NEXT: asrs r2, r0, #31142; CHECK-NEXT: mla r4, r1, r2, r12143; CHECK-NEXT: asrs r1, r1, #31144; CHECK-NEXT: mla r2, r3, r2, r5145; CHECK-NEXT: asrs r3, r3, #31146; CHECK-NEXT: mla r1, r1, r0, r4147; CHECK-NEXT: mla r0, r3, r0, r2148; CHECK-NEXT: vmov q0[3], q0[1], r0, r1149; CHECK-NEXT: pop {r4, r5, r7, pc}150entry:151 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>152 %out1 = sext <2 x i32> %shuf1 to <2 x i64>153 %ext = sext i32 %src2 to i64154 %ins = insertelement <2 x i64> poison, i64 %ext, i32 0155 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer156 %out = mul <2 x i64> %out1, %shuf2157 ret <2 x i64> %out158}159 160define arm_aapcs_vfpcc <2 x i64> @sext32_ext0_1357(<4 x i32> %src1, i32 %src2) {161; CHECK-LABEL: sext32_ext0_1357:162; CHECK: @ %bb.0: @ %entry163; CHECK-NEXT: .save {r4, r5, r7, lr}164; CHECK-NEXT: push {r4, r5, r7, lr}165; CHECK-NEXT: vrev64.32 q1, q0166; CHECK-NEXT: asrs r4, r0, #31167; CHECK-NEXT: vmov r1, s6168; CHECK-NEXT: vmov r3, s4169; CHECK-NEXT: umull lr, r12, r0, r1170; CHECK-NEXT: umull r2, r5, r0, r3171; CHECK-NEXT: vmov q0[2], q0[0], r2, lr172; CHECK-NEXT: asrs r2, r1, #31173; CHECK-NEXT: mla r2, r0, r2, r12174; CHECK-NEXT: mla r1, r4, r1, r2175; CHECK-NEXT: asrs r2, r3, #31176; CHECK-NEXT: mla r0, r0, r2, r5177; CHECK-NEXT: mla r0, r4, r3, r0178; CHECK-NEXT: vmov q0[3], q0[1], r0, r1179; CHECK-NEXT: pop {r4, r5, r7, pc}180entry:181 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>182 %out1 = sext <2 x i32> %shuf1 to <2 x i64>183 %ext = sext i32 %src2 to i64184 %ins = insertelement <2 x i64> poison, i64 %ext, i32 0185 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer186 %out = mul <2 x i64> %shuf2, %out1187 ret <2 x i64> %out188}189 190define arm_aapcs_vfpcc <4 x i64> @sext32_0213_0ext(<8 x i32> %src1, i32 %src2) {191; CHECK-LABEL: sext32_0213_0ext:192; CHECK: @ %bb.0: @ %entry193; CHECK-NEXT: .vsave {d8, d9}194; CHECK-NEXT: vpush {d8, d9}195; CHECK-NEXT: vmov q4, q0196; CHECK-NEXT: vmov q3[2], q3[0], r0, r0197; CHECK-NEXT: vmov.f32 s17, s4198; CHECK-NEXT: vmov.f32 s0, s1199; CHECK-NEXT: vmullb.s32 q2, q4, q3200; CHECK-NEXT: vmov.f32 s2, s3201; CHECK-NEXT: vmullb.s32 q1, q0, q3202; CHECK-NEXT: vmov q0, q2203; CHECK-NEXT: vpop {d8, d9}204; CHECK-NEXT: bx lr205entry:206 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>207 %out1 = sext <4 x i32> %shuf1 to <4 x i64>208 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0209 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer210 %out2 = sext <4 x i32> %shuf2 to <4 x i64>211 %out = mul <4 x i64> %out1, %out2212 ret <4 x i64> %out213}214 215define arm_aapcs_vfpcc <4 x i64> @sext32_0ext_0213(<8 x i32> %src1, i32 %src2) {216; CHECK-LABEL: sext32_0ext_0213:217; CHECK: @ %bb.0: @ %entry218; CHECK-NEXT: .vsave {d8, d9}219; CHECK-NEXT: vpush {d8, d9}220; CHECK-NEXT: vmov q4, q0221; CHECK-NEXT: vmov q3[2], q3[0], r0, r0222; CHECK-NEXT: vmov.f32 s17, s4223; CHECK-NEXT: vmov.f32 s0, s1224; CHECK-NEXT: vmullb.s32 q2, q3, q4225; CHECK-NEXT: vmov.f32 s2, s3226; CHECK-NEXT: vmullb.s32 q1, q3, q0227; CHECK-NEXT: vmov q0, q2228; CHECK-NEXT: vpop {d8, d9}229; CHECK-NEXT: bx lr230entry:231 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>232 %out1 = sext <4 x i32> %shuf1 to <4 x i64>233 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0234 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer235 %out2 = sext <4 x i32> %shuf2 to <4 x i64>236 %out = mul <4 x i64> %out2, %out1237 ret <4 x i64> %out238}239 240define arm_aapcs_vfpcc <4 x i64> @sext32_0213_ext0(<8 x i32> %src1, i32 %src2) {241; CHECK-LABEL: sext32_0213_ext0:242; CHECK: @ %bb.0: @ %entry243; CHECK-NEXT: .save {r4, r5, r7, lr}244; CHECK-NEXT: push {r4, r5, r7, lr}245; CHECK-NEXT: vmov.f32 s4, s1246; CHECK-NEXT: vmov.f32 s6, s3247; CHECK-NEXT: vmov r3, s4248; CHECK-NEXT: vmov r1, s6249; CHECK-NEXT: umull r2, r5, r3, r0250; CHECK-NEXT: umull lr, r12, r1, r0251; CHECK-NEXT: vmov q1[2], q1[0], r2, lr252; CHECK-NEXT: asrs r2, r0, #31253; CHECK-NEXT: mla r4, r1, r2, r12254; CHECK-NEXT: asrs r1, r1, #31255; CHECK-NEXT: mla r5, r3, r2, r5256; CHECK-NEXT: asrs r3, r3, #31257; CHECK-NEXT: mla r1, r1, r0, r4258; CHECK-NEXT: mla r3, r3, r0, r5259; CHECK-NEXT: vmov q1[3], q1[1], r3, r1260; CHECK-NEXT: vmov r1, s2261; CHECK-NEXT: umull r3, r5, r1, r0262; CHECK-NEXT: mla r5, r1, r2, r5263; CHECK-NEXT: asrs r1, r1, #31264; CHECK-NEXT: mla r12, r1, r0, r5265; CHECK-NEXT: vmov r5, s0266; CHECK-NEXT: umull r4, r1, r5, r0267; CHECK-NEXT: mla r1, r5, r2, r1268; CHECK-NEXT: asrs r2, r5, #31269; CHECK-NEXT: vmov q0[2], q0[0], r4, r3270; CHECK-NEXT: mla r0, r2, r0, r1271; CHECK-NEXT: vmov q0[3], q0[1], r0, r12272; CHECK-NEXT: pop {r4, r5, r7, pc}273entry:274 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>275 %out1 = sext <4 x i32> %shuf1 to <4 x i64>276 %ext = sext i32 %src2 to i64277 %ins = insertelement <4 x i64> poison, i64 %ext, i32 0278 %shuf2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer279 %out = mul <4 x i64> %out1, %shuf2280 ret <4 x i64> %out281}282 283define arm_aapcs_vfpcc <4 x i64> @sext32_ext0_0213(<8 x i32> %src1, i32 %src2) {284; CHECK-LABEL: sext32_ext0_0213:285; CHECK: @ %bb.0: @ %entry286; CHECK-NEXT: .save {r4, r5, r7, lr}287; CHECK-NEXT: push {r4, r5, r7, lr}288; CHECK-NEXT: vmov.f32 s4, s1289; CHECK-NEXT: asrs r4, r0, #31290; CHECK-NEXT: vmov.f32 s6, s3291; CHECK-NEXT: vmov r3, s4292; CHECK-NEXT: vmov r1, s6293; CHECK-NEXT: umull r2, r5, r0, r3294; CHECK-NEXT: umull lr, r12, r0, r1295; CHECK-NEXT: vmov q1[2], q1[0], r2, lr296; CHECK-NEXT: asrs r2, r1, #31297; CHECK-NEXT: mla r2, r0, r2, r12298; CHECK-NEXT: mla r1, r4, r1, r2299; CHECK-NEXT: asrs r2, r3, #31300; CHECK-NEXT: mla r2, r0, r2, r5301; CHECK-NEXT: mla r2, r4, r3, r2302; CHECK-NEXT: vmov q1[3], q1[1], r2, r1303; CHECK-NEXT: vmov r1, s2304; CHECK-NEXT: umull r2, r3, r0, r1305; CHECK-NEXT: asrs r5, r1, #31306; CHECK-NEXT: mla r3, r0, r5, r3307; CHECK-NEXT: mla r12, r4, r1, r3308; CHECK-NEXT: vmov r3, s0309; CHECK-NEXT: umull r5, r1, r0, r3310; CHECK-NEXT: vmov q0[2], q0[0], r5, r2311; CHECK-NEXT: asrs r2, r3, #31312; CHECK-NEXT: mla r0, r0, r2, r1313; CHECK-NEXT: mla r0, r4, r3, r0314; CHECK-NEXT: vmov q0[3], q0[1], r0, r12315; CHECK-NEXT: pop {r4, r5, r7, pc}316entry:317 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>318 %out1 = sext <4 x i32> %shuf1 to <4 x i64>319 %ext = sext i32 %src2 to i64320 %ins = insertelement <4 x i64> poison, i64 %ext, i32 0321 %shuf2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer322 %out = mul <4 x i64> %shuf2, %out1323 ret <4 x i64> %out324}325 326define arm_aapcs_vfpcc <2 x i64> @zext32_0246_0ext(<4 x i32> %src1, i32 %src2) {327; CHECK-LABEL: zext32_0246_0ext:328; CHECK: @ %bb.0: @ %entry329; CHECK-NEXT: vmov q2[2], q2[0], r0, r0330; CHECK-NEXT: vmullb.u32 q1, q0, q2331; CHECK-NEXT: vmov q0, q1332; CHECK-NEXT: bx lr333entry:334 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>335 %out1 = zext <2 x i32> %shuf1 to <2 x i64>336 %ins = insertelement <4 x i32> poison, i32 %src2, i32 0337 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer338 %out2 = zext <2 x i32> %shuf2 to <2 x i64>339 %out = mul <2 x i64> %out1, %out2340 ret <2 x i64> %out341}342 343define arm_aapcs_vfpcc <2 x i64> @zext32_0ext_0246(<4 x i32> %src1, i32 %src2) {344; CHECK-LABEL: zext32_0ext_0246:345; CHECK: @ %bb.0: @ %entry346; CHECK-NEXT: vmov q2[2], q2[0], r0, r0347; CHECK-NEXT: vmullb.u32 q1, q2, q0348; CHECK-NEXT: vmov q0, q1349; CHECK-NEXT: bx lr350entry:351 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>352 %out1 = zext <2 x i32> %shuf1 to <2 x i64>353 %ins = insertelement <4 x i32> poison, i32 %src2, i32 0354 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer355 %out2 = zext <2 x i32> %shuf2 to <2 x i64>356 %out = mul <2 x i64> %out2, %out1357 ret <2 x i64> %out358}359 360define arm_aapcs_vfpcc <2 x i64> @zext32_0246_ext0(<4 x i32> %src1, i32 %src2) {361; CHECK-LABEL: zext32_0246_ext0:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: vmov r1, s2364; CHECK-NEXT: vmov r3, s0365; CHECK-NEXT: umull r1, r2, r1, r0366; CHECK-NEXT: umull r0, r3, r3, r0367; CHECK-NEXT: vmov q0[2], q0[0], r0, r1368; CHECK-NEXT: vmov q0[3], q0[1], r3, r2369; CHECK-NEXT: bx lr370entry:371 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>372 %out1 = zext <2 x i32> %shuf1 to <2 x i64>373 %ext = zext i32 %src2 to i64374 %ins = insertelement <2 x i64> poison, i64 %ext, i32 0375 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer376 %out = mul <2 x i64> %out1, %shuf2377 ret <2 x i64> %out378}379 380define arm_aapcs_vfpcc <2 x i64> @zext32_ext0_0246(<4 x i32> %src1, i32 %src2) {381; CHECK-LABEL: zext32_ext0_0246:382; CHECK: @ %bb.0: @ %entry383; CHECK-NEXT: vmov r1, s2384; CHECK-NEXT: vmov r3, s0385; CHECK-NEXT: umull r1, r2, r0, r1386; CHECK-NEXT: umull r0, r3, r0, r3387; CHECK-NEXT: vmov q0[2], q0[0], r0, r1388; CHECK-NEXT: vmov q0[3], q0[1], r3, r2389; CHECK-NEXT: bx lr390entry:391 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>392 %out1 = zext <2 x i32> %shuf1 to <2 x i64>393 %ext = zext i32 %src2 to i64394 %ins = insertelement <2 x i64> poison, i64 %ext, i32 0395 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer396 %out = mul <2 x i64> %shuf2, %out1397 ret <2 x i64> %out398}399 400define arm_aapcs_vfpcc <2 x i64> @zext32_1357_0ext(<4 x i32> %src1, i32 %src2) {401; CHECK-LABEL: zext32_1357_0ext:402; CHECK: @ %bb.0: @ %entry403; CHECK-NEXT: vmov q1[2], q1[0], r0, r0404; CHECK-NEXT: vrev64.32 q2, q0405; CHECK-NEXT: vmullb.u32 q0, q2, q1406; CHECK-NEXT: bx lr407entry:408 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>409 %out1 = zext <2 x i32> %shuf1 to <2 x i64>410 %ins = insertelement <4 x i32> poison, i32 %src2, i32 0411 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer412 %out2 = zext <2 x i32> %shuf2 to <2 x i64>413 %out = mul <2 x i64> %out1, %out2414 ret <2 x i64> %out415}416 417define arm_aapcs_vfpcc <2 x i64> @zext32_0ext_1357(<4 x i32> %src1, i32 %src2) {418; CHECK-LABEL: zext32_0ext_1357:419; CHECK: @ %bb.0: @ %entry420; CHECK-NEXT: vrev64.32 q1, q0421; CHECK-NEXT: vmov q2[2], q2[0], r0, r0422; CHECK-NEXT: vmullb.u32 q0, q2, q1423; CHECK-NEXT: bx lr424entry:425 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>426 %out1 = zext <2 x i32> %shuf1 to <2 x i64>427 %ins = insertelement <4 x i32> poison, i32 %src2, i32 0428 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <2 x i32> zeroinitializer429 %out2 = zext <2 x i32> %shuf2 to <2 x i64>430 %out = mul <2 x i64> %out2, %out1431 ret <2 x i64> %out432}433 434define arm_aapcs_vfpcc <2 x i64> @zext32_1357_ext0(<4 x i32> %src1, i32 %src2) {435; CHECK-LABEL: zext32_1357_ext0:436; CHECK: @ %bb.0: @ %entry437; CHECK-NEXT: vrev64.32 q1, q0438; CHECK-NEXT: vmov r1, s6439; CHECK-NEXT: vmov r3, s4440; CHECK-NEXT: umull r1, r2, r1, r0441; CHECK-NEXT: umull r0, r3, r3, r0442; CHECK-NEXT: vmov q0[2], q0[0], r0, r1443; CHECK-NEXT: vmov q0[3], q0[1], r3, r2444; CHECK-NEXT: bx lr445entry:446 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>447 %out1 = zext <2 x i32> %shuf1 to <2 x i64>448 %ext = zext i32 %src2 to i64449 %ins = insertelement <2 x i64> poison, i64 %ext, i32 0450 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer451 %out = mul <2 x i64> %out1, %shuf2452 ret <2 x i64> %out453}454 455define arm_aapcs_vfpcc <2 x i64> @zext32_ext0_1357(<4 x i32> %src1, i32 %src2) {456; CHECK-LABEL: zext32_ext0_1357:457; CHECK: @ %bb.0: @ %entry458; CHECK-NEXT: vrev64.32 q1, q0459; CHECK-NEXT: vmov r1, s6460; CHECK-NEXT: vmov r3, s4461; CHECK-NEXT: umull r1, r2, r0, r1462; CHECK-NEXT: umull r0, r3, r0, r3463; CHECK-NEXT: vmov q0[2], q0[0], r0, r1464; CHECK-NEXT: vmov q0[3], q0[1], r3, r2465; CHECK-NEXT: bx lr466entry:467 %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>468 %out1 = zext <2 x i32> %shuf1 to <2 x i64>469 %ext = zext i32 %src2 to i64470 %ins = insertelement <2 x i64> poison, i64 %ext, i32 0471 %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer472 %out = mul <2 x i64> %shuf2, %out1473 ret <2 x i64> %out474}475 476define arm_aapcs_vfpcc <4 x i64> @zext32_0213_0ext(<8 x i32> %src1, i32 %src2) {477; CHECK-LABEL: zext32_0213_0ext:478; CHECK: @ %bb.0: @ %entry479; CHECK-NEXT: .vsave {d8, d9}480; CHECK-NEXT: vpush {d8, d9}481; CHECK-NEXT: vmov q4, q0482; CHECK-NEXT: vmov q3[2], q3[0], r0, r0483; CHECK-NEXT: vmov.f32 s17, s4484; CHECK-NEXT: vmov.f32 s0, s1485; CHECK-NEXT: vmullb.u32 q2, q4, q3486; CHECK-NEXT: vmov.f32 s2, s3487; CHECK-NEXT: vmullb.u32 q1, q0, q3488; CHECK-NEXT: vmov q0, q2489; CHECK-NEXT: vpop {d8, d9}490; CHECK-NEXT: bx lr491entry:492 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>493 %out1 = zext <4 x i32> %shuf1 to <4 x i64>494 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0495 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer496 %out2 = zext <4 x i32> %shuf2 to <4 x i64>497 %out = mul <4 x i64> %out1, %out2498 ret <4 x i64> %out499}500 501define arm_aapcs_vfpcc <4 x i64> @zext32_0ext_0213(<8 x i32> %src1, i32 %src2) {502; CHECK-LABEL: zext32_0ext_0213:503; CHECK: @ %bb.0: @ %entry504; CHECK-NEXT: .vsave {d8, d9}505; CHECK-NEXT: vpush {d8, d9}506; CHECK-NEXT: vmov q4, q0507; CHECK-NEXT: vmov q3[2], q3[0], r0, r0508; CHECK-NEXT: vmov.f32 s17, s4509; CHECK-NEXT: vmov.f32 s0, s1510; CHECK-NEXT: vmullb.u32 q2, q3, q4511; CHECK-NEXT: vmov.f32 s2, s3512; CHECK-NEXT: vmullb.u32 q1, q3, q0513; CHECK-NEXT: vmov q0, q2514; CHECK-NEXT: vpop {d8, d9}515; CHECK-NEXT: bx lr516entry:517 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>518 %out1 = zext <4 x i32> %shuf1 to <4 x i64>519 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0520 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer521 %out2 = zext <4 x i32> %shuf2 to <4 x i64>522 %out = mul <4 x i64> %out2, %out1523 ret <4 x i64> %out524}525 526define arm_aapcs_vfpcc <4 x i64> @zext32_0213_ext0(<8 x i32> %src1, i32 %src2) {527; CHECK-LABEL: zext32_0213_ext0:528; CHECK: @ %bb.0: @ %entry529; CHECK-NEXT: vmov r1, s2530; CHECK-NEXT: vmov r3, s0531; CHECK-NEXT: vmov.f32 s0, s1532; CHECK-NEXT: vmov.f32 s2, s3533; CHECK-NEXT: umull r1, r12, r1, r0534; CHECK-NEXT: umull r3, r2, r3, r0535; CHECK-NEXT: vmov q2[2], q2[0], r3, r1536; CHECK-NEXT: vmov r1, s2537; CHECK-NEXT: vmov r3, s0538; CHECK-NEXT: vmov q2[3], q2[1], r2, r12539; CHECK-NEXT: vmov q0, q2540; CHECK-NEXT: umull r1, r2, r1, r0541; CHECK-NEXT: umull r0, r3, r3, r0542; CHECK-NEXT: vmov q1[2], q1[0], r0, r1543; CHECK-NEXT: vmov q1[3], q1[1], r3, r2544; CHECK-NEXT: bx lr545entry:546 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>547 %out1 = zext <4 x i32> %shuf1 to <4 x i64>548 %ext = zext i32 %src2 to i64549 %ins = insertelement <4 x i64> poison, i64 %ext, i32 0550 %shuf2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer551 %out = mul <4 x i64> %out1, %shuf2552 ret <4 x i64> %out553}554 555define arm_aapcs_vfpcc <4 x i64> @zext32_ext0_0213(<8 x i32> %src1, i32 %src2) {556; CHECK-LABEL: zext32_ext0_0213:557; CHECK: @ %bb.0: @ %entry558; CHECK-NEXT: vmov r1, s2559; CHECK-NEXT: vmov r3, s0560; CHECK-NEXT: vmov.f32 s0, s1561; CHECK-NEXT: vmov.f32 s2, s3562; CHECK-NEXT: umull r1, r12, r0, r1563; CHECK-NEXT: umull r3, r2, r0, r3564; CHECK-NEXT: vmov q2[2], q2[0], r3, r1565; CHECK-NEXT: vmov r1, s2566; CHECK-NEXT: vmov r3, s0567; CHECK-NEXT: vmov q2[3], q2[1], r2, r12568; CHECK-NEXT: vmov q0, q2569; CHECK-NEXT: umull r1, r2, r0, r1570; CHECK-NEXT: umull r0, r3, r0, r3571; CHECK-NEXT: vmov q1[2], q1[0], r0, r1572; CHECK-NEXT: vmov q1[3], q1[1], r3, r2573; CHECK-NEXT: bx lr574entry:575 %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>576 %out1 = zext <4 x i32> %shuf1 to <4 x i64>577 %ext = zext i32 %src2 to i64578 %ins = insertelement <4 x i64> poison, i64 %ext, i32 0579 %shuf2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer580 %out = mul <4 x i64> %shuf2, %out1581 ret <4 x i64> %out582}583 584define arm_aapcs_vfpcc <4 x i32> @sext16_02468101214_0ext(<8 x i16> %src1, i16 %src2) {585; CHECK-LABEL: sext16_02468101214_0ext:586; CHECK: @ %bb.0: @ %entry587; CHECK-NEXT: vdup.32 q1, r0588; CHECK-NEXT: vmullb.s16 q0, q0, q1589; CHECK-NEXT: bx lr590entry:591 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>592 %out1 = sext <4 x i16> %shuf1 to <4 x i32>593 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0594 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer595 %out2 = sext <4 x i16> %shuf2 to <4 x i32>596 %out = mul <4 x i32> %out1, %out2597 ret <4 x i32> %out598}599 600define arm_aapcs_vfpcc <4 x i32> @sext16_0ext_02468101214(<8 x i16> %src1, i16 %src2) {601; CHECK-LABEL: sext16_0ext_02468101214:602; CHECK: @ %bb.0: @ %entry603; CHECK-NEXT: vdup.32 q1, r0604; CHECK-NEXT: vmullb.s16 q0, q1, q0605; CHECK-NEXT: bx lr606entry:607 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>608 %out1 = sext <4 x i16> %shuf1 to <4 x i32>609 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0610 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer611 %out2 = sext <4 x i16> %shuf2 to <4 x i32>612 %out = mul <4 x i32> %out2, %out1613 ret <4 x i32> %out614}615 616define arm_aapcs_vfpcc <4 x i32> @sext16_02468101214_ext0(<8 x i16> %src1, i16 %src2) {617; CHECK-LABEL: sext16_02468101214_ext0:618; CHECK: @ %bb.0: @ %entry619; CHECK-NEXT: vmovlb.s16 q0, q0620; CHECK-NEXT: sxth r0, r0621; CHECK-NEXT: vmul.i32 q0, q0, r0622; CHECK-NEXT: bx lr623entry:624 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>625 %out1 = sext <4 x i16> %shuf1 to <4 x i32>626 %ext = sext i16 %src2 to i32627 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0628 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer629 %out = mul <4 x i32> %out1, %shuf2630 ret <4 x i32> %out631}632 633define arm_aapcs_vfpcc <4 x i32> @sext16_ext0_02468101214(<8 x i16> %src1, i16 %src2) {634; CHECK-LABEL: sext16_ext0_02468101214:635; CHECK: @ %bb.0: @ %entry636; CHECK-NEXT: vmovlb.s16 q0, q0637; CHECK-NEXT: sxth r0, r0638; CHECK-NEXT: vmul.i32 q0, q0, r0639; CHECK-NEXT: bx lr640entry:641 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>642 %out1 = sext <4 x i16> %shuf1 to <4 x i32>643 %ext = sext i16 %src2 to i32644 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0645 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer646 %out = mul <4 x i32> %shuf2, %out1647 ret <4 x i32> %out648}649 650define arm_aapcs_vfpcc <4 x i32> @sext16_13579111315_0ext(<8 x i16> %src1, i16 %src2) {651; CHECK-LABEL: sext16_13579111315_0ext:652; CHECK: @ %bb.0: @ %entry653; CHECK-NEXT: vdup.32 q1, r0654; CHECK-NEXT: vrev32.16 q0, q0655; CHECK-NEXT: vmullb.s16 q0, q0, q1656; CHECK-NEXT: bx lr657entry:658 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>659 %out1 = sext <4 x i16> %shuf1 to <4 x i32>660 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0661 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer662 %out2 = sext <4 x i16> %shuf2 to <4 x i32>663 %out = mul <4 x i32> %out1, %out2664 ret <4 x i32> %out665}666 667define arm_aapcs_vfpcc <4 x i32> @sext16_0ext_13579111315(<8 x i16> %src1, i16 %src2) {668; CHECK-LABEL: sext16_0ext_13579111315:669; CHECK: @ %bb.0: @ %entry670; CHECK-NEXT: vrev32.16 q0, q0671; CHECK-NEXT: vdup.32 q1, r0672; CHECK-NEXT: vmullb.s16 q0, q1, q0673; CHECK-NEXT: bx lr674entry:675 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>676 %out1 = sext <4 x i16> %shuf1 to <4 x i32>677 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0678 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer679 %out2 = sext <4 x i16> %shuf2 to <4 x i32>680 %out = mul <4 x i32> %out2, %out1681 ret <4 x i32> %out682}683 684define arm_aapcs_vfpcc <4 x i32> @sext16_13579111315_ext0(<8 x i16> %src1, i16 %src2) {685; CHECK-LABEL: sext16_13579111315_ext0:686; CHECK: @ %bb.0: @ %entry687; CHECK-NEXT: vmovlt.s16 q0, q0688; CHECK-NEXT: sxth r0, r0689; CHECK-NEXT: vmul.i32 q0, q0, r0690; CHECK-NEXT: bx lr691entry:692 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>693 %out1 = sext <4 x i16> %shuf1 to <4 x i32>694 %ext = sext i16 %src2 to i32695 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0696 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer697 %out = mul <4 x i32> %out1, %shuf2698 ret <4 x i32> %out699}700 701define arm_aapcs_vfpcc <4 x i32> @sext16_ext0_13579111315(<8 x i16> %src1, i16 %src2) {702; CHECK-LABEL: sext16_ext0_13579111315:703; CHECK: @ %bb.0: @ %entry704; CHECK-NEXT: vmovlt.s16 q0, q0705; CHECK-NEXT: sxth r0, r0706; CHECK-NEXT: vmul.i32 q0, q0, r0707; CHECK-NEXT: bx lr708entry:709 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>710 %out1 = sext <4 x i16> %shuf1 to <4 x i32>711 %ext = sext i16 %src2 to i32712 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0713 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer714 %out = mul <4 x i32> %shuf2, %out1715 ret <4 x i32> %out716}717 718define arm_aapcs_vfpcc <8 x i32> @sext16_02461357_0ext(<16 x i16> %src1, i16 %src2) {719; CHECK-LABEL: sext16_02461357_0ext:720; CHECK: @ %bb.0: @ %entry721; CHECK-NEXT: vdup.16 q2, r0722; CHECK-NEXT: vrev32.16 q1, q0723; CHECK-NEXT: vmullb.s16 q1, q1, q2724; CHECK-NEXT: vmullb.s16 q0, q0, q2725; CHECK-NEXT: bx lr726entry:727 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>728 %out1 = sext <8 x i16> %shuf1 to <8 x i32>729 %ins = insertelement <16 x i16> poison, i16 %src2, i32 0730 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <8 x i32> zeroinitializer731 %out2 = sext <8 x i16> %shuf2 to <8 x i32>732 %out = mul <8 x i32> %out1, %out2733 ret <8 x i32> %out734}735 736define arm_aapcs_vfpcc <8 x i32> @sext16_0ext_02461357(<16 x i16> %src1, i16 %src2) {737; CHECK-LABEL: sext16_0ext_02461357:738; CHECK: @ %bb.0: @ %entry739; CHECK-NEXT: vrev32.16 q1, q0740; CHECK-NEXT: vdup.16 q2, r0741; CHECK-NEXT: vmullb.s16 q1, q2, q1742; CHECK-NEXT: vmullb.s16 q0, q2, q0743; CHECK-NEXT: bx lr744entry:745 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>746 %out1 = sext <8 x i16> %shuf1 to <8 x i32>747 %ins = insertelement <16 x i16> poison, i16 %src2, i32 0748 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <8 x i32> zeroinitializer749 %out2 = sext <8 x i16> %shuf2 to <8 x i32>750 %out = mul <8 x i32> %out2, %out1751 ret <8 x i32> %out752}753 754define arm_aapcs_vfpcc <8 x i32> @sext16_02461357_ext0(<16 x i16> %src1, i16 %src2) {755; CHECK-LABEL: sext16_02461357_ext0:756; CHECK: @ %bb.0: @ %entry757; CHECK-NEXT: vmovlb.s16 q1, q0758; CHECK-NEXT: sxth r0, r0759; CHECK-NEXT: vmul.i32 q2, q1, r0760; CHECK-NEXT: vmovlt.s16 q0, q0761; CHECK-NEXT: vmul.i32 q1, q0, r0762; CHECK-NEXT: vmov q0, q2763; CHECK-NEXT: bx lr764entry:765 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>766 %out1 = sext <8 x i16> %shuf1 to <8 x i32>767 %ext = sext i16 %src2 to i32768 %ins = insertelement <8 x i32> poison, i32 %ext, i32 0769 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer770 %out = mul <8 x i32> %out1, %shuf2771 ret <8 x i32> %out772}773 774define arm_aapcs_vfpcc <8 x i32> @sext16_ext0_02461357(<16 x i16> %src1, i16 %src2) {775; CHECK-LABEL: sext16_ext0_02461357:776; CHECK: @ %bb.0: @ %entry777; CHECK-NEXT: vmovlb.s16 q1, q0778; CHECK-NEXT: sxth r0, r0779; CHECK-NEXT: vmul.i32 q2, q1, r0780; CHECK-NEXT: vmovlt.s16 q0, q0781; CHECK-NEXT: vmul.i32 q1, q0, r0782; CHECK-NEXT: vmov q0, q2783; CHECK-NEXT: bx lr784entry:785 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>786 %out1 = sext <8 x i16> %shuf1 to <8 x i32>787 %ext = sext i16 %src2 to i32788 %ins = insertelement <8 x i32> poison, i32 %ext, i32 0789 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer790 %out = mul <8 x i32> %shuf2, %out1791 ret <8 x i32> %out792}793 794define arm_aapcs_vfpcc <4 x i32> @zext16_02468101214_0ext(<8 x i16> %src1, i16 %src2) {795; CHECK-LABEL: zext16_02468101214_0ext:796; CHECK: @ %bb.0: @ %entry797; CHECK-NEXT: vdup.32 q1, r0798; CHECK-NEXT: vmullb.u16 q0, q0, q1799; CHECK-NEXT: bx lr800entry:801 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>802 %out1 = zext <4 x i16> %shuf1 to <4 x i32>803 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0804 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer805 %out2 = zext <4 x i16> %shuf2 to <4 x i32>806 %out = mul <4 x i32> %out1, %out2807 ret <4 x i32> %out808}809 810define arm_aapcs_vfpcc <4 x i32> @zext16_0ext_02468101214(<8 x i16> %src1, i16 %src2) {811; CHECK-LABEL: zext16_0ext_02468101214:812; CHECK: @ %bb.0: @ %entry813; CHECK-NEXT: vdup.32 q1, r0814; CHECK-NEXT: vmullb.u16 q0, q1, q0815; CHECK-NEXT: bx lr816entry:817 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>818 %out1 = zext <4 x i16> %shuf1 to <4 x i32>819 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0820 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer821 %out2 = zext <4 x i16> %shuf2 to <4 x i32>822 %out = mul <4 x i32> %out2, %out1823 ret <4 x i32> %out824}825 826define arm_aapcs_vfpcc <4 x i32> @zext16_02468101214_ext0(<8 x i16> %src1, i16 %src2) {827; CHECK-LABEL: zext16_02468101214_ext0:828; CHECK: @ %bb.0: @ %entry829; CHECK-NEXT: vmovlb.u16 q0, q0830; CHECK-NEXT: uxth r0, r0831; CHECK-NEXT: vmul.i32 q0, q0, r0832; CHECK-NEXT: bx lr833entry:834 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>835 %out1 = zext <4 x i16> %shuf1 to <4 x i32>836 %ext = zext i16 %src2 to i32837 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0838 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer839 %out = mul <4 x i32> %out1, %shuf2840 ret <4 x i32> %out841}842 843define arm_aapcs_vfpcc <4 x i32> @zext16_ext0_02468101214(<8 x i16> %src1, i16 %src2) {844; CHECK-LABEL: zext16_ext0_02468101214:845; CHECK: @ %bb.0: @ %entry846; CHECK-NEXT: vmovlb.u16 q0, q0847; CHECK-NEXT: uxth r0, r0848; CHECK-NEXT: vmul.i32 q0, q0, r0849; CHECK-NEXT: bx lr850entry:851 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>852 %out1 = zext <4 x i16> %shuf1 to <4 x i32>853 %ext = zext i16 %src2 to i32854 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0855 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer856 %out = mul <4 x i32> %shuf2, %out1857 ret <4 x i32> %out858}859 860define arm_aapcs_vfpcc <4 x i32> @zext16_13579111315_0ext(<8 x i16> %src1, i16 %src2) {861; CHECK-LABEL: zext16_13579111315_0ext:862; CHECK: @ %bb.0: @ %entry863; CHECK-NEXT: vdup.32 q1, r0864; CHECK-NEXT: vrev32.16 q0, q0865; CHECK-NEXT: vmullb.u16 q0, q0, q1866; CHECK-NEXT: bx lr867entry:868 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>869 %out1 = zext <4 x i16> %shuf1 to <4 x i32>870 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0871 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer872 %out2 = zext <4 x i16> %shuf2 to <4 x i32>873 %out = mul <4 x i32> %out1, %out2874 ret <4 x i32> %out875}876 877define arm_aapcs_vfpcc <4 x i32> @zext16_0ext_13579111315(<8 x i16> %src1, i16 %src2) {878; CHECK-LABEL: zext16_0ext_13579111315:879; CHECK: @ %bb.0: @ %entry880; CHECK-NEXT: vrev32.16 q0, q0881; CHECK-NEXT: vdup.32 q1, r0882; CHECK-NEXT: vmullb.u16 q0, q1, q0883; CHECK-NEXT: bx lr884entry:885 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>886 %out1 = zext <4 x i16> %shuf1 to <4 x i32>887 %ins = insertelement <8 x i16> poison, i16 %src2, i32 0888 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <4 x i32> zeroinitializer889 %out2 = zext <4 x i16> %shuf2 to <4 x i32>890 %out = mul <4 x i32> %out2, %out1891 ret <4 x i32> %out892}893 894define arm_aapcs_vfpcc <4 x i32> @zext16_13579111315_ext0(<8 x i16> %src1, i16 %src2) {895; CHECK-LABEL: zext16_13579111315_ext0:896; CHECK: @ %bb.0: @ %entry897; CHECK-NEXT: vmovlt.u16 q0, q0898; CHECK-NEXT: uxth r0, r0899; CHECK-NEXT: vmul.i32 q0, q0, r0900; CHECK-NEXT: bx lr901entry:902 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>903 %out1 = zext <4 x i16> %shuf1 to <4 x i32>904 %ext = zext i16 %src2 to i32905 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0906 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer907 %out = mul <4 x i32> %out1, %shuf2908 ret <4 x i32> %out909}910 911define arm_aapcs_vfpcc <4 x i32> @zext16_ext0_13579111315(<8 x i16> %src1, i16 %src2) {912; CHECK-LABEL: zext16_ext0_13579111315:913; CHECK: @ %bb.0: @ %entry914; CHECK-NEXT: vmovlt.u16 q0, q0915; CHECK-NEXT: uxth r0, r0916; CHECK-NEXT: vmul.i32 q0, q0, r0917; CHECK-NEXT: bx lr918entry:919 %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>920 %out1 = zext <4 x i16> %shuf1 to <4 x i32>921 %ext = zext i16 %src2 to i32922 %ins = insertelement <4 x i32> poison, i32 %ext, i32 0923 %shuf2 = shufflevector <4 x i32> %ins, <4 x i32> undef, <4 x i32> zeroinitializer924 %out = mul <4 x i32> %shuf2, %out1925 ret <4 x i32> %out926}927 928define arm_aapcs_vfpcc <8 x i32> @zext16_02461357_0ext(<16 x i16> %src1, i16 %src2) {929; CHECK-LABEL: zext16_02461357_0ext:930; CHECK: @ %bb.0: @ %entry931; CHECK-NEXT: vdup.16 q2, r0932; CHECK-NEXT: vrev32.16 q1, q0933; CHECK-NEXT: vmullb.u16 q1, q1, q2934; CHECK-NEXT: vmullb.u16 q0, q0, q2935; CHECK-NEXT: bx lr936entry:937 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>938 %out1 = zext <8 x i16> %shuf1 to <8 x i32>939 %ins = insertelement <16 x i16> poison, i16 %src2, i32 0940 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <8 x i32> zeroinitializer941 %out2 = zext <8 x i16> %shuf2 to <8 x i32>942 %out = mul <8 x i32> %out1, %out2943 ret <8 x i32> %out944}945 946define arm_aapcs_vfpcc <8 x i32> @zext16_0ext_02461357(<16 x i16> %src1, i16 %src2) {947; CHECK-LABEL: zext16_0ext_02461357:948; CHECK: @ %bb.0: @ %entry949; CHECK-NEXT: vrev32.16 q1, q0950; CHECK-NEXT: vdup.16 q2, r0951; CHECK-NEXT: vmullb.u16 q1, q2, q1952; CHECK-NEXT: vmullb.u16 q0, q2, q0953; CHECK-NEXT: bx lr954entry:955 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>956 %out1 = zext <8 x i16> %shuf1 to <8 x i32>957 %ins = insertelement <16 x i16> poison, i16 %src2, i32 0958 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <8 x i32> zeroinitializer959 %out2 = zext <8 x i16> %shuf2 to <8 x i32>960 %out = mul <8 x i32> %out2, %out1961 ret <8 x i32> %out962}963 964define arm_aapcs_vfpcc <8 x i32> @zext16_02461357_ext0(<16 x i16> %src1, i16 %src2) {965; CHECK-LABEL: zext16_02461357_ext0:966; CHECK: @ %bb.0: @ %entry967; CHECK-NEXT: vmovlb.u16 q1, q0968; CHECK-NEXT: uxth r0, r0969; CHECK-NEXT: vmul.i32 q2, q1, r0970; CHECK-NEXT: vmovlt.u16 q0, q0971; CHECK-NEXT: vmul.i32 q1, q0, r0972; CHECK-NEXT: vmov q0, q2973; CHECK-NEXT: bx lr974entry:975 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>976 %out1 = zext <8 x i16> %shuf1 to <8 x i32>977 %ext = zext i16 %src2 to i32978 %ins = insertelement <8 x i32> poison, i32 %ext, i32 0979 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer980 %out = mul <8 x i32> %out1, %shuf2981 ret <8 x i32> %out982}983 984define arm_aapcs_vfpcc <8 x i32> @zext16_ext0_02461357(<16 x i16> %src1, i16 %src2) {985; CHECK-LABEL: zext16_ext0_02461357:986; CHECK: @ %bb.0: @ %entry987; CHECK-NEXT: vmovlb.u16 q1, q0988; CHECK-NEXT: uxth r0, r0989; CHECK-NEXT: vmul.i32 q2, q1, r0990; CHECK-NEXT: vmovlt.u16 q0, q0991; CHECK-NEXT: vmul.i32 q1, q0, r0992; CHECK-NEXT: vmov q0, q2993; CHECK-NEXT: bx lr994entry:995 %shuf1 = shufflevector <16 x i16> %src1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>996 %out1 = zext <8 x i16> %shuf1 to <8 x i32>997 %ext = zext i16 %src2 to i32998 %ins = insertelement <8 x i32> poison, i32 %ext, i32 0999 %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer1000 %out = mul <8 x i32> %shuf2, %out11001 ret <8 x i32> %out1002}1003 1004define arm_aapcs_vfpcc <8 x i16> @sext8_024681012141618202224262830_0ext(<16 x i8> %src1, i8 %src2) {1005; CHECK-LABEL: sext8_024681012141618202224262830_0ext:1006; CHECK: @ %bb.0: @ %entry1007; CHECK-NEXT: vdup.16 q1, r01008; CHECK-NEXT: vmullb.s8 q0, q0, q11009; CHECK-NEXT: bx lr1010entry:1011 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1012 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1013 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01014 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1015 %out2 = sext <8 x i8> %shuf2 to <8 x i16>1016 %out = mul <8 x i16> %out1, %out21017 ret <8 x i16> %out1018}1019 1020define arm_aapcs_vfpcc <8 x i16> @sext8_0ext_024681012141618202224262830(<16 x i8> %src1, i8 %src2) {1021; CHECK-LABEL: sext8_0ext_024681012141618202224262830:1022; CHECK: @ %bb.0: @ %entry1023; CHECK-NEXT: vdup.16 q1, r01024; CHECK-NEXT: vmullb.s8 q0, q1, q01025; CHECK-NEXT: bx lr1026entry:1027 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1028 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1029 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01030 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1031 %out2 = sext <8 x i8> %shuf2 to <8 x i16>1032 %out = mul <8 x i16> %out2, %out11033 ret <8 x i16> %out1034}1035 1036define arm_aapcs_vfpcc <8 x i16> @sext8_024681012141618202224262830_ext0(<16 x i8> %src1, i8 %src2) {1037; CHECK-LABEL: sext8_024681012141618202224262830_ext0:1038; CHECK: @ %bb.0: @ %entry1039; CHECK-NEXT: vmovlb.s8 q0, q01040; CHECK-NEXT: sxtb r0, r01041; CHECK-NEXT: vmul.i16 q0, q0, r01042; CHECK-NEXT: bx lr1043entry:1044 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1045 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1046 %ext = sext i8 %src2 to i161047 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01048 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1049 %out = mul <8 x i16> %out1, %shuf21050 ret <8 x i16> %out1051}1052 1053define arm_aapcs_vfpcc <8 x i16> @sext8_ext0_024681012141618202224262830(<16 x i8> %src1, i8 %src2) {1054; CHECK-LABEL: sext8_ext0_024681012141618202224262830:1055; CHECK: @ %bb.0: @ %entry1056; CHECK-NEXT: vmovlb.s8 q0, q01057; CHECK-NEXT: sxtb r0, r01058; CHECK-NEXT: vmul.i16 q0, q0, r01059; CHECK-NEXT: bx lr1060entry:1061 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1062 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1063 %ext = sext i8 %src2 to i161064 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01065 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1066 %out = mul <8 x i16> %shuf2, %out11067 ret <8 x i16> %out1068}1069 1070define arm_aapcs_vfpcc <8 x i16> @sext8_135791113151719212325272931_0ext(<16 x i8> %src1, i8 %src2) {1071; CHECK-LABEL: sext8_135791113151719212325272931_0ext:1072; CHECK: @ %bb.0: @ %entry1073; CHECK-NEXT: vdup.16 q1, r01074; CHECK-NEXT: vrev16.8 q0, q01075; CHECK-NEXT: vmullb.s8 q0, q0, q11076; CHECK-NEXT: bx lr1077entry:1078 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1079 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1080 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01081 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1082 %out2 = sext <8 x i8> %shuf2 to <8 x i16>1083 %out = mul <8 x i16> %out1, %out21084 ret <8 x i16> %out1085}1086 1087define arm_aapcs_vfpcc <8 x i16> @sext8_0ext_135791113151719212325272931(<16 x i8> %src1, i8 %src2) {1088; CHECK-LABEL: sext8_0ext_135791113151719212325272931:1089; CHECK: @ %bb.0: @ %entry1090; CHECK-NEXT: vrev16.8 q0, q01091; CHECK-NEXT: vdup.16 q1, r01092; CHECK-NEXT: vmullb.s8 q0, q1, q01093; CHECK-NEXT: bx lr1094entry:1095 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1096 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1097 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01098 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1099 %out2 = sext <8 x i8> %shuf2 to <8 x i16>1100 %out = mul <8 x i16> %out2, %out11101 ret <8 x i16> %out1102}1103 1104define arm_aapcs_vfpcc <8 x i16> @sext8_135791113151719212325272931_ext0(<16 x i8> %src1, i8 %src2) {1105; CHECK-LABEL: sext8_135791113151719212325272931_ext0:1106; CHECK: @ %bb.0: @ %entry1107; CHECK-NEXT: vmovlt.s8 q0, q01108; CHECK-NEXT: sxtb r0, r01109; CHECK-NEXT: vmul.i16 q0, q0, r01110; CHECK-NEXT: bx lr1111entry:1112 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1113 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1114 %ext = sext i8 %src2 to i161115 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01116 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1117 %out = mul <8 x i16> %out1, %shuf21118 ret <8 x i16> %out1119}1120 1121define arm_aapcs_vfpcc <8 x i16> @sext8_ext0_135791113151719212325272931(<16 x i8> %src1, i8 %src2) {1122; CHECK-LABEL: sext8_ext0_135791113151719212325272931:1123; CHECK: @ %bb.0: @ %entry1124; CHECK-NEXT: vmovlt.s8 q0, q01125; CHECK-NEXT: sxtb r0, r01126; CHECK-NEXT: vmul.i16 q0, q0, r01127; CHECK-NEXT: bx lr1128entry:1129 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1130 %out1 = sext <8 x i8> %shuf1 to <8 x i16>1131 %ext = sext i8 %src2 to i161132 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01133 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1134 %out = mul <8 x i16> %shuf2, %out11135 ret <8 x i16> %out1136}1137 1138define arm_aapcs_vfpcc <16 x i16> @sext8_0246810121413579111315_0ext(<32 x i8> %src1, i8 %src2) {1139; CHECK-LABEL: sext8_0246810121413579111315_0ext:1140; CHECK: @ %bb.0: @ %entry1141; CHECK-NEXT: vdup.8 q2, r01142; CHECK-NEXT: vrev16.8 q1, q01143; CHECK-NEXT: vmullb.s8 q1, q1, q21144; CHECK-NEXT: vmullb.s8 q0, q0, q21145; CHECK-NEXT: bx lr1146entry:1147 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1148 %out1 = sext <16 x i8> %shuf1 to <16 x i16>1149 %ins = insertelement <32 x i8> poison, i8 %src2, i32 01150 %shuf2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <16 x i32> zeroinitializer1151 %out2 = sext <16 x i8> %shuf2 to <16 x i16>1152 %out = mul <16 x i16> %out1, %out21153 ret <16 x i16> %out1154}1155 1156define arm_aapcs_vfpcc <16 x i16> @sext8_0ext_0246810121413579111315(<32 x i8> %src1, i8 %src2) {1157; CHECK-LABEL: sext8_0ext_0246810121413579111315:1158; CHECK: @ %bb.0: @ %entry1159; CHECK-NEXT: vrev16.8 q1, q01160; CHECK-NEXT: vdup.8 q2, r01161; CHECK-NEXT: vmullb.s8 q1, q2, q11162; CHECK-NEXT: vmullb.s8 q0, q2, q01163; CHECK-NEXT: bx lr1164entry:1165 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1166 %out1 = sext <16 x i8> %shuf1 to <16 x i16>1167 %ins = insertelement <32 x i8> poison, i8 %src2, i32 01168 %shuf2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <16 x i32> zeroinitializer1169 %out2 = sext <16 x i8> %shuf2 to <16 x i16>1170 %out = mul <16 x i16> %out2, %out11171 ret <16 x i16> %out1172}1173 1174define arm_aapcs_vfpcc <16 x i16> @sext8_0246810121413579111315_ext0(<32 x i8> %src1, i8 %src2) {1175; CHECK-LABEL: sext8_0246810121413579111315_ext0:1176; CHECK: @ %bb.0: @ %entry1177; CHECK-NEXT: vmovlb.s8 q1, q01178; CHECK-NEXT: sxtb r0, r01179; CHECK-NEXT: vmul.i16 q2, q1, r01180; CHECK-NEXT: vmovlt.s8 q0, q01181; CHECK-NEXT: vmul.i16 q1, q0, r01182; CHECK-NEXT: vmov q0, q21183; CHECK-NEXT: bx lr1184entry:1185 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1186 %out1 = sext <16 x i8> %shuf1 to <16 x i16>1187 %ext = sext i8 %src2 to i161188 %ins = insertelement <16 x i16> poison, i16 %ext, i32 01189 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer1190 %out = mul <16 x i16> %out1, %shuf21191 ret <16 x i16> %out1192}1193 1194define arm_aapcs_vfpcc <16 x i16> @sext8_ext0_0246810121413579111315(<32 x i8> %src1, i8 %src2) {1195; CHECK-LABEL: sext8_ext0_0246810121413579111315:1196; CHECK: @ %bb.0: @ %entry1197; CHECK-NEXT: vmovlb.s8 q1, q01198; CHECK-NEXT: sxtb r0, r01199; CHECK-NEXT: vmul.i16 q2, q1, r01200; CHECK-NEXT: vmovlt.s8 q0, q01201; CHECK-NEXT: vmul.i16 q1, q0, r01202; CHECK-NEXT: vmov q0, q21203; CHECK-NEXT: bx lr1204entry:1205 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1206 %out1 = sext <16 x i8> %shuf1 to <16 x i16>1207 %ext = sext i8 %src2 to i161208 %ins = insertelement <16 x i16> poison, i16 %ext, i32 01209 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer1210 %out = mul <16 x i16> %shuf2, %out11211 ret <16 x i16> %out1212}1213 1214define arm_aapcs_vfpcc <8 x i16> @zext8_024681012141618202224262830_0ext(<16 x i8> %src1, i8 %src2) {1215; CHECK-LABEL: zext8_024681012141618202224262830_0ext:1216; CHECK: @ %bb.0: @ %entry1217; CHECK-NEXT: vdup.16 q1, r01218; CHECK-NEXT: vmullb.u8 q0, q0, q11219; CHECK-NEXT: bx lr1220entry:1221 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1222 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1223 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01224 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1225 %out2 = zext <8 x i8> %shuf2 to <8 x i16>1226 %out = mul <8 x i16> %out1, %out21227 ret <8 x i16> %out1228}1229 1230define arm_aapcs_vfpcc <8 x i16> @zext8_0ext_024681012141618202224262830(<16 x i8> %src1, i8 %src2) {1231; CHECK-LABEL: zext8_0ext_024681012141618202224262830:1232; CHECK: @ %bb.0: @ %entry1233; CHECK-NEXT: vdup.16 q1, r01234; CHECK-NEXT: vmullb.u8 q0, q1, q01235; CHECK-NEXT: bx lr1236entry:1237 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1238 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1239 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01240 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1241 %out2 = zext <8 x i8> %shuf2 to <8 x i16>1242 %out = mul <8 x i16> %out2, %out11243 ret <8 x i16> %out1244}1245 1246define arm_aapcs_vfpcc <8 x i16> @zext8_024681012141618202224262830_ext0(<16 x i8> %src1, i8 %src2) {1247; CHECK-LABEL: zext8_024681012141618202224262830_ext0:1248; CHECK: @ %bb.0: @ %entry1249; CHECK-NEXT: vmovlb.u8 q0, q01250; CHECK-NEXT: uxtb r0, r01251; CHECK-NEXT: vmul.i16 q0, q0, r01252; CHECK-NEXT: bx lr1253entry:1254 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1255 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1256 %ext = zext i8 %src2 to i161257 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01258 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1259 %out = mul <8 x i16> %out1, %shuf21260 ret <8 x i16> %out1261}1262 1263define arm_aapcs_vfpcc <8 x i16> @zext8_ext0_024681012141618202224262830(<16 x i8> %src1, i8 %src2) {1264; CHECK-LABEL: zext8_ext0_024681012141618202224262830:1265; CHECK: @ %bb.0: @ %entry1266; CHECK-NEXT: vmovlb.u8 q0, q01267; CHECK-NEXT: uxtb r0, r01268; CHECK-NEXT: vmul.i16 q0, q0, r01269; CHECK-NEXT: bx lr1270entry:1271 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1272 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1273 %ext = zext i8 %src2 to i161274 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01275 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1276 %out = mul <8 x i16> %shuf2, %out11277 ret <8 x i16> %out1278}1279 1280define arm_aapcs_vfpcc <8 x i16> @zext8_135791113151719212325272931_0ext(<16 x i8> %src1, i8 %src2) {1281; CHECK-LABEL: zext8_135791113151719212325272931_0ext:1282; CHECK: @ %bb.0: @ %entry1283; CHECK-NEXT: vdup.16 q1, r01284; CHECK-NEXT: vrev16.8 q0, q01285; CHECK-NEXT: vmullb.u8 q0, q0, q11286; CHECK-NEXT: bx lr1287entry:1288 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1289 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1290 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01291 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1292 %out2 = zext <8 x i8> %shuf2 to <8 x i16>1293 %out = mul <8 x i16> %out1, %out21294 ret <8 x i16> %out1295}1296 1297define arm_aapcs_vfpcc <8 x i16> @zext8_0ext_135791113151719212325272931(<16 x i8> %src1, i8 %src2) {1298; CHECK-LABEL: zext8_0ext_135791113151719212325272931:1299; CHECK: @ %bb.0: @ %entry1300; CHECK-NEXT: vrev16.8 q0, q01301; CHECK-NEXT: vdup.16 q1, r01302; CHECK-NEXT: vmullb.u8 q0, q1, q01303; CHECK-NEXT: bx lr1304entry:1305 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1306 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1307 %ins = insertelement <16 x i8> poison, i8 %src2, i32 01308 %shuf2 = shufflevector <16 x i8> %ins, <16 x i8> undef, <8 x i32> zeroinitializer1309 %out2 = zext <8 x i8> %shuf2 to <8 x i16>1310 %out = mul <8 x i16> %out2, %out11311 ret <8 x i16> %out1312}1313 1314define arm_aapcs_vfpcc <8 x i16> @zext8_135791113151719212325272931_ext0(<16 x i8> %src1, i8 %src2) {1315; CHECK-LABEL: zext8_135791113151719212325272931_ext0:1316; CHECK: @ %bb.0: @ %entry1317; CHECK-NEXT: vmovlt.u8 q0, q01318; CHECK-NEXT: uxtb r0, r01319; CHECK-NEXT: vmul.i16 q0, q0, r01320; CHECK-NEXT: bx lr1321entry:1322 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1323 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1324 %ext = zext i8 %src2 to i161325 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01326 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1327 %out = mul <8 x i16> %out1, %shuf21328 ret <8 x i16> %out1329}1330 1331define arm_aapcs_vfpcc <8 x i16> @zext8_ext0_135791113151719212325272931(<16 x i8> %src1, i8 %src2) {1332; CHECK-LABEL: zext8_ext0_135791113151719212325272931:1333; CHECK: @ %bb.0: @ %entry1334; CHECK-NEXT: vmovlt.u8 q0, q01335; CHECK-NEXT: uxtb r0, r01336; CHECK-NEXT: vmul.i16 q0, q0, r01337; CHECK-NEXT: bx lr1338entry:1339 %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1340 %out1 = zext <8 x i8> %shuf1 to <8 x i16>1341 %ext = zext i8 %src2 to i161342 %ins = insertelement <8 x i16> poison, i16 %ext, i32 01343 %shuf2 = shufflevector <8 x i16> %ins, <8 x i16> undef, <8 x i32> zeroinitializer1344 %out = mul <8 x i16> %shuf2, %out11345 ret <8 x i16> %out1346}1347 1348define arm_aapcs_vfpcc <16 x i16> @zext8_0246810121413579111315_0ext(<32 x i8> %src1, i8 %src2) {1349; CHECK-LABEL: zext8_0246810121413579111315_0ext:1350; CHECK: @ %bb.0: @ %entry1351; CHECK-NEXT: vdup.8 q2, r01352; CHECK-NEXT: vrev16.8 q1, q01353; CHECK-NEXT: vmullb.u8 q1, q1, q21354; CHECK-NEXT: vmullb.u8 q0, q0, q21355; CHECK-NEXT: bx lr1356entry:1357 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1358 %out1 = zext <16 x i8> %shuf1 to <16 x i16>1359 %ins = insertelement <32 x i8> poison, i8 %src2, i32 01360 %shuf2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <16 x i32> zeroinitializer1361 %out2 = zext <16 x i8> %shuf2 to <16 x i16>1362 %out = mul <16 x i16> %out1, %out21363 ret <16 x i16> %out1364}1365 1366define arm_aapcs_vfpcc <16 x i16> @zext8_0ext_0246810121413579111315(<32 x i8> %src1, i8 %src2) {1367; CHECK-LABEL: zext8_0ext_0246810121413579111315:1368; CHECK: @ %bb.0: @ %entry1369; CHECK-NEXT: vrev16.8 q1, q01370; CHECK-NEXT: vdup.8 q2, r01371; CHECK-NEXT: vmullb.u8 q1, q2, q11372; CHECK-NEXT: vmullb.u8 q0, q2, q01373; CHECK-NEXT: bx lr1374entry:1375 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1376 %out1 = zext <16 x i8> %shuf1 to <16 x i16>1377 %ins = insertelement <32 x i8> poison, i8 %src2, i32 01378 %shuf2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <16 x i32> zeroinitializer1379 %out2 = zext <16 x i8> %shuf2 to <16 x i16>1380 %out = mul <16 x i16> %out2, %out11381 ret <16 x i16> %out1382}1383 1384define arm_aapcs_vfpcc <16 x i16> @zext8_0246810121413579111315_ext0(<32 x i8> %src1, i8 %src2) {1385; CHECK-LABEL: zext8_0246810121413579111315_ext0:1386; CHECK: @ %bb.0: @ %entry1387; CHECK-NEXT: vmovlb.u8 q1, q01388; CHECK-NEXT: uxtb r0, r01389; CHECK-NEXT: vmul.i16 q2, q1, r01390; CHECK-NEXT: vmovlt.u8 q0, q01391; CHECK-NEXT: vmul.i16 q1, q0, r01392; CHECK-NEXT: vmov q0, q21393; CHECK-NEXT: bx lr1394entry:1395 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1396 %out1 = zext <16 x i8> %shuf1 to <16 x i16>1397 %ext = zext i8 %src2 to i161398 %ins = insertelement <16 x i16> poison, i16 %ext, i32 01399 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer1400 %out = mul <16 x i16> %out1, %shuf21401 ret <16 x i16> %out1402}1403 1404define arm_aapcs_vfpcc <16 x i16> @zext8_ext0_0246810121413579111315(<32 x i8> %src1, i8 %src2) {1405; CHECK-LABEL: zext8_ext0_0246810121413579111315:1406; CHECK: @ %bb.0: @ %entry1407; CHECK-NEXT: vmovlb.u8 q1, q01408; CHECK-NEXT: uxtb r0, r01409; CHECK-NEXT: vmul.i16 q2, q1, r01410; CHECK-NEXT: vmovlt.u8 q0, q01411; CHECK-NEXT: vmul.i16 q1, q0, r01412; CHECK-NEXT: vmov q0, q21413; CHECK-NEXT: bx lr1414entry:1415 %shuf1 = shufflevector <32 x i8> %src1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1416 %out1 = zext <16 x i8> %shuf1 to <16 x i16>1417 %ext = zext i8 %src2 to i161418 %ins = insertelement <16 x i16> poison, i16 %ext, i32 01419 %shuf2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer1420 %out = mul <16 x i16> %shuf2, %out11421 ret <16 x i16> %out1422}1423