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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @vpsel_i8(<16 x i8> %mask, <16 x i8> %src1, <16 x i8> %src2) {5; CHECK-LABEL: vpsel_i8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcmp.i8 ne, q0, zr8; CHECK-NEXT: vpsel q0, q1, q29; CHECK-NEXT: bx lr10entry:11 %0 = icmp ne <16 x i8> %mask, zeroinitializer12 %1 = select <16 x i1> %0, <16 x i8> %src1, <16 x i8> %src213 ret <16 x i8> %114}15 16define arm_aapcs_vfpcc <8 x i16> @vpsel_i16(<8 x i16> %mask, <8 x i16> %src1, <8 x i16> %src2) {17; CHECK-LABEL: vpsel_i16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vcmp.i16 ne, q0, zr20; CHECK-NEXT: vpsel q0, q1, q221; CHECK-NEXT: bx lr22entry:23 %0 = icmp ne <8 x i16> %mask, zeroinitializer24 %1 = select <8 x i1> %0, <8 x i16> %src1, <8 x i16> %src225 ret <8 x i16> %126}27 28define arm_aapcs_vfpcc <4 x i32> @vpsel_i32(<4 x i32> %mask, <4 x i32> %src1, <4 x i32> %src2) {29; CHECK-LABEL: vpsel_i32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vcmp.i32 ne, q0, zr32; CHECK-NEXT: vpsel q0, q1, q233; CHECK-NEXT: bx lr34entry:35 %0 = icmp ne <4 x i32> %mask, zeroinitializer36 %1 = select <4 x i1> %0, <4 x i32> %src1, <4 x i32> %src237 ret <4 x i32> %138}39 40define arm_aapcs_vfpcc <2 x i64> @vpsel_i64(<2 x i64> %mask, <2 x i64> %src1, <2 x i64> %src2) {41; CHECK-LABEL: vpsel_i64:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vmov r0, r1, d044; CHECK-NEXT: movs r2, #045; CHECK-NEXT: vmov r12, r3, d146; CHECK-NEXT: orrs r0, r147; CHECK-NEXT: csetm r0, ne48; CHECK-NEXT: bfi r2, r0, #0, #849; CHECK-NEXT: orrs.w r0, r12, r350; CHECK-NEXT: csetm r0, ne51; CHECK-NEXT: bfi r2, r0, #8, #852; CHECK-NEXT: vmsr p0, r253; CHECK-NEXT: vpsel q0, q1, q254; CHECK-NEXT: bx lr55entry:56 %0 = icmp ne <2 x i64> %mask, zeroinitializer57 %1 = select <2 x i1> %0, <2 x i64> %src1, <2 x i64> %src258 ret <2 x i64> %159}60 61define arm_aapcs_vfpcc <8 x half> @vpsel_f16(<8 x i16> %mask, <8 x half> %src1, <8 x half> %src2) {62; CHECK-LABEL: vpsel_f16:63; CHECK: @ %bb.0: @ %entry64; CHECK-NEXT: vcmp.i16 ne, q0, zr65; CHECK-NEXT: vpsel q0, q1, q266; CHECK-NEXT: bx lr67entry:68 %0 = icmp ne <8 x i16> %mask, zeroinitializer69 %1 = select <8 x i1> %0, <8 x half> %src1, <8 x half> %src270 ret <8 x half> %171}72 73define arm_aapcs_vfpcc <4 x float> @vpsel_f32(<4 x i32> %mask, <4 x float> %src1, <4 x float> %src2) {74; CHECK-LABEL: vpsel_f32:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: vcmp.i32 ne, q0, zr77; CHECK-NEXT: vpsel q0, q1, q278; CHECK-NEXT: bx lr79entry:80 %0 = icmp ne <4 x i32> %mask, zeroinitializer81 %1 = select <4 x i1> %0, <4 x float> %src1, <4 x float> %src282 ret <4 x float> %183}84 85define arm_aapcs_vfpcc <2 x double> @vpsel_f64(<2 x i64> %mask, <2 x double> %src1, <2 x double> %src2) {86; CHECK-LABEL: vpsel_f64:87; CHECK: @ %bb.0: @ %entry88; CHECK-NEXT: vmov r0, r1, d089; CHECK-NEXT: movs r2, #090; CHECK-NEXT: vmov r12, r3, d191; CHECK-NEXT: orrs r0, r192; CHECK-NEXT: csetm r0, ne93; CHECK-NEXT: bfi r2, r0, #0, #894; CHECK-NEXT: orrs.w r0, r12, r395; CHECK-NEXT: csetm r0, ne96; CHECK-NEXT: bfi r2, r0, #8, #897; CHECK-NEXT: vmsr p0, r298; CHECK-NEXT: vpsel q0, q1, q299; CHECK-NEXT: bx lr100entry:101 %0 = icmp ne <2 x i64> %mask, zeroinitializer102 %1 = select <2 x i1> %0, <2 x double> %src1, <2 x double> %src2103 ret <2 x double> %1104}105 106define arm_aapcs_vfpcc <4 x i32> @foo(<4 x i32> %vec.ind) {107; CHECK-LABEL: foo:108; CHECK: @ %bb.0:109; CHECK-NEXT: vmov.i32 q2, #0x1110; CHECK-NEXT: vmov.i32 q1, #0x0111; CHECK-NEXT: vand q2, q0, q2112; CHECK-NEXT: vcmp.i32 eq, q2, zr113; CHECK-NEXT: vpsel q0, q0, q1114; CHECK-NEXT: bx lr115 %tmp = and <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1>116 %tmp1 = icmp eq <4 x i32> %tmp, zeroinitializer117 %tmp2 = select <4 x i1> %tmp1, <4 x i32> %vec.ind, <4 x i32> zeroinitializer118 ret <4 x i32> %tmp2119}120