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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"6 target triple = "thumbv8.1m.main-none-none-eabi"7 8 define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_1_pred(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {9 entry:10 ;11 ; Intentionally left blank, see the MIR sequence below.12 ;13 ret <4 x float> %inactive114 }15 16 attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }17 attributes #1 = { nounwind readnone }18 attributes #2 = { nounwind }19 20...21---22name: vpt_2_blocks_1_pred23alignment: 424exposesReturnsTwice: false25legalized: false26regBankSelected: false27selected: false28failedISel: false29tracksRegLiveness: true30hasWinCFI: false31registers: []32liveins:33 - { reg: '$q0', virtual-reg: '' }34 - { reg: '$q1', virtual-reg: '' }35 - { reg: '$q2', virtual-reg: '' }36 - { reg: '$q5', virtual-reg: '' }37 - { reg: '$r0', virtual-reg: '' }38 - { reg: '$r1', virtual-reg: '' }39frameInfo:40 isFrameAddressTaken: false41 isReturnAddressTaken: false42 hasStackMap: false43 hasPatchPoint: false44 stackSize: 045 offsetAdjustment: 046 maxAlignment: 047 adjustsStack: false48 hasCalls: false49 stackProtector: ''50 maxCallFrameSize: 051 cvBytesOfCalleeSavedRegisters: 052 hasOpaqueSPAdjustment: false53 hasVAStart: false54 hasMustTailInVarArgFunc: false55 localFrameSize: 056 savePoint: []57 restorePoint: []58fixedStack: []59stack: []60constants: []61body: |62 bb.0:63 liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r1264 65 66 67 ; CHECK-LABEL: name: vpt_2_blocks_1_pred68 ; CHECK: successors: %bb.0(0x80000000)69 ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r1270 ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg71 ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit $q1, implicit $q5, implicit killed $r4 {72 ; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr73 ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr, $noreg74 ; CHECK: }75 ; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14 /* CC::al */, $noreg, $noreg76 ; CHECK: BUNDLE implicit-def $q7, implicit killed $vpr, implicit killed $r4 {77 ; CHECK: MVE_VPST 8, implicit $vpr78 ; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr, $noreg79 ; CHECK: }80 ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr81 ; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg82 renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg, $noreg83 renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg84 renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg85 renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg86 renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr, $noreg87 t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr88 t2B %bb.0, 14, $noreg89 90...91