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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s3 4declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)5 6define arm_aapcs_vfpcc <4 x i32> @vpt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {7; CHECK-LABEL: vpt_block:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vpt.s32 ge, q0, q210; CHECK-NEXT: vorrt q0, q1, q211; CHECK-NEXT: bx lr12entry:13 %0 = icmp sge <4 x i32> %a, %c14 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)15 ret <4 x i32> %116}17 18define arm_aapcs_vfpcc <4 x i32> @vptt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {19; CHECK-LABEL: vptt_block:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vmov q3, q022; CHECK-NEXT: vptt.s32 ge, q0, q223; CHECK-NEXT: vorrt q3, q1, q224; CHECK-NEXT: vorrt q0, q3, q225; CHECK-NEXT: bx lr26entry:27 %0 = icmp sge <4 x i32> %a, %c28 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)29 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)30 ret <4 x i32> %231}32 33define arm_aapcs_vfpcc <4 x i32> @vpttt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {34; CHECK-LABEL: vpttt_block:35; CHECK: @ %bb.0: @ %entry36; CHECK-NEXT: vpttt.s32 ge, q0, q237; CHECK-NEXT: vorrt q0, q1, q238; CHECK-NEXT: vorrt q0, q1, q239; CHECK-NEXT: vorrt q0, q1, q240; CHECK-NEXT: bx lr41entry:42 %0 = icmp sge <4 x i32> %a, %c43 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)44 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)45 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %2)46 ret <4 x i32> %347}48 49define arm_aapcs_vfpcc <4 x i32> @vptttt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {50; CHECK-LABEL: vptttt_block:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: vptttt.s32 ge, q0, q253; CHECK-NEXT: vorrt q0, q1, q254; CHECK-NEXT: vorrt q0, q1, q255; CHECK-NEXT: vorrt q0, q1, q256; CHECK-NEXT: vorrt q0, q1, q257; CHECK-NEXT: bx lr58entry:59 %0 = icmp sge <4 x i32> %a, %c60 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)61 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)62 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %2)63 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)64 ret <4 x i32> %465}66 67 68define arm_aapcs_vfpcc <4 x i32> @vpte_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {69; CHECK-LABEL: vpte_block:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: vpte.s32 ge, q0, q272; CHECK-NEXT: vorrt q0, q1, q273; CHECK-NEXT: vmove q0, q274; CHECK-NEXT: bx lr75entry:76 %0 = icmp sge <4 x i32> %a, %c77 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)78 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>79 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)80 ret <4 x i32> %381}82 83define arm_aapcs_vfpcc <4 x i32> @vptte_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {84; CHECK-LABEL: vptte_block:85; CHECK: @ %bb.0: @ %entry86; CHECK-NEXT: vptte.s32 ge, q0, q287; CHECK-NEXT: vorrt q0, q1, q288; CHECK-NEXT: vorrt q0, q1, q289; CHECK-NEXT: vorre q0, q1, q290; CHECK-NEXT: bx lr91entry:92 %0 = icmp sge <4 x i32> %a, %c93 %1 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>94 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)95 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %2)96 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %1, <4 x i32> %3)97 ret <4 x i32> %498}99 100define arm_aapcs_vfpcc <4 x i32> @vptee_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {101; CHECK-LABEL: vptee_block:102; CHECK: @ %bb.0: @ %entry103; CHECK-NEXT: vptee.s32 ge, q0, q2104; CHECK-NEXT: vorrt q0, q1, q2105; CHECK-NEXT: vorre q0, q1, q2106; CHECK-NEXT: vorre q0, q1, q2107; CHECK-NEXT: bx lr108entry:109 %0 = icmp sge <4 x i32> %a, %c110 %1 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>111 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)112 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %1, <4 x i32> %2)113 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %1, <4 x i32> %3)114 ret <4 x i32> %4115}116 117define arm_aapcs_vfpcc <4 x i32> @vptet_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {118; CHECK-LABEL: vptet_block:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vptet.s32 ge, q0, q2121; CHECK-NEXT: vorrt q0, q1, q2122; CHECK-NEXT: vmove q0, q2123; CHECK-NEXT: vmovt q0, q2124; CHECK-NEXT: bx lr125entry:126 %0 = icmp sge <4 x i32> %a, %c127 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)128 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>129 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)130 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)131 ret <4 x i32> %4132}133 134define arm_aapcs_vfpcc <4 x i32> @vpttet_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {135; CHECK-LABEL: vpttet_block:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vpttet.s32 ge, q0, q2138; CHECK-NEXT: vorrt q0, q1, q2139; CHECK-NEXT: vmovt q0, q2140; CHECK-NEXT: vmove q0, q2141; CHECK-NEXT: vmovt q0, q2142; CHECK-NEXT: bx lr143entry:144 %0 = icmp sge <4 x i32> %a, %c145 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)146 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>147 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)148 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)149 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %4)150 ret <4 x i32> %5151}152 153define arm_aapcs_vfpcc <4 x i32> @vptett_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {154; CHECK-LABEL: vptett_block:155; CHECK: @ %bb.0: @ %entry156; CHECK-NEXT: vptett.s32 ge, q0, q2157; CHECK-NEXT: vorrt q0, q1, q2158; CHECK-NEXT: vmove q0, q2159; CHECK-NEXT: vmovt q0, q2160; CHECK-NEXT: vmovt q0, q2161; CHECK-NEXT: bx lr162entry:163 %0 = icmp sge <4 x i32> %a, %c164 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)165 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>166 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)167 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)168 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %4)169 ret <4 x i32> %5170}171 172define arm_aapcs_vfpcc <4 x i32> @vpteet_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {173; CHECK-LABEL: vpteet_block:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vpteet.s32 ge, q0, q2176; CHECK-NEXT: vorrt q0, q1, q2177; CHECK-NEXT: vmove q0, q2178; CHECK-NEXT: vmove q0, q2179; CHECK-NEXT: vmovt q0, q2180; CHECK-NEXT: bx lr181entry:182 %0 = icmp sge <4 x i32> %a, %c183 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)184 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>185 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)186 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)187 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %4)188 ret <4 x i32> %5189}190 191define arm_aapcs_vfpcc <4 x i32> @vpteee_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {192; CHECK-LABEL: vpteee_block:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: vpteee.s32 ge, q0, q2195; CHECK-NEXT: vorrt q0, q1, q2196; CHECK-NEXT: vmove q0, q2197; CHECK-NEXT: vmove q0, q2198; CHECK-NEXT: vmove q0, q2199; CHECK-NEXT: bx lr200entry:201 %0 = icmp sge <4 x i32> %a, %c202 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)203 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>204 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)205 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)206 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)207 ret <4 x i32> %5208}209 210define arm_aapcs_vfpcc <4 x i32> @vptete_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {211; CHECK-LABEL: vptete_block:212; CHECK: @ %bb.0: @ %entry213; CHECK-NEXT: vptete.s32 ge, q0, q2214; CHECK-NEXT: vorrt q0, q1, q2215; CHECK-NEXT: vmove q0, q2216; CHECK-NEXT: vmovt q0, q2217; CHECK-NEXT: vmove q0, q2218; CHECK-NEXT: bx lr219entry:220 %0 = icmp sge <4 x i32> %a, %c221 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)222 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>223 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)224 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)225 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)226 ret <4 x i32> %5227}228 229define arm_aapcs_vfpcc <4 x i32> @vpttte_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {230; CHECK-LABEL: vpttte_block:231; CHECK: @ %bb.0: @ %entry232; CHECK-NEXT: vpttte.s32 ge, q0, q2233; CHECK-NEXT: vorrt q0, q1, q2234; CHECK-NEXT: vmovt q0, q2235; CHECK-NEXT: vmovt q0, q2236; CHECK-NEXT: vmove q0, q2237; CHECK-NEXT: bx lr238entry:239 %0 = icmp sge <4 x i32> %a, %c240 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)241 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>242 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)243 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)244 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)245 ret <4 x i32> %5246}247 248define arm_aapcs_vfpcc <4 x i32> @vpttee_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {249; CHECK-LABEL: vpttee_block:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: vpttee.s32 ge, q0, q2252; CHECK-NEXT: vorrt q0, q1, q2253; CHECK-NEXT: vmovt q0, q2254; CHECK-NEXT: vmove q0, q2255; CHECK-NEXT: vmove q0, q2256; CHECK-NEXT: bx lr257entry:258 %0 = icmp sge <4 x i32> %a, %c259 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)260 %2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>261 %3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)262 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)263 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)264 ret <4 x i32> %5265}266