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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode -run-pass arm-mve-vpt-opts -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: vcmp_with_opposite_cond6alignment: 47body: |8 ; CHECK-LABEL: name: vcmp_with_opposite_cond9 ; CHECK: bb.0:10 ; CHECK-NEXT: successors: %bb.1(0x80000000)11 ; CHECK-NEXT: {{ $}}12 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF13 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF14 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gprwithzr = IMPLICIT_DEF15 ; CHECK-NEXT: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg16 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg, $noreg17 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: bb.1:19 ; CHECK-NEXT: successors: %bb.2(0x80000000)20 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg22 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32_]], 0, $noreg, $noreg23 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: bb.2:25 ; CHECK-NEXT: successors: %bb.3(0x80000000)26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg28 ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg, $noreg29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.3:31 ; CHECK-NEXT: successors: %bb.4(0x80000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg34 ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg, $noreg35 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: bb.4:37 ; CHECK-NEXT: successors: %bb.5(0x80000000)38 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg40 ; CHECK-NEXT: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg, $noreg41 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: bb.5:43 ; CHECK-NEXT: successors: %bb.6(0x80000000)44 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg46 ; CHECK-NEXT: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg, $noreg47 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: bb.6:49 ; CHECK-NEXT: successors: %bb.7(0x80000000)50 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg52 ; CHECK-NEXT: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg53 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: bb.7:55 ; CHECK-NEXT: successors: %bb.8(0x80000000)56 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg58 ; CHECK-NEXT: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg, $noreg59 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: bb.8:61 ; CHECK-NEXT: successors: %bb.9(0x80000000)62 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg64 ; CHECK-NEXT: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg, $noreg65 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: bb.9:67 ; CHECK-NEXT: successors: %bb.10(0x80000000)68 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg70 ; CHECK-NEXT: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg, $noreg71 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: bb.10:73 ; CHECK-NEXT: successors: %bb.11(0x80000000)74 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg76 ; CHECK-NEXT: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg, $noreg77 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: bb.11:79 ; CHECK-NEXT: successors: %bb.12(0x80000000)80 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: [[MVE_VCMPf16r:%[0-9]+]]:vccr = MVE_VCMPf16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg82 ; CHECK-NEXT: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16r]], 0, $noreg, $noreg83 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: bb.12:85 ; CHECK-NEXT: successors: %bb.13(0x80000000)86 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: [[MVE_VCMPf32r:%[0-9]+]]:vccr = MVE_VCMPf32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg88 ; CHECK-NEXT: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32r]], 0, $noreg, $noreg89 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: bb.13:91 ; CHECK-NEXT: successors: %bb.14(0x80000000)92 ; CHECK-NEXT: {{ $}}93 ; CHECK-NEXT: [[MVE_VCMPi16r:%[0-9]+]]:vccr = MVE_VCMPi16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg94 ; CHECK-NEXT: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16r]], 0, $noreg, $noreg95 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: bb.14:97 ; CHECK-NEXT: successors: %bb.15(0x80000000)98 ; CHECK-NEXT: {{ $}}99 ; CHECK-NEXT: [[MVE_VCMPi32r:%[0-9]+]]:vccr = MVE_VCMPi32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg100 ; CHECK-NEXT: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32r]], 0, $noreg, $noreg101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: bb.15:103 ; CHECK-NEXT: successors: %bb.16(0x80000000)104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: [[MVE_VCMPi8r:%[0-9]+]]:vccr = MVE_VCMPi8r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg106 ; CHECK-NEXT: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8r]], 0, $noreg, $noreg107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: bb.16:109 ; CHECK-NEXT: successors: %bb.17(0x80000000)110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[MVE_VCMPs16r:%[0-9]+]]:vccr = MVE_VCMPs16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg112 ; CHECK-NEXT: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16r]], 0, $noreg, $noreg113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: bb.17:115 ; CHECK-NEXT: successors: %bb.18(0x80000000)116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[MVE_VCMPs32r:%[0-9]+]]:vccr = MVE_VCMPs32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg118 ; CHECK-NEXT: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32r]], 0, $noreg, $noreg119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: bb.18:121 ; CHECK-NEXT: successors: %bb.19(0x80000000)122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: [[MVE_VCMPs8r:%[0-9]+]]:vccr = MVE_VCMPs8r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg124 ; CHECK-NEXT: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8r]], 0, $noreg, $noreg125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: bb.19:127 ; CHECK-NEXT: successors: %bb.20(0x80000000)128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[MVE_VCMPu16r:%[0-9]+]]:vccr = MVE_VCMPu16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg130 ; CHECK-NEXT: [[MVE_VPNOT19:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16r]], 0, $noreg, $noreg131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: bb.20:133 ; CHECK-NEXT: successors: %bb.21(0x80000000)134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: [[MVE_VCMPu32r:%[0-9]+]]:vccr = MVE_VCMPu32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg136 ; CHECK-NEXT: [[MVE_VPNOT20:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32r]], 0, $noreg, $noreg137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: bb.21:139 ; CHECK-NEXT: successors: %bb.22(0x80000000)140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: [[MVE_VCMPu8r:%[0-9]+]]:vccr = MVE_VCMPu8r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg142 ; CHECK-NEXT: [[MVE_VPNOT21:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r]], 0, $noreg, $noreg143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: bb.22:145 ; CHECK-NEXT: [[MVE_VCMPu8r1:%[0-9]+]]:vccr = MVE_VCMPu8r [[DEF]], $zr, 10, 0, $noreg, $noreg146 ; CHECK-NEXT: [[MVE_VPNOT22:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r1]], 0, $noreg, $noreg147 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]148 ;149 ; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs.150 ;151 bb.0:152 %1:mqpr = IMPLICIT_DEF153 %2:mqpr = IMPLICIT_DEF154 %25:gprwithzr = IMPLICIT_DEF155 %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg156 %3:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg157 158 bb.1:159 %4:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg160 %5:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg161 162 bb.2:163 %6:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg164 %7:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg165 166 bb.3:167 %8:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg168 %9:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg169 170 bb.4:171 %10:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg172 %11:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg173 174 bb.5:175 %12:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg176 %13:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg177 178 bb.6:179 %14:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg180 %15:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg181 182 bb.7:183 %16:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg184 %17:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg185 186 bb.8:187 %18:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg188 %19:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg189 190 bb.9:191 %20:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg192 %21:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg193 194 bb.10:195 %22:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg196 %23:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg197 198 bb.11:199 %24:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg200 %26:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg201 202 bb.12:203 %27:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg204 %28:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg205 206 bb.13:207 %29:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg208 %30:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg209 210 bb.14:211 %31:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg212 %32:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg213 214 bb.15:215 %33:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg216 %34:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg217 218 bb.16:219 %35:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg220 %36:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg221 222 bb.17:223 %37:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg224 %38:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg225 226 bb.18:227 %39:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg228 %40:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg229 230 bb.19:231 %41:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg232 %42:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg233 234 bb.20:235 %43:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg236 %44:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg237 238 bb.21:239 %45:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg240 %46:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg241 242 bb.22:243 ; There shouldn't be any exception for $zr, so the second VCMP should244 ; be transformed into a VPNOT.245 %47:vccr = MVE_VCMPu8r %1:mqpr, $zr, 10, 0, $noreg, $noreg246 %48:vccr = MVE_VCMPu8r %1:mqpr, $zr, 11, 0, $noreg, $noreg247 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr248...249---250name: vcmp_with_opposite_cond_and_swapped_operands251alignment: 4252body: |253 ; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands254 ; CHECK: bb.0:255 ; CHECK-NEXT: successors: %bb.1(0x80000000)256 ; CHECK-NEXT: {{ $}}257 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF258 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF259 ; CHECK-NEXT: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg260 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg, $noreg261 ; CHECK-NEXT: {{ $}}262 ; CHECK-NEXT: bb.1:263 ; CHECK-NEXT: successors: %bb.2(0x80000000)264 ; CHECK-NEXT: {{ $}}265 ; CHECK-NEXT: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg266 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg, $noreg267 ; CHECK-NEXT: {{ $}}268 ; CHECK-NEXT: bb.2:269 ; CHECK-NEXT: successors: %bb.3(0x80000000)270 ; CHECK-NEXT: {{ $}}271 ; CHECK-NEXT: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg272 ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg, $noreg273 ; CHECK-NEXT: {{ $}}274 ; CHECK-NEXT: bb.3:275 ; CHECK-NEXT: successors: %bb.4(0x80000000)276 ; CHECK-NEXT: {{ $}}277 ; CHECK-NEXT: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg278 ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg, $noreg279 ; CHECK-NEXT: {{ $}}280 ; CHECK-NEXT: bb.4:281 ; CHECK-NEXT: successors: %bb.5(0x80000000)282 ; CHECK-NEXT: {{ $}}283 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg284 ; CHECK-NEXT: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg285 ; CHECK-NEXT: {{ $}}286 ; CHECK-NEXT: bb.5:287 ; CHECK-NEXT: successors: %bb.6(0x80000000)288 ; CHECK-NEXT: {{ $}}289 ; CHECK-NEXT: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg290 ; CHECK-NEXT: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg, $noreg291 ; CHECK-NEXT: {{ $}}292 ; CHECK-NEXT: bb.6:293 ; CHECK-NEXT: successors: %bb.7(0x80000000)294 ; CHECK-NEXT: {{ $}}295 ; CHECK-NEXT: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg296 ; CHECK-NEXT: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg, $noreg297 ; CHECK-NEXT: {{ $}}298 ; CHECK-NEXT: bb.7:299 ; CHECK-NEXT: successors: %bb.8(0x80000000)300 ; CHECK-NEXT: {{ $}}301 ; CHECK-NEXT: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg302 ; CHECK-NEXT: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg, $noreg303 ; CHECK-NEXT: {{ $}}304 ; CHECK-NEXT: bb.8:305 ; CHECK-NEXT: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg306 ; CHECK-NEXT: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg, $noreg307 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]308 ;309 ; Tests that VCMPs with an opposite condition and swapped operands are310 ; correctly converted into VPNOTs.311 ;312 bb.0:313 %1:mqpr = IMPLICIT_DEF314 %2:mqpr = IMPLICIT_DEF315 %0:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg316 %3:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg317 318 bb.1:319 %4:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg320 %5:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg321 322 bb.2:323 %6:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg324 %7:vccr = MVE_VCMPi8 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg325 326 bb.3:327 %8:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg328 %9:vccr = MVE_VCMPs16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg329 330 bb.4:331 %10:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg332 %11:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg333 334 bb.5:335 %12:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg336 %13:vccr = MVE_VCMPs8 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg337 338 bb.6:339 %14:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg340 %15:vccr = MVE_VCMPu16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg341 342 bb.7:343 %16:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg344 %17:vccr = MVE_VCMPu32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg345 346 bb.8:347 %18:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg348 %19:vccr = MVE_VCMPu8 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg349 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr350 351...352 353...354---355name: triple_vcmp356alignment: 4357body: |358 ;359 ; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first360 ; becomes a VPNOT.361 ;362 bb.0:363 ; CHECK-LABEL: name: triple_vcmp364 ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg365 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg366 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg367 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr368 %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg369 %3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg370 %4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg371 tBX_RET 14, $noreg, implicit %0:mqpr372...373---374name: killed_vccr_values375alignment: 4376body: |377 ; CHECK-LABEL: name: killed_vccr_values378 ; CHECK: bb.0:379 ; CHECK-NEXT: successors: %bb.1(0x80000000)380 ; CHECK-NEXT: {{ $}}381 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF382 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF383 ; CHECK-NEXT: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg384 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VCMPf16_]], $noreg, undef [[MVE_VORR]]385 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg, $noreg386 ; CHECK-NEXT: {{ $}}387 ; CHECK-NEXT: bb.1:388 ; CHECK-NEXT: successors: %bb.2(0x80000000)389 ; CHECK-NEXT: {{ $}}390 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg391 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg392 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]393 ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg394 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]395 ; CHECK-NEXT: {{ $}}396 ; CHECK-NEXT: bb.2:397 ; CHECK-NEXT: successors: %bb.3(0x80000000)398 ; CHECK-NEXT: {{ $}}399 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg400 ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg401 ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]402 ; CHECK-NEXT: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg, $noreg403 ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR4]]404 ; CHECK-NEXT: {{ $}}405 ; CHECK-NEXT: bb.3:406 ; CHECK-NEXT: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg407 ; CHECK-NEXT: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg408 ; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR5]]409 ; CHECK-NEXT: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg410 ; CHECK-NEXT: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR6]]411 ; CHECK-NEXT: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]412 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]413 bb.0:414 ;415 ; Tests that, if the result of the VCMP is killed before the416 ; second VCMP (that will be converted into a VPNOT) is found,417 ; the kill flag is removed.418 ;419 %1:mqpr = IMPLICIT_DEF420 %2:mqpr = IMPLICIT_DEF421 %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg422 %3:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, killed %0, $noreg, undef %3423 %4:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg424 bb.1:425 ;426 ; Tests that, if the result of the VCMP that has been replaced with a427 ; VPNOT is killed (before the insertion of the second VPNOT),428 ; the kill flag is removed.429 ;430 %5:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg431 %6:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg432 %7:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, killed %6, $noreg, undef %7433 %8:mqpr = MVE_VORR %7, %7, 1, %5, $noreg, undef %8434 bb.2:435 ;436 ; Tests that the kill flag is removed when inserting a VPNOT for437 ; an instruction.438 ;439 %9:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg440 %10:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg441 %11:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %10, $noreg, undef %11442 %12:mqpr = MVE_VORR %11, %11, 1, killed %9, $noreg, undef %12443 bb.3:444 ;445 ; Tests that the kill flag is correctly removed when replacing a use446 ; of the opposite vccr, $noreg value with the last VPNOT's result447 ;448 %13:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg449 %14:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg450 %15:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %14, $noreg, undef %15451 %16:mqpr = MVE_VORR %15, %15, 1, %13, $noreg, undef %16452 %17:mqpr = MVE_VORR %16, %16, 1, killed %13, $noreg, undef %17453 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr454 455...456---457name: predicated_vcmps458alignment: 4459body: |460 ; CHECK-LABEL: name: predicated_vcmps461 ; CHECK: bb.0:462 ; CHECK-NEXT: successors: %bb.1(0x80000000)463 ; CHECK-NEXT: {{ $}}464 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF465 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF466 ; CHECK-NEXT: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg467 ; CHECK-NEXT: [[MVE_VCMPi16_1:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF1]], [[DEF]], 12, 1, [[MVE_VCMPi16_]], $noreg468 ; CHECK-NEXT: [[MVE_VCMPi16_2:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi16_]], $noreg469 ; CHECK-NEXT: {{ $}}470 ; CHECK-NEXT: bb.1:471 ; CHECK-NEXT: successors: %bb.2(0x80000000)472 ; CHECK-NEXT: {{ $}}473 ; CHECK-NEXT: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg474 ; CHECK-NEXT: [[MVE_VCMPi32_1:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF1]], [[DEF]], 12, 1, [[MVE_VCMPi32_]], $noreg475 ; CHECK-NEXT: [[MVE_VCMPi32_2:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi32_]], $noreg476 ; CHECK-NEXT: {{ $}}477 ; CHECK-NEXT: bb.2:478 ; CHECK-NEXT: successors: %bb.3(0x80000000)479 ; CHECK-NEXT: {{ $}}480 ; CHECK-NEXT: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg481 ; CHECK-NEXT: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPf16_]], $noreg482 ; CHECK-NEXT: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPf16_]], $noreg483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: bb.3:485 ; CHECK-NEXT: successors: %bb.4(0x80000000)486 ; CHECK-NEXT: {{ $}}487 ; CHECK-NEXT: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg488 ; CHECK-NEXT: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPf32_]], $noreg489 ; CHECK-NEXT: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPf32_]], $noreg490 ; CHECK-NEXT: {{ $}}491 ; CHECK-NEXT: bb.4:492 ; CHECK-NEXT: successors: %bb.5(0x80000000)493 ; CHECK-NEXT: {{ $}}494 ; CHECK-NEXT: [[MVE_VCMPi16_3:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg495 ; CHECK-NEXT: [[MVE_VCMPi16_4:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPi16_3]], $noreg496 ; CHECK-NEXT: [[MVE_VCMPi16_5:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi16_3]], $noreg497 ; CHECK-NEXT: {{ $}}498 ; CHECK-NEXT: bb.5:499 ; CHECK-NEXT: [[MVE_VCMPi32_3:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg500 ; CHECK-NEXT: [[MVE_VCMPi32_4:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPi32_3]], $noreg501 ; CHECK-NEXT: [[MVE_VCMPi32_5:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi32_3]], $noreg502 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]503 ;504 ; Tests that predicated VCMPs are not replaced.505 ;506 bb.0:507 %1:mqpr = IMPLICIT_DEF508 %2:mqpr = IMPLICIT_DEF509 %0:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg510 %3:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 1, %0, $noreg511 %4:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, %0, $noreg512 513 bb.1:514 %5:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg515 %6:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 1, %5, $noreg516 %7:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, %5, $noreg517 518 bb.2:519 %8:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg520 %9:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 1, %8, $noreg521 %10:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 1, %8, $noreg522 523 bb.3:524 %11:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg525 %12:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 1, %11, $noreg526 %13:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 1, %11, $noreg527 528 bb.4:529 %14:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg530 %15:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 1, %14, $noreg531 %16:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, %14, $noreg532 533 bb.5:534 %17:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg535 %18:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 1, %17, $noreg536 %19:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, %17, $noreg537 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr538...539---540name: flt_with_swapped_operands541alignment: 4542body: |543 ; CHECK-LABEL: name: flt_with_swapped_operands544 ; CHECK: bb.0:545 ; CHECK-NEXT: successors: %bb.1(0x80000000)546 ; CHECK-NEXT: {{ $}}547 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF548 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF549 ; CHECK-NEXT: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg550 ; CHECK-NEXT: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF1]], [[DEF]], 12, 0, $noreg, $noreg551 ; CHECK-NEXT: {{ $}}552 ; CHECK-NEXT: bb.1:553 ; CHECK-NEXT: successors: %bb.2(0x80000000)554 ; CHECK-NEXT: {{ $}}555 ; CHECK-NEXT: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg556 ; CHECK-NEXT: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF1]], [[DEF]], 12, 0, $noreg, $noreg557 ; CHECK-NEXT: {{ $}}558 ; CHECK-NEXT: bb.2:559 ; CHECK-NEXT: successors: %bb.3(0x80000000)560 ; CHECK-NEXT: {{ $}}561 ; CHECK-NEXT: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg562 ; CHECK-NEXT: [[MVE_VCMPf16_3:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF1]], [[DEF]], 11, 0, $noreg, $noreg563 ; CHECK-NEXT: {{ $}}564 ; CHECK-NEXT: bb.3:565 ; CHECK-NEXT: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg566 ; CHECK-NEXT: [[MVE_VCMPf32_3:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF1]], [[DEF]], 11, 0, $noreg, $noreg567 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]568 ;569 ; Tests that float VCMPs with an opposite condition and swapped operands570 ; are not transformed into VPNOTs.571 ;572 bb.0:573 %1:mqpr = IMPLICIT_DEF574 %2:mqpr = IMPLICIT_DEF575 %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg576 %3:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg577 578 bb.1:579 %4:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg580 %5:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg581 582 bb.2:583 %6:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg584 %7:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg585 586 bb.3:587 %8:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg588 %9:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg589 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr590 591...592---593name: different_opcodes594alignment: 4595body: |596 ;597 ; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP598 ; is not transformed into a VPNOT.599 ;600 bb.0:601 ; CHECK-LABEL: name: different_opcodes602 ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg, $noreg603 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg, $noreg604 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr605 %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg, $noreg606 %3:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg, $noreg607 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr608...609---610name: incorrect_condcode611alignment: 4612body: |613 ; CHECK-LABEL: name: incorrect_condcode614 ; CHECK: bb.0:615 ; CHECK-NEXT: successors: %bb.1(0x80000000)616 ; CHECK-NEXT: {{ $}}617 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF618 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF619 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg620 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF1]], [[DEF]], 11, 0, $noreg, $noreg621 ; CHECK-NEXT: {{ $}}622 ; CHECK-NEXT: bb.1:623 ; CHECK-NEXT: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg624 ; CHECK-NEXT: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 12, 0, $noreg, $noreg625 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]626 ;627 ; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not628 ; the opposite CondCode.629 ;630 bb.0:631 %1:mqpr = IMPLICIT_DEF632 %2:mqpr = IMPLICIT_DEF633 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg634 %3:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg635 636 bb.1:637 %4:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg638 %5:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg639 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr640 641...642---643name: vpr_or_vccr_write_between_vcmps644alignment: 4645body: |646 ;647 ; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if648 ; VCCR/VPR is written to in-between.649 ;650 bb.0:651 ; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps652 ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg653 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed [[MVE_VCMPs32_]], 0, $noreg, $noreg654 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg655 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr656 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg657 %3:vccr = MVE_VPNOT killed %0, 0, $noreg, $noreg658 %4:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg659 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr660...661---662name: spill_prevention663alignment: 4664body: |665 ; CHECK-LABEL: name: spill_prevention666 ; CHECK: bb.0:667 ; CHECK-NEXT: successors: %bb.1(0x80000000)668 ; CHECK-NEXT: {{ $}}669 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF670 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF671 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr = IMPLICIT_DEF672 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg673 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg674 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]675 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg676 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]677 ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg678 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]679 ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg680 ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]681 ; CHECK-NEXT: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg, $noreg682 ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR4]]683 ; CHECK-NEXT: {{ $}}684 ; CHECK-NEXT: bb.1:685 ; CHECK-NEXT: successors: %bb.2(0x80000000)686 ; CHECK-NEXT: {{ $}}687 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg688 ; CHECK-NEXT: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg689 ; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR5]]690 ; CHECK-NEXT: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 0, $noreg, $noreg, undef [[MVE_VORR6]]691 ; CHECK-NEXT: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg692 ; CHECK-NEXT: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]693 ; CHECK-NEXT: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 0, $noreg, $noreg, undef [[MVE_VORR8]]694 ; CHECK-NEXT: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT6]], 0, $noreg, $noreg695 ; CHECK-NEXT: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT7]], $noreg, undef [[MVE_VORR9]]696 ; CHECK-NEXT: {{ $}}697 ; CHECK-NEXT: bb.2:698 ; CHECK-NEXT: successors: %bb.3(0x80000000)699 ; CHECK-NEXT: {{ $}}700 ; CHECK-NEXT: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg701 ; CHECK-NEXT: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg702 ; CHECK-NEXT: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR10]]703 ; CHECK-NEXT: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR11]]704 ; CHECK-NEXT: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg, $noreg705 ; CHECK-NEXT: [[MVE_VORR12:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR11]], [[MVE_VORR11]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR12]]706 ; CHECK-NEXT: [[MVE_VORR13:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR12]], [[MVE_VORR12]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR13]]707 ; CHECK-NEXT: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg, $noreg708 ; CHECK-NEXT: [[MVE_VORR14:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR13]], [[MVE_VORR13]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR14]]709 ; CHECK-NEXT: [[MVE_VORR15:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR14]], [[MVE_VORR14]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR15]]710 ; CHECK-NEXT: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT10]], 0, $noreg, $noreg711 ; CHECK-NEXT: [[MVE_VORR16:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR15]], [[MVE_VORR15]], 1, [[MVE_VPNOT11]], $noreg, undef [[MVE_VORR16]]712 ; CHECK-NEXT: [[MVE_VORR17:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR16]], [[MVE_VORR16]], 1, [[MVE_VPNOT11]], $noreg, undef [[MVE_VORR17]]713 ; CHECK-NEXT: {{ $}}714 ; CHECK-NEXT: bb.3:715 ; CHECK-NEXT: successors: %bb.4(0x80000000)716 ; CHECK-NEXT: {{ $}}717 ; CHECK-NEXT: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg718 ; CHECK-NEXT: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_3]], 0, $noreg, $noreg719 ; CHECK-NEXT: [[MVE_VORR18:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT12]], $noreg, undef [[MVE_VORR11]]720 ; CHECK-NEXT: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT12]], 0, $noreg, $noreg721 ; CHECK-NEXT: [[MVE_VORR19:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT13]], $noreg, undef [[MVE_VORR19]]722 ; CHECK-NEXT: {{ $}}723 ; CHECK-NEXT: bb.4:724 ; CHECK-NEXT: [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed [[DEF2]], 14 /* CC::al */, $noreg725 ; CHECK-NEXT: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[VMSR_P0_]], 0, $noreg, $noreg726 ; CHECK-NEXT: [[MVE_VORR20:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR19]], [[MVE_VORR19]], 1, [[MVE_VPNOT14]], $noreg, undef [[MVE_VORR20]]727 ; CHECK-NEXT: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT14]], 0, $noreg, $noreg728 ; CHECK-NEXT: [[MVE_VORR21:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR20]], [[MVE_VORR20]], 1, [[MVE_VPNOT15]], $noreg, undef [[MVE_VORR21]]729 ; CHECK-NEXT: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT15]], 0, $noreg, $noreg730 ; CHECK-NEXT: [[MVE_VORR22:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR21]], [[MVE_VORR21]], 1, [[MVE_VPNOT16]], $noreg, undef [[MVE_VORR22]]731 ; CHECK-NEXT: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT16]], 0, $noreg, $noreg732 ; CHECK-NEXT: [[MVE_VORR23:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR22]], [[MVE_VORR22]], 1, [[MVE_VPNOT17]], $noreg, undef [[MVE_VORR23]]733 ; CHECK-NEXT: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT17]], 0, $noreg, $noreg734 ; CHECK-NEXT: [[MVE_VORR24:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR23]], [[MVE_VORR23]], 1, [[MVE_VPNOT18]], $noreg, undef [[MVE_VORR24]]735 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]736 bb.0:737 ;738 ; Basic test case739 ;740 741 %1:mqpr = IMPLICIT_DEF742 %2:mqpr = IMPLICIT_DEF743 %32:gpr = IMPLICIT_DEF744 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg745 %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg746 %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4747 %5:mqpr = MVE_VORR %4, %4, 1, %0, $noreg, undef %5748 %6:mqpr = MVE_VORR %5, %5, 1, %3, $noreg, undef %6749 %7:mqpr = MVE_VORR %6, %6, 1, %0, $noreg, undef %7750 %8:mqpr = MVE_VORR %7, %7, 1, %3, $noreg, undef %8751 bb.1:752 ;753 ; Tests that unpredicated instructions in the middle of the block754 ; don't interfere with the replacement.755 ;756 %9:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg757 %10:vccr = MVE_VPNOT %9, 0, $noreg, $noreg758 %11:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %10, $noreg, undef %11759 %12:mqpr = MVE_VORR %11, %11, 0, $noreg, $noreg, undef %12760 %13:mqpr = MVE_VORR %12, %12, 1, %9, $noreg, undef %13761 %14:mqpr = MVE_VORR %13, %13, 0, $noreg, $noreg, undef %14762 %15:mqpr = MVE_VORR %14, %14, 1, %10, $noreg, undef %15763 bb.2:764 ;765 ; Tests that all uses of the register are replaced, even when it's used766 ; multiple times in a row.767 ;768 %16:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg769 %17:vccr = MVE_VPNOT %16, 0, $noreg, $noreg770 %18:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %17, $noreg, undef %18771 %19:mqpr = MVE_VORR %18, %18, 1, %17, $noreg, undef %19772 %20:mqpr = MVE_VORR %19, %19, 1, %16, $noreg, undef %20773 %21:mqpr = MVE_VORR %20, %20, 1, %16, $noreg, undef %21774 %22:mqpr = MVE_VORR %21, %21, 1, %17, $noreg, undef %22775 %23:mqpr = MVE_VORR %22, %22, 1, %17, $noreg, undef %23776 %24:mqpr = MVE_VORR %23, %23, 1, %16, $noreg, undef %24777 %25:mqpr = MVE_VORR %24, %24, 1, %16, $noreg, undef %25778 779 bb.3:780 ;781 ; Tests that already present VPNOTs are "registered" by the pass so782 ; it does not insert a useless VPNOT.783 ;784 %26:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg785 %27:vccr = MVE_VPNOT %26, 0, $noreg, $noreg786 %28:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %27, $noreg, undef %19787 %29:vccr = MVE_VPNOT %27, 0, $noreg, $noreg788 %30:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %26, $noreg, undef %30789 bb.4:790 ;791 ; Tests that the pass works with instructions other than vcmp.792 ;793 %31:vccr = VMSR_P0 killed %32:gpr, 14 /* CC::al */, $noreg794 %33:vccr = MVE_VPNOT %31, 0, $noreg, $noreg795 %34:mqpr = MVE_VORR %30, %30, 1, %33, $noreg, undef %34796 %35:mqpr = MVE_VORR %34, %34, 1, %31, $noreg, undef %35797 %36:mqpr = MVE_VORR %35, %35, 1, %33, $noreg, undef %36798 %37:mqpr = MVE_VORR %36, %36, 1, %31, $noreg, undef %37799 %38:mqpr = MVE_VORR %37, %37, 1, %33, $noreg, undef %38800 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr801...802---803name: spill_prevention_multi804alignment: 4805body: |806 bb.0:807 ;808 ; Tests that multiple groups of predicated instructions in the same basic block are optimized.809 ;810 ; CHECK-LABEL: name: spill_prevention_multi811 ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg812 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg813 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]814 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg815 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]816 ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg817 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]818 ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg819 ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]820 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg821 ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR4]]822 ; CHECK-NEXT: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg823 ; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR5]]824 ; CHECK-NEXT: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT4]], 0, $noreg, $noreg825 ; CHECK-NEXT: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR6]]826 ; CHECK-NEXT: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg827 ; CHECK-NEXT: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]828 ; CHECK-NEXT: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg829 ; CHECK-NEXT: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg830 ; CHECK-NEXT: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT7]], $noreg, undef [[MVE_VORR8]]831 ; CHECK-NEXT: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT7]], 0, $noreg, $noreg832 ; CHECK-NEXT: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR9]]833 ; CHECK-NEXT: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg, $noreg834 ; CHECK-NEXT: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR9]], [[MVE_VORR9]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR10]]835 ; CHECK-NEXT: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg, $noreg836 ; CHECK-NEXT: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR11]]837 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr838 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg839 %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg840 %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4841 %5:mqpr = MVE_VORR %4, %4, 1, %0, $noreg, undef %5842 %6:mqpr = MVE_VORR %5, %5, 1, %3, $noreg, undef %6843 %7:mqpr = MVE_VORR %6, %6, 1, %0, $noreg, undef %7844 %8:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg845 %9:vccr = MVE_VPNOT %8, 0, $noreg, $noreg846 %10:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %8, $noreg, undef %10847 %11:mqpr = MVE_VORR %10, %10, 1, %9, $noreg, undef %11848 %12:mqpr = MVE_VORR %11, %11, 1, %8, $noreg, undef %12849 %13:mqpr = MVE_VORR %12, %12, 1, %9, $noreg, undef %13850 %14:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg851 %15:vccr = MVE_VPNOT %14, 0, $noreg, $noreg852 %16:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %15, $noreg, undef %16853 %17:mqpr = MVE_VORR %16, %16, 1, %14, $noreg, undef %17854 %18:mqpr = MVE_VORR %17, %17, 1, %15, $noreg, undef %18855 %19:mqpr = MVE_VORR %18, %18, 1, %14, $noreg, undef %19856 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr857...858---859name: spill_prevention_predicated_vpnots860alignment: 4861body: |862 ; CHECK-LABEL: name: spill_prevention_predicated_vpnots863 ; CHECK: bb.0:864 ; CHECK-NEXT: successors: %bb.1(0x80000000)865 ; CHECK-NEXT: {{ $}}866 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF867 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF868 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg869 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_]], $noreg870 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR]]871 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR1]]872 ; CHECK-NEXT: {{ $}}873 ; CHECK-NEXT: bb.1:874 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg875 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_1]], $noreg876 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR]]877 ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR1]]878 ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF]], 1, [[MVE_VPNOT1]], $noreg, undef %11:mqpr879 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]880 ;881 ; Tests that predicated VPNOTs are not considered by this pass882 ; (This means that these examples should not be optimized.)883 ;884 bb.0:885 %1:mqpr = IMPLICIT_DEF886 %2:mqpr = IMPLICIT_DEF887 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg888 %3:vccr = MVE_VPNOT %0, 1, %0, $noreg889 %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %0, $noreg, undef %4890 %5:mqpr = MVE_VORR %4, %4, 1, %3, $noreg, undef %5891 bb.1:892 %6:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg893 %7:vccr = MVE_VPNOT %0, 1, %6, $noreg894 %8:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, %7, $noreg, undef %4895 %9:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %6, $noreg, undef %5896 %10:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, %7, $noreg, undef %11:mqpr897 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr898...899---900name: spill_prevention_copies901alignment: 4902body: |903 ;904 ; Tests that VPNOTs are replaced by a COPY instead of inserting a VPNOT905 ; (which would result in a double VPNOT).906 ;907 bb.0:908 ; CHECK-LABEL: name: spill_prevention_copies909 ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg910 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg911 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]912 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR1]]913 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR2]]914 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr915 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg916 %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg917 %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4918 %5:vccr = MVE_VPNOT %0, 0, $noreg, $noreg919 %6:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %5, $noreg, undef %6920 %7:vccr = MVE_VPNOT %0, 0, $noreg, $noreg921 %8:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %7, $noreg, undef %8922 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr923 924...925---926name: spill_prevention_vpnot_reordering927alignment: 4928body: |929 ; CHECK-LABEL: name: spill_prevention_vpnot_reordering930 ; CHECK: bb.0:931 ; CHECK-NEXT: successors: %bb.1(0x80000000)932 ; CHECK-NEXT: {{ $}}933 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF934 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF935 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg936 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR]]937 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR1]]938 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg939 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR1]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR2]]940 ; CHECK-NEXT: {{ $}}941 ; CHECK-NEXT: bb.1:942 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg943 ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR3]]944 ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR4]]945 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg946 ; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR4]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR5]]947 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]948 ;949 ; Tests that the first VPNOT is moved down when the result of the VCMP is used950 ; before the first usage of the VPNOT's result.951 ;952 bb.0:953 %1:mqpr = IMPLICIT_DEF954 %2:mqpr = IMPLICIT_DEF955 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg956 %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg957 %4:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, %0, $noreg, undef %4958 %5:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, %0, $noreg, undef %5959 %6:mqpr = MVE_VORR %4, %5, 1, %3, $noreg, undef %6960 961 bb.1:962 ; Test again with a "killed" flag to check if it's properly removed.963 %7:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg964 %8:vccr = MVE_VPNOT %7, 0, $noreg, $noreg965 %9:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, %7, $noreg, undef %9966 %10:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, killed %7, $noreg, undef %10967 %11:mqpr = MVE_VORR %9, %10, 1, %8, $noreg, undef %11968 tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr969...970---971name: spill_prevention_stop_after_write972alignment: 4973body: |974 ; CHECK-LABEL: name: spill_prevention_stop_after_write975 ; CHECK: bb.0:976 ; CHECK-NEXT: successors: %bb.1(0x80000000)977 ; CHECK-NEXT: {{ $}}978 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF979 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF980 ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg981 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg982 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]983 ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg984 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]985 ; CHECK-NEXT: [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed %7:gpr, 14 /* CC::al */, $noreg986 ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR2]]987 ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR3]]988 ; CHECK-NEXT: {{ $}}989 ; CHECK-NEXT: bb.1:990 ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg991 ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg992 ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR]]993 ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg994 ; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR5]]995 ; CHECK-NEXT: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF1]], [[DEF]], 10, 0, $noreg, $noreg996 ; CHECK-NEXT: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR6]]997 ; CHECK-NEXT: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR7]]998 ; CHECK-NEXT: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR8]]999 ;1000 ; Tests that the optimisation stops when it sees an instruction1001 ; that writes to VPR, and that doesn't use any of the registers we care about.1002 ;1003 bb.0:1004 %1:mqpr = IMPLICIT_DEF1005 %2:mqpr = IMPLICIT_DEF1006 %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg1007 %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg1008 %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %41009 %5:mqpr = MVE_VORR %4, %4, 1, %0, $noreg, undef %51010 %6:vccr = VMSR_P0 killed %7:gpr, 14 /* CC::al */, $noreg1011 %8:mqpr = MVE_VORR %5, %5, 1, %0, $noreg, undef %81012 %9:mqpr = MVE_VORR %8, %8, 1, %3, $noreg, undef %91013 1014 bb.1:1015 %10:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg1016 %11:vccr = MVE_VPNOT %10, 0, $noreg, $noreg1017 %12:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %11, $noreg, undef %41018 %13:mqpr = MVE_VORR %12, %12, 1, %10, $noreg, undef %131019 %14:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg1020 %15:mqpr = MVE_VORR %13, %13, 1, %11, $noreg, undef %151021 %16:mqpr = MVE_VORR %15, %15, 1, %10, $noreg, undef %161022 %17:mqpr = MVE_VORR %16, %16, 1, %11, $noreg, undef %171023...1024---1025name: reuse_kill_flags1026alignment: 41027body: |1028 bb.0:1029 ; CHECK-LABEL: name: reuse_kill_flags1030 ; CHECK: [[t2MOVi:%[0-9]+]]:tgpreven = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg1031 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vccr = COPY [[t2MOVi]]1032 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF1033 ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[COPY]], $noreg, undef [[MVE_VORR]]1034 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF1035 ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF1]], 1, killed [[COPY]], $noreg, undef [[MVE_VORR1]]1036 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF1]]1037 %0:tgpreven = t2MOVi 0, 14, $noreg, $noreg1038 %1:vccr = COPY %0:tgpreven1039 %2:mqpr = IMPLICIT_DEF1040 %3:mqpr = MVE_VORR %2:mqpr, %2:mqpr, 1, killed %1, $noreg, undef %31041 %4:vccr = COPY %0:tgpreven1042 %5:mqpr = IMPLICIT_DEF1043 %6:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, killed %4, $noreg, undef %61044 tBX_RET 14 /* CC::al */, $noreg, implicit %5:mqpr1045...1046---1047name: kill_flags_21048alignment: 41049body: |1050 bb.0:1051 ; CHECK-LABEL: name: kill_flags_21052 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01053 ; CHECK-NEXT: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg1054 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vccr = COPY [[t2MOVi]]1055 ; CHECK-NEXT: [[MVE_VHADDs8_:%[0-9]+]]:mqpr = MVE_VHADDs8 [[COPY]], [[COPY]], 1, [[COPY1]], $noreg, [[COPY]]1056 ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[COPY1]], 0, $noreg, $noreg1057 ; CHECK-NEXT: [[MVE_VSLIimm8_:%[0-9]+]]:mqpr = MVE_VSLIimm8 [[MVE_VHADDs8_]], [[COPY]], 0, 1, [[MVE_VPNOT]], $noreg1058 ; CHECK-NEXT: $q0 = COPY [[MVE_VSLIimm8_]]1059 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $q01060 %0:mqpr = COPY $q01061 %1:rgpr = t2MOVi 0, 14, $noreg, $noreg1062 %2:vccr = COPY %1:rgpr1063 %3:mqpr = MVE_VHADDs8 %0:mqpr, %0:mqpr, 1, killed %2:vccr, $noreg, %0:mqpr1064 %4:rgpr = t2MOVi16 65535, 14, $noreg1065 %5:vccr = COPY %4:rgpr1066 %6:mqpr = MVE_VSLIimm8 %3:mqpr, %0:mqpr, 0, 1, killed %5:vccr, $noreg1067 $q0 = COPY %6:mqpr1068 tBX_RET 14, $noreg, implicit $q01069...1070