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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc i32 @vqdmulh_v16i8(<16 x i8> %s0, <16 x i8> %s1) {5; CHECK-LABEL: vqdmulh_v16i8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqdmulh.s8 q0, q1, q08; CHECK-NEXT: vaddv.s8 r0, q09; CHECK-NEXT: bx lr10entry:11 %l2 = sext <16 x i8> %s0 to <16 x i32>12 %l5 = sext <16 x i8> %s1 to <16 x i32>13 %l6 = mul nsw <16 x i32> %l5, %l214 %l7 = ashr <16 x i32> %l6, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>15 %l8 = icmp slt <16 x i32> %l7, <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>16 %l9 = select <16 x i1> %l8, <16 x i32> %l7, <16 x i32> <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>17 %l10 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %l9)18 ret i32 %l1019}20 21define arm_aapcs_vfpcc <16 x i8> @vqdmulh_v16i8_b(<16 x i8> %s0, <16 x i8> %s1) {22; CHECK-LABEL: vqdmulh_v16i8_b:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vqdmulh.s8 q0, q1, q025; CHECK-NEXT: bx lr26entry:27 %l2 = sext <16 x i8> %s0 to <16 x i32>28 %l5 = sext <16 x i8> %s1 to <16 x i32>29 %l6 = mul nsw <16 x i32> %l5, %l230 %l7 = ashr <16 x i32> %l6, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>31 %l8 = icmp slt <16 x i32> %l7, <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>32 %l9 = select <16 x i1> %l8, <16 x i32> %l7, <16 x i32> <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>33 %l10 = trunc <16 x i32> %l9 to <16 x i8>34 ret <16 x i8> %l1035}36 37define arm_aapcs_vfpcc <8 x i8> @vqdmulh_v8i8_b(<8 x i8> %s0, <8 x i8> %s1) {38; CHECK-LABEL: vqdmulh_v8i8_b:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vqdmulh.s8 q0, q1, q041; CHECK-NEXT: vmovlb.s8 q0, q042; CHECK-NEXT: bx lr43entry:44 %l2 = sext <8 x i8> %s0 to <8 x i32>45 %l5 = sext <8 x i8> %s1 to <8 x i32>46 %l6 = mul nsw <8 x i32> %l5, %l247 %l7 = ashr <8 x i32> %l6, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>48 %l8 = icmp slt <8 x i32> %l7, <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>49 %l9 = select <8 x i1> %l8, <8 x i32> %l7, <8 x i32> <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>50 %l10 = trunc <8 x i32> %l9 to <8 x i8>51 ret <8 x i8> %l1052}53 54define arm_aapcs_vfpcc <4 x i8> @vqdmulh_v4i8_b(<4 x i8> %s0, <4 x i8> %s1) {55; CHECK-LABEL: vqdmulh_v4i8_b:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vqdmulh.s8 q0, q1, q058; CHECK-NEXT: vmovlb.s8 q0, q059; CHECK-NEXT: vmovlb.s16 q0, q060; CHECK-NEXT: bx lr61entry:62 %l2 = sext <4 x i8> %s0 to <4 x i32>63 %l5 = sext <4 x i8> %s1 to <4 x i32>64 %l6 = mul nsw <4 x i32> %l5, %l265 %l7 = ashr <4 x i32> %l6, <i32 7, i32 7, i32 7, i32 7>66 %l8 = icmp slt <4 x i32> %l7, <i32 127, i32 127, i32 127, i32 127>67 %l9 = select <4 x i1> %l8, <4 x i32> %l7, <4 x i32> <i32 127, i32 127, i32 127, i32 127>68 %l10 = trunc <4 x i32> %l9 to <4 x i8>69 ret <4 x i8> %l1070}71 72define arm_aapcs_vfpcc <32 x i8> @vqdmulh_v32i8_b(<32 x i8> %s0, <32 x i8> %s1) {73; CHECK-LABEL: vqdmulh_v32i8_b:74; CHECK: @ %bb.0: @ %entry75; CHECK-NEXT: vqdmulh.s8 q0, q2, q076; CHECK-NEXT: vqdmulh.s8 q1, q3, q177; CHECK-NEXT: bx lr78entry:79 %l2 = sext <32 x i8> %s0 to <32 x i32>80 %l5 = sext <32 x i8> %s1 to <32 x i32>81 %l6 = mul nsw <32 x i32> %l5, %l282 %l7 = ashr <32 x i32> %l6, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>83 %l8 = icmp slt <32 x i32> %l7, <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>84 %l9 = select <32 x i1> %l8, <32 x i32> %l7, <32 x i32> <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>85 %l10 = trunc <32 x i32> %l9 to <32 x i8>86 ret <32 x i8> %l1087}88 89define arm_aapcs_vfpcc i32 @vqdmulh_v8i16(<8 x i16> %s0, <8 x i16> %s1) {90; CHECK-LABEL: vqdmulh_v8i16:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vqdmulh.s16 q0, q1, q093; CHECK-NEXT: vaddv.s16 r0, q094; CHECK-NEXT: bx lr95entry:96 %l2 = sext <8 x i16> %s0 to <8 x i32>97 %l5 = sext <8 x i16> %s1 to <8 x i32>98 %l6 = mul nsw <8 x i32> %l5, %l299 %l7 = ashr <8 x i32> %l6, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>100 %l8 = icmp slt <8 x i32> %l7, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>101 %l9 = select <8 x i1> %l8, <8 x i32> %l7, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>102 %l10 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %l9)103 ret i32 %l10104}105 106define arm_aapcs_vfpcc <8 x i16> @vqdmulh_v8i16_b(<8 x i16> %s0, <8 x i16> %s1) {107; CHECK-LABEL: vqdmulh_v8i16_b:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vqdmulh.s16 q0, q1, q0110; CHECK-NEXT: bx lr111entry:112 %l2 = sext <8 x i16> %s0 to <8 x i32>113 %l5 = sext <8 x i16> %s1 to <8 x i32>114 %l6 = mul nsw <8 x i32> %l5, %l2115 %l7 = ashr <8 x i32> %l6, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>116 %l8 = icmp slt <8 x i32> %l7, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>117 %l9 = select <8 x i1> %l8, <8 x i32> %l7, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>118 %l10 = trunc <8 x i32> %l9 to <8 x i16>119 ret <8 x i16> %l10120}121 122define arm_aapcs_vfpcc <4 x i16> @vqdmulh_v4i16_b(<4 x i16> %s0, <4 x i16> %s1) {123; CHECK-LABEL: vqdmulh_v4i16_b:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vqdmulh.s16 q0, q1, q0126; CHECK-NEXT: vmovlb.s16 q0, q0127; CHECK-NEXT: bx lr128entry:129 %l2 = sext <4 x i16> %s0 to <4 x i32>130 %l5 = sext <4 x i16> %s1 to <4 x i32>131 %l6 = mul nsw <4 x i32> %l5, %l2132 %l7 = ashr <4 x i32> %l6, <i32 15, i32 15, i32 15, i32 15>133 %l4 = icmp slt <4 x i32> %l7, <i32 32767, i32 32767, i32 32767, i32 32767>134 %l9 = select <4 x i1> %l4, <4 x i32> %l7, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>135 %l10 = trunc <4 x i32> %l9 to <4 x i16>136 ret <4 x i16> %l10137}138 139define arm_aapcs_vfpcc <16 x i16> @vqdmulh_v16i16_b(<16 x i16> %s0, <16 x i16> %s1) {140; CHECK-LABEL: vqdmulh_v16i16_b:141; CHECK: @ %bb.0: @ %entry142; CHECK-NEXT: vqdmulh.s16 q0, q2, q0143; CHECK-NEXT: vqdmulh.s16 q1, q3, q1144; CHECK-NEXT: bx lr145entry:146 %l2 = sext <16 x i16> %s0 to <16 x i32>147 %l5 = sext <16 x i16> %s1 to <16 x i32>148 %l6 = mul nsw <16 x i32> %l5, %l2149 %l7 = ashr <16 x i32> %l6, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>150 %l16 = icmp slt <16 x i32> %l7, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>151 %l9 = select <16 x i1> %l16, <16 x i32> %l7, <16 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>152 %l10 = trunc <16 x i32> %l9 to <16 x i16>153 ret <16 x i16> %l10154}155 156define arm_aapcs_vfpcc <8 x i16> @vqdmulh_v8i16_c(<8 x i16> %s0, <8 x i16> %s1) {157; CHECK-LABEL: vqdmulh_v8i16_c:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: .pad #16160; CHECK-NEXT: sub sp, #16161; CHECK-NEXT: vmov.u16 r0, q0[6]162; CHECK-NEXT: vmov.u16 r1, q0[4]163; CHECK-NEXT: vmov q2[2], q2[0], r1, r0164; CHECK-NEXT: vmov.u16 r0, q0[7]165; CHECK-NEXT: vmov.u16 r1, q0[5]166; CHECK-NEXT: vmov.u16 r2, q0[0]167; CHECK-NEXT: vmov q2[3], q2[1], r1, r0168; CHECK-NEXT: vmov.u16 r0, q1[6]169; CHECK-NEXT: vmov.u16 r1, q1[4]170; CHECK-NEXT: vmov q3[2], q3[0], r1, r0171; CHECK-NEXT: vmov.u16 r0, q1[7]172; CHECK-NEXT: vmov.u16 r1, q1[5]173; CHECK-NEXT: vmov q3[3], q3[1], r1, r0174; CHECK-NEXT: mov r0, sp175; CHECK-NEXT: vmullb.s16 q2, q3, q2176; CHECK-NEXT: vmov.u16 r1, q0[2]177; CHECK-NEXT: vshl.i32 q2, q2, #10178; CHECK-NEXT: vshr.s32 q2, q2, #10179; CHECK-NEXT: vshr.s32 q2, q2, #15180; CHECK-NEXT: vstrh.32 q2, [r0, #8]181; CHECK-NEXT: vmov q2[2], q2[0], r2, r1182; CHECK-NEXT: vmov.u16 r1, q0[3]183; CHECK-NEXT: vmov.u16 r2, q0[1]184; CHECK-NEXT: vmov q2[3], q2[1], r2, r1185; CHECK-NEXT: vmov.u16 r1, q1[2]186; CHECK-NEXT: vmov.u16 r2, q1[0]187; CHECK-NEXT: vmov q0[2], q0[0], r2, r1188; CHECK-NEXT: vmov.u16 r1, q1[3]189; CHECK-NEXT: vmov.u16 r2, q1[1]190; CHECK-NEXT: vmov q0[3], q0[1], r2, r1191; CHECK-NEXT: vmullb.s16 q0, q0, q2192; CHECK-NEXT: vshl.i32 q0, q0, #10193; CHECK-NEXT: vshr.s32 q0, q0, #10194; CHECK-NEXT: vshr.s32 q0, q0, #15195; CHECK-NEXT: vstrh.32 q0, [r0]196; CHECK-NEXT: vldrw.u32 q0, [r0]197; CHECK-NEXT: add sp, #16198; CHECK-NEXT: bx lr199entry:200 %l2 = sext <8 x i16> %s0 to <8 x i22>201 %l5 = sext <8 x i16> %s1 to <8 x i22>202 %l6 = mul nsw <8 x i22> %l5, %l2203 %l7 = ashr <8 x i22> %l6, <i22 15, i22 15, i22 15, i22 15, i22 15, i22 15, i22 15, i22 15>204 %l8 = icmp slt <8 x i22> %l7, <i22 32767, i22 32767, i22 32767, i22 32767, i22 32767, i22 32767, i22 32767, i22 32767>205 %l9 = select <8 x i1> %l8, <8 x i22> %l7, <8 x i22> <i22 32767, i22 32767, i22 32767, i22 32767, i22 32767, i22 32767, i22 32767, i22 32767>206 %l10 = trunc <8 x i22> %l9 to <8 x i16>207 ret <8 x i16> %l10208}209 210define arm_aapcs_vfpcc <8 x i16> @vqdmulh_v8i16_interleaved(<8 x i16> %s0, <8 x i16> %s1) {211; CHECK-LABEL: vqdmulh_v8i16_interleaved:212; CHECK: @ %bb.0: @ %entry213; CHECK-NEXT: vqdmulh.s16 q0, q1, q0214; CHECK-NEXT: bx lr215entry:216 %0 = shufflevector <8 x i16> %s0, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>217 %1 = sext <8 x i16> %0 to <8 x i32>218 %l2 = sext <8 x i16> %s0 to <8 x i32>219 %2 = shufflevector <8 x i16> %s1, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>220 %3 = sext <8 x i16> %2 to <8 x i32>221 %l5 = sext <8 x i16> %s1 to <8 x i32>222 %l6 = mul nsw <8 x i32> %3, %1223 %l7 = ashr <8 x i32> %l6, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>224 %l8 = icmp slt <8 x i32> %l7, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>225 %l9 = select <8 x i1> %l8, <8 x i32> %l7, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>226 %l10 = trunc <8 x i32> %l9 to <8 x i16>227 %4 = shufflevector <8 x i16> %l10, <8 x i16> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>228 ret <8 x i16> %4229}230 231define arm_aapcs_vfpcc <8 x i16> @vqdmulh_v8i16_interleaved2(<4 x i32> %s0a, <8 x i16> %s1) {232; CHECK-LABEL: vqdmulh_v8i16_interleaved2:233; CHECK: @ %bb.0:234; CHECK-NEXT: vqdmulh.s16 q2, q1, q0235; CHECK-NEXT: vrev32.16 q1, q1236; CHECK-NEXT: vqdmulh.s16 q0, q1, q0237; CHECK-NEXT: vmovnt.i32 q2, q0238; CHECK-NEXT: vmov q0, q2239; CHECK-NEXT: bx lr240 %s0 = trunc <4 x i32> %s0a to <4 x i16>241 %strided.vec = shufflevector <8 x i16> %s1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>242 %strided.vec44 = shufflevector <8 x i16> %s1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>243 %l7 = sext <4 x i16> %strided.vec to <4 x i32>244 %l8 = sext <4 x i16> %s0 to <4 x i32>245 %l9 = mul nsw <4 x i32> %l7, %l8246 %l10 = ashr <4 x i32> %l9, <i32 15, i32 15, i32 15, i32 15>247 %l11 = icmp slt <4 x i32> %l10, <i32 32767, i32 32767, i32 32767, i32 32767>248 %l12 = select <4 x i1> %l11, <4 x i32> %l10, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>249 %l13 = trunc <4 x i32> %l12 to <4 x i16>250 %l14 = sext <4 x i16> %strided.vec44 to <4 x i32>251 %l15 = mul nsw <4 x i32> %l14, %l8252 %l16 = ashr <4 x i32> %l15, <i32 15, i32 15, i32 15, i32 15>253 %l17 = icmp slt <4 x i32> %l16, <i32 32767, i32 32767, i32 32767, i32 32767>254 %l18 = select <4 x i1> %l17, <4 x i32> %l16, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>255 %l19 = trunc <4 x i32> %l18 to <4 x i16>256 %interleaved.vec = shufflevector <4 x i16> %l13, <4 x i16> %l19, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>257 ret <8 x i16> %interleaved.vec258}259 260define arm_aapcs_vfpcc i64 @vqdmulh_v4i32(<4 x i32> %s0, <4 x i32> %s1) {261; CHECK-LABEL: vqdmulh_v4i32:262; CHECK: @ %bb.0: @ %entry263; CHECK-NEXT: vqdmulh.s32 q0, q1, q0264; CHECK-NEXT: vaddlv.s32 r0, r1, q0265; CHECK-NEXT: bx lr266entry:267 %l2 = sext <4 x i32> %s0 to <4 x i64>268 %l5 = sext <4 x i32> %s1 to <4 x i64>269 %l6 = mul nsw <4 x i64> %l5, %l2270 %l7 = ashr <4 x i64> %l6, <i64 31, i64 31, i64 31, i64 31>271 %l8 = icmp slt <4 x i64> %l7, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>272 %l9 = select <4 x i1> %l8, <4 x i64> %l7, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>273 %l10 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %l9)274 ret i64 %l10275}276 277define arm_aapcs_vfpcc <4 x i32> @vqdmulh_v4i32_b(<4 x i32> %s0, <4 x i32> %s1) {278; CHECK-LABEL: vqdmulh_v4i32_b:279; CHECK: @ %bb.0: @ %entry280; CHECK-NEXT: vqdmulh.s32 q0, q1, q0281; CHECK-NEXT: bx lr282entry:283 %l2 = sext <4 x i32> %s0 to <4 x i64>284 %l5 = sext <4 x i32> %s1 to <4 x i64>285 %l6 = mul nsw <4 x i64> %l5, %l2286 %l7 = ashr <4 x i64> %l6, <i64 31, i64 31, i64 31, i64 31>287 %l8 = icmp slt <4 x i64> %l7, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>288 %l9 = select <4 x i1> %l8, <4 x i64> %l7, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>289 %l10 = trunc <4 x i64> %l9 to <4 x i32>290 ret <4 x i32> %l10291}292 293define arm_aapcs_vfpcc <2 x i32> @vqdmulh_v2i32_b(<2 x i32> %s0, <2 x i32> %s1) {294; CHECK-LABEL: vqdmulh_v2i32_b:295; CHECK: @ %bb.0: @ %entry296; CHECK-NEXT: vqdmulh.s32 q0, q1, q0297; CHECK-NEXT: vmov r0, s2298; CHECK-NEXT: vmov r1, s0299; CHECK-NEXT: vmov q0[2], q0[0], r1, r0300; CHECK-NEXT: asrs r0, r0, #31301; CHECK-NEXT: asrs r1, r1, #31302; CHECK-NEXT: vmov q0[3], q0[1], r1, r0303; CHECK-NEXT: bx lr304entry:305 %l2 = sext <2 x i32> %s0 to <2 x i64>306 %l5 = sext <2 x i32> %s1 to <2 x i64>307 %l6 = mul nsw <2 x i64> %l5, %l2308 %l7 = ashr <2 x i64> %l6, <i64 31, i64 31>309 %l8 = icmp slt <2 x i64> %l7, <i64 2147483647, i64 2147483647>310 %l9 = select <2 x i1> %l8, <2 x i64> %l7, <2 x i64> <i64 2147483647, i64 2147483647>311 %l10 = trunc <2 x i64> %l9 to <2 x i32>312 ret <2 x i32> %l10313}314 315define arm_aapcs_vfpcc <8 x i32> @vqdmulh_v8i32_b(<8 x i32> %s0, <8 x i32> %s1) {316; CHECK-LABEL: vqdmulh_v8i32_b:317; CHECK: @ %bb.0: @ %entry318; CHECK-NEXT: vqdmulh.s32 q0, q2, q0319; CHECK-NEXT: vqdmulh.s32 q1, q3, q1320; CHECK-NEXT: bx lr321entry:322 %l2 = sext <8 x i32> %s0 to <8 x i64>323 %l5 = sext <8 x i32> %s1 to <8 x i64>324 %l6 = mul nsw <8 x i64> %l5, %l2325 %l7 = ashr <8 x i64> %l6, <i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31>326 %l8 = icmp slt <8 x i64> %l7, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>327 %l9 = select <8 x i1> %l8, <8 x i64> %l7, <8 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>328 %l10 = trunc <8 x i64> %l9 to <8 x i32>329 ret <8 x i32> %l10330}331 332define arm_aapcs_vfpcc <16 x i32> @vqdmulh_v16i32_b(<16 x i32> %s0, <16 x i32> %s1) {333; CHECK-LABEL: vqdmulh_v16i32_b:334; CHECK: @ %bb.0: @ %entry335; CHECK-NEXT: .vsave {d8, d9}336; CHECK-NEXT: vpush {d8, d9}337; CHECK-NEXT: add r0, sp, #16338; CHECK-NEXT: vldrw.u32 q4, [r0]339; CHECK-NEXT: add r0, sp, #32340; CHECK-NEXT: vqdmulh.s32 q0, q4, q0341; CHECK-NEXT: vldrw.u32 q4, [r0]342; CHECK-NEXT: add r0, sp, #48343; CHECK-NEXT: vqdmulh.s32 q1, q4, q1344; CHECK-NEXT: vldrw.u32 q4, [r0]345; CHECK-NEXT: add r0, sp, #64346; CHECK-NEXT: vqdmulh.s32 q2, q4, q2347; CHECK-NEXT: vldrw.u32 q4, [r0]348; CHECK-NEXT: vqdmulh.s32 q3, q4, q3349; CHECK-NEXT: vpop {d8, d9}350; CHECK-NEXT: bx lr351entry:352 %l2 = sext <16 x i32> %s0 to <16 x i64>353 %l5 = sext <16 x i32> %s1 to <16 x i64>354 %l6 = mul nsw <16 x i64> %l5, %l2355 %l7 = ashr <16 x i64> %l6, <i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31>356 %l8 = icmp slt <16 x i64> %l7, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>357 %l9 = select <16 x i1> %l8, <16 x i64> %l7, <16 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>358 %l10 = trunc <16 x i64> %l9 to <16 x i32>359 ret <16 x i32> %l10360}361 362 363 364define void @vqdmulh_loop_i8(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) local_unnamed_addr #0 {365; CHECK-LABEL: vqdmulh_loop_i8:366; CHECK: @ %bb.0: @ %entry367; CHECK-NEXT: .save {r7, lr}368; CHECK-NEXT: push {r7, lr}369; CHECK-NEXT: mov.w lr, #64370; CHECK-NEXT: .LBB17_1: @ %vector.body371; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1372; CHECK-NEXT: vldrb.u8 q0, [r0], #16373; CHECK-NEXT: vldrb.u8 q1, [r1], #16374; CHECK-NEXT: vqdmulh.s8 q0, q1, q0375; CHECK-NEXT: vstrb.8 q0, [r2], #16376; CHECK-NEXT: le lr, .LBB17_1377; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup378; CHECK-NEXT: pop {r7, pc}379entry:380 br label %vector.body381 382vector.body: ; preds = %vector.body, %entry383 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]384 %0 = getelementptr inbounds i8, ptr %x, i32 %index385 %wide.load = load <16 x i8>, ptr %0, align 1386 %1 = sext <16 x i8> %wide.load to <16 x i32>387 %2 = getelementptr inbounds i8, ptr %y, i32 %index388 %wide.load26 = load <16 x i8>, ptr %2, align 1389 %3 = sext <16 x i8> %wide.load26 to <16 x i32>390 %4 = mul nsw <16 x i32> %3, %1391 %5 = ashr <16 x i32> %4, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>392 %6 = icmp slt <16 x i32> %5, <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>393 %7 = select <16 x i1> %6, <16 x i32> %5, <16 x i32> <i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127, i32 127>394 %8 = trunc <16 x i32> %7 to <16 x i8>395 %9 = getelementptr inbounds i8, ptr %z, i32 %index396 store <16 x i8> %8, ptr %9, align 1397 %index.next = add i32 %index, 16398 %10 = icmp eq i32 %index.next, 1024399 br i1 %10, label %for.cond.cleanup, label %vector.body400 401for.cond.cleanup: ; preds = %vector.body402 ret void403}404 405define void @vqdmulh_loop_i16(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {406; CHECK-LABEL: vqdmulh_loop_i16:407; CHECK: @ %bb.0: @ %entry408; CHECK-NEXT: .save {r7, lr}409; CHECK-NEXT: push {r7, lr}410; CHECK-NEXT: mov.w lr, #128411; CHECK-NEXT: .LBB18_1: @ %vector.body412; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1413; CHECK-NEXT: vldrh.u16 q0, [r0], #16414; CHECK-NEXT: vldrh.u16 q1, [r1], #16415; CHECK-NEXT: vqdmulh.s16 q0, q1, q0416; CHECK-NEXT: vstrb.8 q0, [r2], #16417; CHECK-NEXT: le lr, .LBB18_1418; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup419; CHECK-NEXT: pop {r7, pc}420entry:421 br label %vector.body422 423vector.body: ; preds = %vector.body, %entry424 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]425 %0 = getelementptr inbounds i16, ptr %x, i32 %index426 %wide.load = load <8 x i16>, ptr %0, align 2427 %1 = sext <8 x i16> %wide.load to <8 x i32>428 %2 = getelementptr inbounds i16, ptr %y, i32 %index429 %wide.load30 = load <8 x i16>, ptr %2, align 2430 %3 = sext <8 x i16> %wide.load30 to <8 x i32>431 %4 = mul nsw <8 x i32> %3, %1432 %5 = ashr <8 x i32> %4, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>433 %6 = icmp slt <8 x i32> %5, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>434 %7 = select <8 x i1> %6, <8 x i32> %5, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>435 %8 = trunc <8 x i32> %7 to <8 x i16>436 %9 = getelementptr inbounds i16, ptr %z, i32 %index437 store <8 x i16> %8, ptr %9, align 2438 %index.next = add i32 %index, 8439 %10 = icmp eq i32 %index.next, 1024440 br i1 %10, label %for.cond.cleanup, label %vector.body441 442for.cond.cleanup: ; preds = %vector.body443 ret void444}445 446define void @vqdmulh_loop_i32(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {447; CHECK-LABEL: vqdmulh_loop_i32:448; CHECK: @ %bb.0: @ %entry449; CHECK-NEXT: .save {r7, lr}450; CHECK-NEXT: push {r7, lr}451; CHECK-NEXT: mov.w lr, #256452; CHECK-NEXT: .LBB19_1: @ %vector.body453; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1454; CHECK-NEXT: vldrw.u32 q0, [r0], #16455; CHECK-NEXT: vldrw.u32 q1, [r1], #16456; CHECK-NEXT: vqdmulh.s32 q0, q1, q0457; CHECK-NEXT: vstrb.8 q0, [r2], #16458; CHECK-NEXT: le lr, .LBB19_1459; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup460; CHECK-NEXT: pop {r7, pc}461entry:462 br label %vector.body463 464vector.body: ; preds = %vector.body, %entry465 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]466 %0 = getelementptr inbounds i32, ptr %x, i32 %index467 %wide.load = load <4 x i32>, ptr %0, align 4468 %1 = sext <4 x i32> %wide.load to <4 x i64>469 %2 = getelementptr inbounds i32, ptr %y, i32 %index470 %wide.load30 = load <4 x i32>, ptr %2, align 4471 %3 = sext <4 x i32> %wide.load30 to <4 x i64>472 %4 = mul nsw <4 x i64> %3, %1473 %5 = ashr <4 x i64> %4, <i64 31, i64 31, i64 31, i64 31>474 %6 = icmp slt <4 x i64> %5, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>475 %7 = select <4 x i1> %6, <4 x i64> %5, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>476 %8 = trunc <4 x i64> %7 to <4 x i32>477 %9 = getelementptr inbounds i32, ptr %z, i32 %index478 store <4 x i32> %8, ptr %9, align 4479 %index.next = add i32 %index, 4480 %10 = icmp eq i32 %index.next, 1024481 br i1 %10, label %for.cond.cleanup, label %vector.body482 483for.cond.cleanup: ; preds = %vector.body484 ret void485}486 487define <2 x i64> @large_i128(<2 x double> %x) {488; CHECK-LABEL: large_i128:489; CHECK: @ %bb.0: @ %entry490; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}491; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}492; CHECK-NEXT: .pad #4493; CHECK-NEXT: sub sp, #4494; CHECK-NEXT: mov r8, r3495; CHECK-NEXT: mov r5, r2496; CHECK-NEXT: bl __fixdfti497; CHECK-NEXT: subs r7, r2, #1498; CHECK-NEXT: mov.w r9, #1499; CHECK-NEXT: sbcs r7, r3, #0500; CHECK-NEXT: mov.w r4, #0501; CHECK-NEXT: cset r7, lt502; CHECK-NEXT: cmp r7, #0503; CHECK-NEXT: csel r0, r0, r7, ne504; CHECK-NEXT: csel r3, r3, r7, ne505; CHECK-NEXT: csel r1, r1, r7, ne506; CHECK-NEXT: csel r2, r2, r9, ne507; CHECK-NEXT: rsbs r7, r0, #0508; CHECK-NEXT: sbcs.w r7, r4, r1509; CHECK-NEXT: sbcs.w r2, r4, r2510; CHECK-NEXT: sbcs.w r2, r4, r3511; CHECK-NEXT: cset r2, lt512; CHECK-NEXT: cmp r2, #0513; CHECK-NEXT: csel r6, r0, r2, ne514; CHECK-NEXT: csel r7, r1, r2, ne515; CHECK-NEXT: mov r0, r5516; CHECK-NEXT: mov r1, r8517; CHECK-NEXT: bl __fixdfti518; CHECK-NEXT: subs r5, r2, #1519; CHECK-NEXT: sbcs r5, r3, #0520; CHECK-NEXT: cset r5, lt521; CHECK-NEXT: cmp r5, #0522; CHECK-NEXT: csel r0, r0, r5, ne523; CHECK-NEXT: csel r3, r3, r5, ne524; CHECK-NEXT: csel r1, r1, r5, ne525; CHECK-NEXT: csel r2, r2, r9, ne526; CHECK-NEXT: rsbs r5, r0, #0527; CHECK-NEXT: sbcs.w r5, r4, r1528; CHECK-NEXT: sbcs.w r2, r4, r2529; CHECK-NEXT: sbcs.w r2, r4, r3530; CHECK-NEXT: cset r3, lt531; CHECK-NEXT: cmp r3, #0532; CHECK-NEXT: csel r2, r0, r3, ne533; CHECK-NEXT: csel r3, r1, r3, ne534; CHECK-NEXT: mov r0, r6535; CHECK-NEXT: mov r1, r7536; CHECK-NEXT: add sp, #4537; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}538entry:539 %conv = fptosi <2 x double> %x to <2 x i128>540 %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>541 %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>542 %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer543 %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer544 %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>545 ret <2 x i64> %conv6546}547 548declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)549declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)550declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)551