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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <8 x i16> @vqmovni32_sminmax_t1(<4 x i32> %s0, <8 x i16> %src1) {5; CHECK-LABEL: vqmovni32_sminmax_t1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqmovnt.s32 q1, q08; CHECK-NEXT: vmov q0, q19; CHECK-NEXT: bx lr10entry:11 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>12 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>13 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>14 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>15 %src2 = bitcast <4 x i32> %s2 to <8 x i16>16 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>17 ret <8 x i16> %out18}19 20define arm_aapcs_vfpcc <8 x i16> @vqmovni32_sminmax_t2(<4 x i32> %s0, <8 x i16> %src1) {21; CHECK-LABEL: vqmovni32_sminmax_t2:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: vqmovnb.s32 q0, q024; CHECK-NEXT: vmovnt.i32 q0, q125; CHECK-NEXT: bx lr26entry:27 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>28 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>29 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>30 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>31 %src2 = bitcast <4 x i32> %s2 to <8 x i16>32 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>33 ret <8 x i16> %out34}35 36define arm_aapcs_vfpcc <8 x i16> @vqmovni32_sminmax_b1(<4 x i32> %s0, <8 x i16> %src1) {37; CHECK-LABEL: vqmovni32_sminmax_b1:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: vqmovnb.s32 q1, q040; CHECK-NEXT: vmov q0, q141; CHECK-NEXT: bx lr42entry:43 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>44 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>45 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>46 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>47 %src2 = bitcast <4 x i32> %s2 to <8 x i16>48 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>49 ret <8 x i16> %out50}51 52define arm_aapcs_vfpcc <8 x i16> @vqmovni32_sminmax_b2(<4 x i32> %s0, <8 x i16> %src1) {53; CHECK-LABEL: vqmovni32_sminmax_b2:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: vqmovnb.s32 q0, q056; CHECK-NEXT: vmovlb.s16 q0, q057; CHECK-NEXT: vmovnb.i32 q0, q158; CHECK-NEXT: bx lr59entry:60 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>61 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>62 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>63 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>64 %src2 = bitcast <4 x i32> %s2 to <8 x i16>65 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>66 ret <8 x i16> %out67}68 69 70define arm_aapcs_vfpcc <8 x i16> @vqmovni32_uminmax_t1(<4 x i32> %s0, <8 x i16> %src1) {71; CHECK-LABEL: vqmovni32_uminmax_t1:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: vqmovnb.u32 q0, q074; CHECK-NEXT: vmovlb.u16 q0, q075; CHECK-NEXT: vmovnt.i32 q1, q076; CHECK-NEXT: vmov q0, q177; CHECK-NEXT: bx lr78entry:79 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>80 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>81 %src2 = bitcast <4 x i32> %s2 to <8 x i16>82 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>83 ret <8 x i16> %out84}85 86define arm_aapcs_vfpcc <8 x i16> @vqmovni32_uminmax_t2(<4 x i32> %s0, <8 x i16> %src1) {87; CHECK-LABEL: vqmovni32_uminmax_t2:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: vqmovnb.u32 q0, q090; CHECK-NEXT: vmovlb.u16 q0, q091; CHECK-NEXT: vmovnt.i32 q0, q192; CHECK-NEXT: bx lr93entry:94 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>95 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>96 %src2 = bitcast <4 x i32> %s2 to <8 x i16>97 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>98 ret <8 x i16> %out99}100 101define arm_aapcs_vfpcc <8 x i16> @vqmovni32_uminmax_b1(<4 x i32> %s0, <8 x i16> %src1) {102; CHECK-LABEL: vqmovni32_uminmax_b1:103; CHECK: @ %bb.0: @ %entry104; CHECK-NEXT: vqmovnb.u32 q0, q0105; CHECK-NEXT: vmovlb.u16 q0, q0106; CHECK-NEXT: vmovnb.i32 q1, q0107; CHECK-NEXT: vmov q0, q1108; CHECK-NEXT: bx lr109entry:110 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>111 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>112 %src2 = bitcast <4 x i32> %s2 to <8 x i16>113 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>114 ret <8 x i16> %out115}116 117define arm_aapcs_vfpcc <8 x i16> @vqmovni32_uminmax_b2(<4 x i32> %s0, <8 x i16> %src1) {118; CHECK-LABEL: vqmovni32_uminmax_b2:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vmov.i32 q0, #0x0121; CHECK-NEXT: vmovnb.i32 q0, q1122; CHECK-NEXT: bx lr123entry:124 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>125 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>126 %src2 = bitcast <4 x i32> %s2 to <8 x i16>127 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>128 ret <8 x i16> %out129}130 131 132define arm_aapcs_vfpcc <16 x i8> @vqmovni16_sminmax_t1(<8 x i16> %s0, <16 x i8> %src1) {133; CHECK-LABEL: vqmovni16_sminmax_t1:134; CHECK: @ %bb.0: @ %entry135; CHECK-NEXT: vqmovnt.s16 q1, q0136; CHECK-NEXT: vmov q0, q1137; CHECK-NEXT: bx lr138entry:139 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>140 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>141 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>142 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>143 %src2 = bitcast <8 x i16> %s2 to <16 x i8>144 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>145 ret <16 x i8> %out146}147 148define arm_aapcs_vfpcc <16 x i8> @vqmovni16_sminmax_t2(<8 x i16> %s0, <16 x i8> %src1) {149; CHECK-LABEL: vqmovni16_sminmax_t2:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vqmovnb.s16 q0, q0152; CHECK-NEXT: vmovnt.i16 q0, q1153; CHECK-NEXT: bx lr154entry:155 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>156 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>157 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>158 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>159 %src2 = bitcast <8 x i16> %s2 to <16 x i8>160 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>161 ret <16 x i8> %out162}163 164define arm_aapcs_vfpcc <16 x i8> @vqmovni16_sminmax_b1(<8 x i16> %s0, <16 x i8> %src1) {165; CHECK-LABEL: vqmovni16_sminmax_b1:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vqmovnb.s16 q1, q0168; CHECK-NEXT: vmov q0, q1169; CHECK-NEXT: bx lr170entry:171 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>172 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>173 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>174 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>175 %src2 = bitcast <8 x i16> %s2 to <16 x i8>176 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>177 ret <16 x i8> %out178}179 180define arm_aapcs_vfpcc <16 x i8> @vqmovni16_sminmax_b2(<8 x i16> %s0, <16 x i8> %src1) {181; CHECK-LABEL: vqmovni16_sminmax_b2:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: vqmovnb.s16 q0, q0184; CHECK-NEXT: vmovlb.s8 q0, q0185; CHECK-NEXT: vmovnb.i16 q0, q1186; CHECK-NEXT: bx lr187entry:188 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>189 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>190 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>191 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>192 %src2 = bitcast <8 x i16> %s2 to <16 x i8>193 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>194 ret <16 x i8> %out195}196 197 198define arm_aapcs_vfpcc <16 x i8> @vqmovni16_uminmax_t1(<8 x i16> %s0, <16 x i8> %src1) {199; CHECK-LABEL: vqmovni16_uminmax_t1:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: vqmovnt.u16 q1, q0202; CHECK-NEXT: vmov q0, q1203; CHECK-NEXT: bx lr204entry:205 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>206 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>207 %src2 = bitcast <8 x i16> %s2 to <16 x i8>208 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>209 ret <16 x i8> %out210}211 212define arm_aapcs_vfpcc <16 x i8> @vqmovni16_uminmax_t2(<8 x i16> %s0, <16 x i8> %src1) {213; CHECK-LABEL: vqmovni16_uminmax_t2:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vqmovnb.u16 q0, q0216; CHECK-NEXT: vmovnt.i16 q0, q1217; CHECK-NEXT: bx lr218entry:219 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>220 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>221 %src2 = bitcast <8 x i16> %s2 to <16 x i8>222 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>223 ret <16 x i8> %out224}225 226define arm_aapcs_vfpcc <16 x i8> @vqmovni16_uminmax_b1(<8 x i16> %s0, <16 x i8> %src1) {227; CHECK-LABEL: vqmovni16_uminmax_b1:228; CHECK: @ %bb.0: @ %entry229; CHECK-NEXT: vqmovnb.u16 q1, q0230; CHECK-NEXT: vmov q0, q1231; CHECK-NEXT: bx lr232entry:233 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>234 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>235 %src2 = bitcast <8 x i16> %s2 to <16 x i8>236 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>237 ret <16 x i8> %out238}239 240define arm_aapcs_vfpcc <16 x i8> @vqmovni16_uminmax_b2(<8 x i16> %s0, <16 x i8> %src1) {241; CHECK-LABEL: vqmovni16_uminmax_b2:242; CHECK: @ %bb.0: @ %entry243; CHECK-NEXT: vmov.i32 q0, #0x0244; CHECK-NEXT: vmovnb.i16 q0, q1245; CHECK-NEXT: bx lr246entry:247 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>248 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>249 %src2 = bitcast <8 x i16> %s2 to <16 x i8>250 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>251 ret <16 x i8> %out252}253