323 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vqmovni32_smaxmin(<4 x i32> %s0) {5; CHECK-LABEL: vqmovni32_smaxmin:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqmovnb.s32 q0, q08; CHECK-NEXT: vmovlb.s16 q0, q09; CHECK-NEXT: bx lr10entry:11 %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>12 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>13 %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>14 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>15 ret <4 x i32> %s216}17 18define arm_aapcs_vfpcc <4 x i32> @vqmovni32_sminmax(<4 x i32> %s0) {19; CHECK-LABEL: vqmovni32_sminmax:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vqmovnb.s32 q0, q022; CHECK-NEXT: vmovlb.s16 q0, q023; CHECK-NEXT: bx lr24entry:25 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>26 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>27 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>28 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>29 ret <4 x i32> %s230}31 32define arm_aapcs_vfpcc <4 x i32> @vqmovni32_umaxmin(<4 x i32> %s0) {33; CHECK-LABEL: vqmovni32_umaxmin:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vqmovnb.u32 q0, q036; CHECK-NEXT: vmovlb.u16 q0, q037; CHECK-NEXT: bx lr38entry:39 %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>40 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>41 ret <4 x i32> %s142}43 44define arm_aapcs_vfpcc <4 x i32> @vqmovni32_uminmax(<4 x i32> %s0) {45; CHECK-LABEL: vqmovni32_uminmax:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vqmovnb.u32 q0, q048; CHECK-NEXT: vmovlb.u16 q0, q049; CHECK-NEXT: bx lr50entry:51 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>52 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>53 ret <4 x i32> %s254}55 56define arm_aapcs_vfpcc <8 x i16> @vqmovni16_smaxmin(<8 x i16> %s0) {57; CHECK-LABEL: vqmovni16_smaxmin:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: vqmovnb.s16 q0, q060; CHECK-NEXT: vmovlb.s8 q0, q061; CHECK-NEXT: bx lr62entry:63 %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>64 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>65 %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>66 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>67 ret <8 x i16> %s268}69 70define arm_aapcs_vfpcc <8 x i16> @vqmovni16_sminmax(<8 x i16> %s0) {71; CHECK-LABEL: vqmovni16_sminmax:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: vqmovnb.s16 q0, q074; CHECK-NEXT: vmovlb.s8 q0, q075; CHECK-NEXT: bx lr76entry:77 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>78 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>79 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>80 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>81 ret <8 x i16> %s282}83 84define arm_aapcs_vfpcc <8 x i16> @vqmovni16_umaxmin(<8 x i16> %s0) {85; CHECK-LABEL: vqmovni16_umaxmin:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vqmovnb.u16 q0, q088; CHECK-NEXT: vmovlb.u8 q0, q089; CHECK-NEXT: bx lr90entry:91 %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>92 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>93 ret <8 x i16> %s194}95 96define arm_aapcs_vfpcc <8 x i16> @vqmovni16_uminmax(<8 x i16> %s0) {97; CHECK-LABEL: vqmovni16_uminmax:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: vqmovnb.u16 q0, q0100; CHECK-NEXT: vmovlb.u8 q0, q0101; CHECK-NEXT: bx lr102entry:103 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>104 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>105 ret <8 x i16> %s2106}107 108define arm_aapcs_vfpcc <16 x i8> @vqmovni8_smaxmin(<16 x i8> %s0) {109; CHECK-LABEL: vqmovni8_smaxmin:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vmov.i8 q1, #0x7112; CHECK-NEXT: vmin.s8 q0, q0, q1113; CHECK-NEXT: vmov.i8 q1, #0xf8114; CHECK-NEXT: vmax.s8 q0, q0, q1115; CHECK-NEXT: bx lr116entry:117 %c1 = icmp slt <16 x i8> %s0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>118 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>119 %c2 = icmp sgt <16 x i8> %s1, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>120 %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>121 ret <16 x i8> %s2122}123 124define arm_aapcs_vfpcc <16 x i8> @vqmovni8_sminmax(<16 x i8> %s0) {125; CHECK-LABEL: vqmovni8_sminmax:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vmov.i8 q1, #0xf8128; CHECK-NEXT: vmax.s8 q0, q0, q1129; CHECK-NEXT: vmov.i8 q1, #0x7130; CHECK-NEXT: vmin.s8 q0, q0, q1131; CHECK-NEXT: bx lr132entry:133 %c1 = icmp sgt <16 x i8> %s0, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>134 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>135 %c2 = icmp slt <16 x i8> %s1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>136 %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>137 ret <16 x i8> %s2138}139 140define arm_aapcs_vfpcc <16 x i8> @vqmovni8_umaxmin(<16 x i8> %s0) {141; CHECK-LABEL: vqmovni8_umaxmin:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vmov.i8 q1, #0xf144; CHECK-NEXT: vmin.u8 q0, q0, q1145; CHECK-NEXT: bx lr146entry:147 %c1 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>148 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>149 ret <16 x i8> %s1150}151 152define arm_aapcs_vfpcc <16 x i8> @vqmovni8_uminmax(<16 x i8> %s0) {153; CHECK-LABEL: vqmovni8_uminmax:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vmov.i8 q1, #0xf156; CHECK-NEXT: vmin.u8 q0, q0, q1157; CHECK-NEXT: bx lr158entry:159 %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>160 %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>161 ret <16 x i8> %s2162}163 164define arm_aapcs_vfpcc <2 x i64> @vqmovni64_smaxmin(<2 x i64> %s0) {165; CHECK-LABEL: vqmovni64_smaxmin:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vmov r0, r1, d0168; CHECK-NEXT: mvn r12, #-2147483648169; CHECK-NEXT: movs r3, #0170; CHECK-NEXT: subs.w r0, r0, r12171; CHECK-NEXT: sbcs r0, r1, #0172; CHECK-NEXT: csetm r1, lt173; CHECK-NEXT: movs r0, #0174; CHECK-NEXT: bfi r3, r1, #0, #8175; CHECK-NEXT: vmov r1, r2, d1176; CHECK-NEXT: subs.w r1, r1, r12177; CHECK-NEXT: sbcs r1, r2, #0178; CHECK-NEXT: csetm r1, lt179; CHECK-NEXT: bfi r3, r1, #8, #8180; CHECK-NEXT: adr r1, .LCPI12_0181; CHECK-NEXT: vldrw.u32 q1, [r1]182; CHECK-NEXT: vmsr p0, r3183; CHECK-NEXT: mov.w r3, #-1184; CHECK-NEXT: vpsel q0, q0, q1185; CHECK-NEXT: vmov r1, r2, d0186; CHECK-NEXT: rsbs.w r1, r1, #-2147483648187; CHECK-NEXT: sbcs.w r1, r3, r2188; CHECK-NEXT: csetm r1, lt189; CHECK-NEXT: bfi r0, r1, #0, #8190; CHECK-NEXT: vmov r1, r2, d1191; CHECK-NEXT: rsbs.w r1, r1, #-2147483648192; CHECK-NEXT: sbcs.w r1, r3, r2193; CHECK-NEXT: csetm r1, lt194; CHECK-NEXT: bfi r0, r1, #8, #8195; CHECK-NEXT: vmsr p0, r0196; CHECK-NEXT: adr r0, .LCPI12_1197; CHECK-NEXT: vldrw.u32 q1, [r0]198; CHECK-NEXT: vpsel q0, q0, q1199; CHECK-NEXT: bx lr200; CHECK-NEXT: .p2align 4201; CHECK-NEXT: @ %bb.1:202; CHECK-NEXT: .LCPI12_0:203; CHECK-NEXT: .long 2147483647 @ 0x7fffffff204; CHECK-NEXT: .long 0 @ 0x0205; CHECK-NEXT: .long 2147483647 @ 0x7fffffff206; CHECK-NEXT: .long 0 @ 0x0207; CHECK-NEXT: .LCPI12_1:208; CHECK-NEXT: .long 2147483648 @ 0x80000000209; CHECK-NEXT: .long 4294967295 @ 0xffffffff210; CHECK-NEXT: .long 2147483648 @ 0x80000000211; CHECK-NEXT: .long 4294967295 @ 0xffffffff212entry:213 %c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>214 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>215 %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>216 %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>217 ret <2 x i64> %s2218}219 220define arm_aapcs_vfpcc <2 x i64> @vqmovni64_sminmax(<2 x i64> %s0) {221; CHECK-LABEL: vqmovni64_sminmax:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmov r0, r1, d0224; CHECK-NEXT: mov.w r12, #-1225; CHECK-NEXT: movs r3, #0226; CHECK-NEXT: rsbs.w r0, r0, #-2147483648227; CHECK-NEXT: sbcs.w r0, r12, r1228; CHECK-NEXT: csetm r1, lt229; CHECK-NEXT: movs r0, #0230; CHECK-NEXT: bfi r3, r1, #0, #8231; CHECK-NEXT: vmov r1, r2, d1232; CHECK-NEXT: rsbs.w r1, r1, #-2147483648233; CHECK-NEXT: sbcs.w r1, r12, r2234; CHECK-NEXT: csetm r1, lt235; CHECK-NEXT: bfi r3, r1, #8, #8236; CHECK-NEXT: adr r1, .LCPI13_0237; CHECK-NEXT: vldrw.u32 q1, [r1]238; CHECK-NEXT: vmsr p0, r3239; CHECK-NEXT: mvn r3, #-2147483648240; CHECK-NEXT: vpsel q0, q0, q1241; CHECK-NEXT: vmov r1, r2, d0242; CHECK-NEXT: subs r1, r1, r3243; CHECK-NEXT: sbcs r1, r2, #0244; CHECK-NEXT: csetm r1, lt245; CHECK-NEXT: bfi r0, r1, #0, #8246; CHECK-NEXT: vmov r1, r2, d1247; CHECK-NEXT: subs r1, r1, r3248; CHECK-NEXT: sbcs r1, r2, #0249; CHECK-NEXT: csetm r1, lt250; CHECK-NEXT: bfi r0, r1, #8, #8251; CHECK-NEXT: vmsr p0, r0252; CHECK-NEXT: adr r0, .LCPI13_1253; CHECK-NEXT: vldrw.u32 q1, [r0]254; CHECK-NEXT: vpsel q0, q0, q1255; CHECK-NEXT: bx lr256; CHECK-NEXT: .p2align 4257; CHECK-NEXT: @ %bb.1:258; CHECK-NEXT: .LCPI13_0:259; CHECK-NEXT: .long 2147483648 @ 0x80000000260; CHECK-NEXT: .long 4294967295 @ 0xffffffff261; CHECK-NEXT: .long 2147483648 @ 0x80000000262; CHECK-NEXT: .long 4294967295 @ 0xffffffff263; CHECK-NEXT: .LCPI13_1:264; CHECK-NEXT: .long 2147483647 @ 0x7fffffff265; CHECK-NEXT: .long 0 @ 0x0266; CHECK-NEXT: .long 2147483647 @ 0x7fffffff267; CHECK-NEXT: .long 0 @ 0x0268entry:269 %c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>270 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>271 %c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647>272 %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>273 ret <2 x i64> %s2274}275 276define arm_aapcs_vfpcc <2 x i64> @vqmovni64_umaxmin(<2 x i64> %s0) {277; CHECK-LABEL: vqmovni64_umaxmin:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vmov r0, r1, d0280; CHECK-NEXT: vmov.i64 q1, #0xffffffff281; CHECK-NEXT: subs.w r0, r0, #-1282; CHECK-NEXT: sbcs r0, r1, #0283; CHECK-NEXT: mov.w r1, #0284; CHECK-NEXT: csetm r0, lo285; CHECK-NEXT: bfi r1, r0, #0, #8286; CHECK-NEXT: vmov r0, r2, d1287; CHECK-NEXT: subs.w r0, r0, #-1288; CHECK-NEXT: sbcs r0, r2, #0289; CHECK-NEXT: csetm r0, lo290; CHECK-NEXT: bfi r1, r0, #8, #8291; CHECK-NEXT: vmsr p0, r1292; CHECK-NEXT: vpsel q0, q0, q1293; CHECK-NEXT: bx lr294entry:295 %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>296 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>297 ret <2 x i64> %s1298}299 300define arm_aapcs_vfpcc <2 x i64> @vqmovni64_uminmax(<2 x i64> %s0) {301; CHECK-LABEL: vqmovni64_uminmax:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: vmov r0, r1, d0304; CHECK-NEXT: vmov.i64 q1, #0xffffffff305; CHECK-NEXT: subs.w r0, r0, #-1306; CHECK-NEXT: sbcs r0, r1, #0307; CHECK-NEXT: mov.w r1, #0308; CHECK-NEXT: csetm r0, lo309; CHECK-NEXT: bfi r1, r0, #0, #8310; CHECK-NEXT: vmov r0, r2, d1311; CHECK-NEXT: subs.w r0, r0, #-1312; CHECK-NEXT: sbcs r0, r2, #0313; CHECK-NEXT: csetm r0, lo314; CHECK-NEXT: bfi r1, r0, #8, #8315; CHECK-NEXT: vmsr p0, r1316; CHECK-NEXT: vpsel q0, q0, q1317; CHECK-NEXT: bx lr318entry:319 %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>320 %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>321 ret <2 x i64> %s2322}323