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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vqshrni32_smaxmin(<4 x i32> %so) {5; CHECK-LABEL: vqshrni32_smaxmin:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqshrnb.s32 q0, q0, #38; CHECK-NEXT: vmovlb.s16 q0, q09; CHECK-NEXT: bx lr10entry:11 %s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>12 %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>13 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>14 %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>15 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>16 ret <4 x i32> %s217}18 19define arm_aapcs_vfpcc <4 x i32> @vqshrni32_sminmax(<4 x i32> %so) {20; CHECK-LABEL: vqshrni32_sminmax:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vqshrnb.s32 q0, q0, #323; CHECK-NEXT: vmovlb.s16 q0, q024; CHECK-NEXT: bx lr25entry:26 %s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>27 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>28 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>29 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>30 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>31 ret <4 x i32> %s232}33 34define arm_aapcs_vfpcc <4 x i32> @vqshrni32_umaxmin(<4 x i32> %so) {35; CHECK-LABEL: vqshrni32_umaxmin:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vqshrnb.u32 q0, q0, #338; CHECK-NEXT: vmovlb.u16 q0, q039; CHECK-NEXT: bx lr40entry:41 %s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>42 %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>43 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>44 ret <4 x i32> %s145}46 47define arm_aapcs_vfpcc <4 x i32> @vqshrni32_uminmax(<4 x i32> %so) {48; CHECK-LABEL: vqshrni32_uminmax:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: vqshrnb.u32 q0, q0, #351; CHECK-NEXT: vmovlb.u16 q0, q052; CHECK-NEXT: bx lr53entry:54 %s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>55 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>56 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>57 ret <4 x i32> %s258}59 60define arm_aapcs_vfpcc <8 x i16> @vqshrni16_smaxmin(<8 x i16> %so) {61; CHECK-LABEL: vqshrni16_smaxmin:62; CHECK: @ %bb.0: @ %entry63; CHECK-NEXT: vqshrnb.s16 q0, q0, #364; CHECK-NEXT: vmovlb.s8 q0, q065; CHECK-NEXT: bx lr66entry:67 %s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>68 %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>69 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>70 %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>71 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>72 ret <8 x i16> %s273}74 75define arm_aapcs_vfpcc <8 x i16> @vqshrni16_sminmax(<8 x i16> %so) {76; CHECK-LABEL: vqshrni16_sminmax:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vqshrnb.s16 q0, q0, #379; CHECK-NEXT: vmovlb.s8 q0, q080; CHECK-NEXT: bx lr81entry:82 %s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>83 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>84 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>85 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>86 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>87 ret <8 x i16> %s288}89 90define arm_aapcs_vfpcc <8 x i16> @vqshrni16_umaxmin(<8 x i16> %so) {91; CHECK-LABEL: vqshrni16_umaxmin:92; CHECK: @ %bb.0: @ %entry93; CHECK-NEXT: vqshrnb.u16 q0, q0, #394; CHECK-NEXT: vmovlb.u8 q0, q095; CHECK-NEXT: bx lr96entry:97 %s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>98 %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>99 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>100 ret <8 x i16> %s1101}102 103define arm_aapcs_vfpcc <8 x i16> @vqshrni16_uminmax(<8 x i16> %so) {104; CHECK-LABEL: vqshrni16_uminmax:105; CHECK: @ %bb.0: @ %entry106; CHECK-NEXT: vqshrnb.u16 q0, q0, #3107; CHECK-NEXT: vmovlb.u8 q0, q0108; CHECK-NEXT: bx lr109entry:110 %s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>111 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>112 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>113 ret <8 x i16> %s2114}115 116define arm_aapcs_vfpcc <16 x i8> @vqshrni8_smaxmin(<16 x i8> %so) {117; CHECK-LABEL: vqshrni8_smaxmin:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: vshr.s8 q0, q0, #3120; CHECK-NEXT: vmov.i8 q1, #0x7121; CHECK-NEXT: vmin.s8 q0, q0, q1122; CHECK-NEXT: vmov.i8 q1, #0xf8123; CHECK-NEXT: vmax.s8 q0, q0, q1124; CHECK-NEXT: bx lr125entry:126 %s0 = ashr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>127 %c1 = icmp slt <16 x i8> %s0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>128 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>129 %c2 = icmp sgt <16 x i8> %s1, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>130 %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>131 ret <16 x i8> %s2132}133 134define arm_aapcs_vfpcc <16 x i8> @vqshrni8_sminmax(<16 x i8> %so) {135; CHECK-LABEL: vqshrni8_sminmax:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vshr.s8 q0, q0, #3138; CHECK-NEXT: vmov.i8 q1, #0xf8139; CHECK-NEXT: vmax.s8 q0, q0, q1140; CHECK-NEXT: vmov.i8 q1, #0x7141; CHECK-NEXT: vmin.s8 q0, q0, q1142; CHECK-NEXT: bx lr143entry:144 %s0 = ashr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>145 %c1 = icmp sgt <16 x i8> %s0, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>146 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>147 %c2 = icmp slt <16 x i8> %s1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>148 %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>149 ret <16 x i8> %s2150}151 152define arm_aapcs_vfpcc <16 x i8> @vqshrni8_umaxmin(<16 x i8> %so) {153; CHECK-LABEL: vqshrni8_umaxmin:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vshr.u8 q0, q0, #3156; CHECK-NEXT: vmov.i8 q1, #0xf157; CHECK-NEXT: vmin.u8 q0, q0, q1158; CHECK-NEXT: bx lr159entry:160 %s0 = lshr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>161 %c1 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>162 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>163 ret <16 x i8> %s1164}165 166define arm_aapcs_vfpcc <16 x i8> @vqshrni8_uminmax(<16 x i8> %so) {167; CHECK-LABEL: vqshrni8_uminmax:168; CHECK: @ %bb.0: @ %entry169; CHECK-NEXT: vshr.u8 q0, q0, #3170; CHECK-NEXT: vmov.i8 q1, #0xf171; CHECK-NEXT: vmin.u8 q0, q0, q1172; CHECK-NEXT: bx lr173entry:174 %s0 = lshr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>175 %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>176 %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>177 ret <16 x i8> %s2178}179 180define arm_aapcs_vfpcc <2 x i64> @vqshrni64_smaxmin(<2 x i64> %so) {181; CHECK-LABEL: vqshrni64_smaxmin:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: .save {r7, lr}184; CHECK-NEXT: push {r7, lr}185; CHECK-NEXT: vmov r0, r1, d1186; CHECK-NEXT: mvn r12, #-2147483648187; CHECK-NEXT: vmov r2, r3, d0188; CHECK-NEXT: asrl r0, r1, #3189; CHECK-NEXT: asrl r2, r3, #3190; CHECK-NEXT: vmov q0[2], q0[0], r2, r0191; CHECK-NEXT: subs.w r2, r2, r12192; CHECK-NEXT: sbcs r2, r3, #0193; CHECK-NEXT: vmov q0[3], q0[1], r3, r1194; CHECK-NEXT: csetm lr, lt195; CHECK-NEXT: subs.w r0, r0, r12196; CHECK-NEXT: mov.w r2, #0197; CHECK-NEXT: sbcs r0, r1, #0198; CHECK-NEXT: bfi r2, lr, #0, #8199; CHECK-NEXT: csetm r0, lt200; CHECK-NEXT: bfi r2, r0, #8, #8201; CHECK-NEXT: adr r0, .LCPI12_0202; CHECK-NEXT: vldrw.u32 q1, [r0]203; CHECK-NEXT: vmsr p0, r2204; CHECK-NEXT: mov.w r2, #-1205; CHECK-NEXT: movs r3, #0206; CHECK-NEXT: vpsel q0, q0, q1207; CHECK-NEXT: vmov r0, r1, d0208; CHECK-NEXT: rsbs.w r0, r0, #-2147483648209; CHECK-NEXT: sbcs.w r0, r2, r1210; CHECK-NEXT: csetm r0, lt211; CHECK-NEXT: bfi r3, r0, #0, #8212; CHECK-NEXT: vmov r0, r1, d1213; CHECK-NEXT: rsbs.w r0, r0, #-2147483648214; CHECK-NEXT: sbcs.w r0, r2, r1215; CHECK-NEXT: csetm r0, lt216; CHECK-NEXT: bfi r3, r0, #8, #8217; CHECK-NEXT: adr r0, .LCPI12_1218; CHECK-NEXT: vldrw.u32 q1, [r0]219; CHECK-NEXT: vmsr p0, r3220; CHECK-NEXT: vpsel q0, q0, q1221; CHECK-NEXT: pop {r7, pc}222; CHECK-NEXT: .p2align 4223; CHECK-NEXT: @ %bb.1:224; CHECK-NEXT: .LCPI12_0:225; CHECK-NEXT: .long 2147483647 @ 0x7fffffff226; CHECK-NEXT: .long 0 @ 0x0227; CHECK-NEXT: .long 2147483647 @ 0x7fffffff228; CHECK-NEXT: .long 0 @ 0x0229; CHECK-NEXT: .LCPI12_1:230; CHECK-NEXT: .long 2147483648 @ 0x80000000231; CHECK-NEXT: .long 4294967295 @ 0xffffffff232; CHECK-NEXT: .long 2147483648 @ 0x80000000233; CHECK-NEXT: .long 4294967295 @ 0xffffffff234entry:235 %s0 = ashr <2 x i64> %so, <i64 3, i64 3>236 %c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>237 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>238 %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>239 %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>240 ret <2 x i64> %s2241}242 243define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) {244; CHECK-LABEL: vqshrni64_sminmax:245; CHECK: @ %bb.0: @ %entry246; CHECK-NEXT: .save {r4, r5, r6, lr}247; CHECK-NEXT: push {r4, r5, r6, lr}248; CHECK-NEXT: vmov r2, r1, d0249; CHECK-NEXT: mov.w r12, #-1250; CHECK-NEXT: asrl r2, r1, #3251; CHECK-NEXT: vmov r4, r5, d1252; CHECK-NEXT: rsbs.w r0, r2, #-2147483648253; CHECK-NEXT: asrl r4, r5, #3254; CHECK-NEXT: sbcs.w r0, r12, r1255; CHECK-NEXT: mov.w r3, #0256; CHECK-NEXT: csetm lr, lt257; CHECK-NEXT: rsbs.w r0, r4, #-2147483648258; CHECK-NEXT: sbcs.w r0, r12, r5259; CHECK-NEXT: bfi r3, lr, #0, #8260; CHECK-NEXT: csetm r0, lt261; CHECK-NEXT: vmov q0[2], q0[0], r2, r4262; CHECK-NEXT: bfi r3, r0, #8, #8263; CHECK-NEXT: adr r0, .LCPI13_0264; CHECK-NEXT: vldrw.u32 q1, [r0]265; CHECK-NEXT: vmsr p0, r3266; CHECK-NEXT: vmov q0[3], q0[1], r1, r5267; CHECK-NEXT: mvn r2, #-2147483648268; CHECK-NEXT: vpsel q0, q0, q1269; CHECK-NEXT: movs r6, #0270; CHECK-NEXT: vmov r0, r1, d0271; CHECK-NEXT: subs r0, r0, r2272; CHECK-NEXT: sbcs r0, r1, #0273; CHECK-NEXT: csetm r0, lt274; CHECK-NEXT: bfi r6, r0, #0, #8275; CHECK-NEXT: vmov r0, r1, d1276; CHECK-NEXT: subs r0, r0, r2277; CHECK-NEXT: sbcs r0, r1, #0278; CHECK-NEXT: csetm r0, lt279; CHECK-NEXT: bfi r6, r0, #8, #8280; CHECK-NEXT: adr r0, .LCPI13_1281; CHECK-NEXT: vldrw.u32 q1, [r0]282; CHECK-NEXT: vmsr p0, r6283; CHECK-NEXT: vpsel q0, q0, q1284; CHECK-NEXT: pop {r4, r5, r6, pc}285; CHECK-NEXT: .p2align 4286; CHECK-NEXT: @ %bb.1:287; CHECK-NEXT: .LCPI13_0:288; CHECK-NEXT: .long 2147483648 @ 0x80000000289; CHECK-NEXT: .long 4294967295 @ 0xffffffff290; CHECK-NEXT: .long 2147483648 @ 0x80000000291; CHECK-NEXT: .long 4294967295 @ 0xffffffff292; CHECK-NEXT: .LCPI13_1:293; CHECK-NEXT: .long 2147483647 @ 0x7fffffff294; CHECK-NEXT: .long 0 @ 0x0295; CHECK-NEXT: .long 2147483647 @ 0x7fffffff296; CHECK-NEXT: .long 0 @ 0x0297entry:298 %s0 = ashr <2 x i64> %so, <i64 3, i64 3>299 %c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>300 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>301 %c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647>302 %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>303 ret <2 x i64> %s2304}305 306define arm_aapcs_vfpcc <2 x i64> @vqshrni64_umaxmin(<2 x i64> %so) {307; CHECK-LABEL: vqshrni64_umaxmin:308; CHECK: @ %bb.0: @ %entry309; CHECK-NEXT: vmov r0, r1, d1310; CHECK-NEXT: vmov.i64 q1, #0xffffffff311; CHECK-NEXT: vmov r2, r3, d0312; CHECK-NEXT: lsrl r0, r1, #3313; CHECK-NEXT: lsrl r2, r3, #3314; CHECK-NEXT: vmov q0[2], q0[0], r2, r0315; CHECK-NEXT: subs.w r2, r2, #-1316; CHECK-NEXT: sbcs r2, r3, #0317; CHECK-NEXT: vmov q0[3], q0[1], r3, r1318; CHECK-NEXT: csetm r2, lo319; CHECK-NEXT: subs.w r0, r0, #-1320; CHECK-NEXT: mov.w r3, #0321; CHECK-NEXT: sbcs r0, r1, #0322; CHECK-NEXT: bfi r3, r2, #0, #8323; CHECK-NEXT: csetm r0, lo324; CHECK-NEXT: bfi r3, r0, #8, #8325; CHECK-NEXT: vmsr p0, r3326; CHECK-NEXT: vpsel q0, q0, q1327; CHECK-NEXT: bx lr328entry:329 %s0 = lshr <2 x i64> %so, <i64 3, i64 3>330 %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>331 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>332 ret <2 x i64> %s1333}334 335define arm_aapcs_vfpcc <2 x i64> @vqshrni64_uminmax(<2 x i64> %so) {336; CHECK-LABEL: vqshrni64_uminmax:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: vmov r0, r1, d1339; CHECK-NEXT: vmov.i64 q1, #0xffffffff340; CHECK-NEXT: vmov r2, r3, d0341; CHECK-NEXT: lsrl r0, r1, #3342; CHECK-NEXT: lsrl r2, r3, #3343; CHECK-NEXT: vmov q0[2], q0[0], r2, r0344; CHECK-NEXT: subs.w r2, r2, #-1345; CHECK-NEXT: sbcs r2, r3, #0346; CHECK-NEXT: vmov q0[3], q0[1], r3, r1347; CHECK-NEXT: csetm r2, lo348; CHECK-NEXT: subs.w r0, r0, #-1349; CHECK-NEXT: mov.w r3, #0350; CHECK-NEXT: sbcs r0, r1, #0351; CHECK-NEXT: bfi r3, r2, #0, #8352; CHECK-NEXT: csetm r0, lo353; CHECK-NEXT: bfi r3, r0, #8, #8354; CHECK-NEXT: vmsr p0, r3355; CHECK-NEXT: vpsel q0, q0, q1356; CHECK-NEXT: bx lr357entry:358 %s0 = lshr <2 x i64> %so, <i64 3, i64 3>359 %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>360 %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>361 ret <2 x i64> %s2362}363