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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {5; CHECK-LABEL: cmp_sel_C1_or_C2_vec:6; CHECK: @ %bb.0:7; CHECK-NEXT: adr r0, .LCPI0_08; CHECK-NEXT: adr r1, .LCPI0_19; CHECK-NEXT: vcmp.i32 eq, q0, q110; CHECK-NEXT: vldrw.u32 q0, [r1]11; CHECK-NEXT: vldrw.u32 q1, [r0]12; CHECK-NEXT: vpsel q0, q1, q013; CHECK-NEXT: bx lr14; CHECK-NEXT: .p2align 415; CHECK-NEXT: @ %bb.1:16; CHECK-NEXT: .LCPI0_0:17; CHECK-NEXT: .long 3000 @ 0xbb818; CHECK-NEXT: .long 1 @ 0x119; CHECK-NEXT: .long 4294967295 @ 0xffffffff20; CHECK-NEXT: .long 0 @ 0x021; CHECK-NEXT: .LCPI0_1:22; CHECK-NEXT: .long 42 @ 0x2a23; CHECK-NEXT: .long 0 @ 0x024; CHECK-NEXT: .long 4294967294 @ 0xfffffffe25; CHECK-NEXT: .long 4294967295 @ 0xffffffff26 %cond = icmp eq <4 x i32> %x, %y27 %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>28 ret <4 x i32> %add29}30 31define arm_aapcs_vfpcc <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {32; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:33; CHECK: @ %bb.0:34; CHECK-NEXT: adr r0, .LCPI1_035; CHECK-NEXT: adr r1, .LCPI1_136; CHECK-NEXT: vcmp.i32 eq, q0, q137; CHECK-NEXT: vldrw.u32 q0, [r1]38; CHECK-NEXT: vldrw.u32 q1, [r0]39; CHECK-NEXT: vpsel q0, q1, q040; CHECK-NEXT: bx lr41; CHECK-NEXT: .p2align 442; CHECK-NEXT: @ %bb.1:43; CHECK-NEXT: .LCPI1_0:44; CHECK-NEXT: .long 43 @ 0x2b45; CHECK-NEXT: .long 1 @ 0x146; CHECK-NEXT: .long 4294967295 @ 0xffffffff47; CHECK-NEXT: .long 0 @ 0x048; CHECK-NEXT: .LCPI1_1:49; CHECK-NEXT: .long 42 @ 0x2a50; CHECK-NEXT: .long 0 @ 0x051; CHECK-NEXT: .long 4294967294 @ 0xfffffffe52; CHECK-NEXT: .long 4294967295 @ 0xffffffff53 %cond = icmp eq <4 x i32> %x, %y54 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>55 ret <4 x i32> %add56}57 58define arm_aapcs_vfpcc <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {59; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:60; CHECK: @ %bb.0:61; CHECK-NEXT: adr r0, .LCPI2_062; CHECK-NEXT: adr r1, .LCPI2_163; CHECK-NEXT: vcmp.i32 eq, q0, q164; CHECK-NEXT: vldrw.u32 q0, [r1]65; CHECK-NEXT: vldrw.u32 q1, [r0]66; CHECK-NEXT: vpsel q0, q1, q067; CHECK-NEXT: bx lr68; CHECK-NEXT: .p2align 469; CHECK-NEXT: @ %bb.1:70; CHECK-NEXT: .LCPI2_0:71; CHECK-NEXT: .long 43 @ 0x2b72; CHECK-NEXT: .long 1 @ 0x173; CHECK-NEXT: .long 4294967295 @ 0xffffffff74; CHECK-NEXT: .long 0 @ 0x075; CHECK-NEXT: .LCPI2_1:76; CHECK-NEXT: .long 44 @ 0x2c77; CHECK-NEXT: .long 2 @ 0x278; CHECK-NEXT: .long 0 @ 0x079; CHECK-NEXT: .long 1 @ 0x180 %cond = icmp eq <4 x i32> %x, %y81 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>82 ret <4 x i32> %add83}84 85define arm_aapcs_vfpcc <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {86; CHECK-LABEL: cmp_sel_minus1_or_0_vec:87; CHECK: @ %bb.0:88; CHECK-NEXT: vmov.i32 q2, #0x089; CHECK-NEXT: vmov.i8 q3, #0xff90; CHECK-NEXT: vcmp.i32 eq, q0, q191; CHECK-NEXT: vpsel q0, q3, q292; CHECK-NEXT: bx lr93 %cond = icmp eq <4 x i32> %x, %y94 %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>95 ret <4 x i32> %add96}97 98define arm_aapcs_vfpcc <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {99; CHECK-LABEL: cmp_sel_0_or_minus1_vec:100; CHECK: @ %bb.0:101; CHECK-NEXT: vmov.i8 q2, #0xff102; CHECK-NEXT: vmov.i32 q3, #0x0103; CHECK-NEXT: vcmp.i32 eq, q0, q1104; CHECK-NEXT: vpsel q0, q3, q2105; CHECK-NEXT: bx lr106 %cond = icmp eq <4 x i32> %x, %y107 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>108 ret <4 x i32> %add109}110 111define arm_aapcs_vfpcc <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {112; CHECK-LABEL: cmp_sel_1_or_0_vec:113; CHECK: @ %bb.0:114; CHECK-NEXT: vmov.i32 q2, #0x0115; CHECK-NEXT: vmov.i32 q3, #0x1116; CHECK-NEXT: vcmp.i32 eq, q0, q1117; CHECK-NEXT: vpsel q0, q3, q2118; CHECK-NEXT: bx lr119 %cond = icmp eq <4 x i32> %x, %y120 %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>121 ret <4 x i32> %add122}123 124define arm_aapcs_vfpcc <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {125; CHECK-LABEL: cmp_sel_0_or_1_vec:126; CHECK: @ %bb.0:127; CHECK-NEXT: vmov.i32 q2, #0x1128; CHECK-NEXT: vmov.i32 q3, #0x0129; CHECK-NEXT: vcmp.i32 eq, q0, q1130; CHECK-NEXT: vpsel q0, q3, q2131; CHECK-NEXT: bx lr132 %cond = icmp eq <4 x i32> %x, %y133 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>134 ret <4 x i32> %add135}136 137define arm_aapcs_vfpcc <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {138; CHECK-LABEL: signbit_mask_v16i8:139; CHECK: @ %bb.0:140; CHECK-NEXT: vshr.s8 q0, q0, #7141; CHECK-NEXT: vand q0, q0, q1142; CHECK-NEXT: bx lr143 %cond = icmp slt <16 x i8> %a, zeroinitializer144 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer145 ret <16 x i8> %r146}147 148define arm_aapcs_vfpcc <8 x i16> @signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {149; CHECK-LABEL: signbit_mask_v8i16:150; CHECK: @ %bb.0:151; CHECK-NEXT: vshr.s16 q0, q0, #15152; CHECK-NEXT: vand q0, q0, q1153; CHECK-NEXT: bx lr154 %cond = icmp slt <8 x i16> %a, zeroinitializer155 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer156 ret <8 x i16> %r157}158 159define arm_aapcs_vfpcc <4 x i32> @signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {160; CHECK-LABEL: signbit_mask_v4i32:161; CHECK: @ %bb.0:162; CHECK-NEXT: vshr.s32 q0, q0, #31163; CHECK-NEXT: vand q0, q0, q1164; CHECK-NEXT: bx lr165 %cond = icmp slt <4 x i32> %a, zeroinitializer166 %r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer167 ret <4 x i32> %r168}169 170define arm_aapcs_vfpcc <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {171; CHECK-LABEL: signbit_mask_v2i64:172; CHECK: @ %bb.0:173; CHECK-NEXT: vmov r1, s1174; CHECK-NEXT: movs r0, #0175; CHECK-NEXT: vmov.i32 q2, #0x0176; CHECK-NEXT: asrs r1, r1, #31177; CHECK-NEXT: bfi r0, r1, #0, #8178; CHECK-NEXT: vmov r1, s3179; CHECK-NEXT: asrs r1, r1, #31180; CHECK-NEXT: bfi r0, r1, #8, #8181; CHECK-NEXT: vmsr p0, r0182; CHECK-NEXT: vpsel q0, q1, q2183; CHECK-NEXT: bx lr184 %cond = icmp slt <2 x i64> %a, zeroinitializer185 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer186 ret <2 x i64> %r187}188 189define arm_aapcs_vfpcc <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) {190; CHECK-LABEL: signbit_setmask_v16i8:191; CHECK: @ %bb.0:192; CHECK-NEXT: vshr.s8 q0, q0, #7193; CHECK-NEXT: vorr q0, q0, q1194; CHECK-NEXT: bx lr195 %cond = icmp slt <16 x i8> %a, zeroinitializer196 %r = select <16 x i1> %cond, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %b197 ret <16 x i8> %r198}199 200define arm_aapcs_vfpcc <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) {201; CHECK-LABEL: signbit_setmask_v8i16:202; CHECK: @ %bb.0:203; CHECK-NEXT: vshr.s16 q0, q0, #15204; CHECK-NEXT: vorr q0, q0, q1205; CHECK-NEXT: bx lr206 %cond = icmp slt <8 x i16> %a, zeroinitializer207 %r = select <8 x i1> %cond, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %b208 ret <8 x i16> %r209}210 211define arm_aapcs_vfpcc <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) {212; CHECK-LABEL: signbit_setmask_v4i32:213; CHECK: @ %bb.0:214; CHECK-NEXT: vshr.s32 q0, q0, #31215; CHECK-NEXT: vorr q0, q0, q1216; CHECK-NEXT: bx lr217 %cond = icmp slt <4 x i32> %a, zeroinitializer218 %r = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %b219 ret <4 x i32> %r220}221 222define arm_aapcs_vfpcc <2 x i64> @signbit_setmask_v2i64(<2 x i64> %a, <2 x i64> %b) {223; CHECK-LABEL: signbit_setmask_v2i64:224; CHECK: @ %bb.0:225; CHECK-NEXT: vmov r1, s1226; CHECK-NEXT: movs r0, #0227; CHECK-NEXT: vmov.i8 q2, #0xff228; CHECK-NEXT: asrs r1, r1, #31229; CHECK-NEXT: bfi r0, r1, #0, #8230; CHECK-NEXT: vmov r1, s3231; CHECK-NEXT: asrs r1, r1, #31232; CHECK-NEXT: bfi r0, r1, #8, #8233; CHECK-NEXT: vmsr p0, r0234; CHECK-NEXT: vpsel q0, q2, q1235; CHECK-NEXT: bx lr236 %cond = icmp slt <2 x i64> %a, zeroinitializer237 %r = select <2 x i1> %cond, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %b238 ret <2 x i64> %r239}240define arm_aapcs_vfpcc <16 x i8> @not_signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {241; CHECK-LABEL: not_signbit_mask_v16i8:242; CHECK: @ %bb.0:243; CHECK-NEXT: vmov.i8 q2, #0xff244; CHECK-NEXT: vmov.i32 q3, #0x0245; CHECK-NEXT: vcmp.s8 gt, q0, q2246; CHECK-NEXT: vpsel q0, q1, q3247; CHECK-NEXT: bx lr248 %cond = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>249 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer250 ret <16 x i8> %r251}252 253define arm_aapcs_vfpcc <8 x i16> @not_signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {254; CHECK-LABEL: not_signbit_mask_v8i16:255; CHECK: @ %bb.0:256; CHECK-NEXT: vmov.i8 q2, #0xff257; CHECK-NEXT: vmov.i32 q3, #0x0258; CHECK-NEXT: vcmp.s16 gt, q0, q2259; CHECK-NEXT: vpsel q0, q1, q3260; CHECK-NEXT: bx lr261 %cond = icmp sgt <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>262 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer263 ret <8 x i16> %r264}265 266define arm_aapcs_vfpcc <4 x i32> @not_signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {267; CHECK-LABEL: not_signbit_mask_v4i32:268; CHECK: @ %bb.0:269; CHECK-NEXT: vmov.i8 q2, #0xff270; CHECK-NEXT: vmov.i32 q3, #0x0271; CHECK-NEXT: vcmp.s32 gt, q0, q2272; CHECK-NEXT: vpsel q0, q1, q3273; CHECK-NEXT: bx lr274 %cond = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>275 %r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer276 ret <4 x i32> %r277}278 279define arm_aapcs_vfpcc <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {280; CHECK-LABEL: not_signbit_mask_v2i64:281; CHECK: @ %bb.0:282; CHECK-NEXT: vmov r1, s1283; CHECK-NEXT: movs r0, #0284; CHECK-NEXT: vmov.i32 q2, #0x0285; CHECK-NEXT: mvns r1, r1286; CHECK-NEXT: asrs r1, r1, #31287; CHECK-NEXT: bfi r0, r1, #0, #8288; CHECK-NEXT: vmov r1, s3289; CHECK-NEXT: mvns r1, r1290; CHECK-NEXT: asrs r1, r1, #31291; CHECK-NEXT: bfi r0, r1, #8, #8292; CHECK-NEXT: vmsr p0, r0293; CHECK-NEXT: vpsel q0, q1, q2294; CHECK-NEXT: bx lr295 %cond = icmp sgt <2 x i64> %a, <i64 -1, i64 -1>296 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer297 ret <2 x i64> %r298}299