1321 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s3 4; i325 6define void @vst4_v2i32(ptr %src, ptr %dst) {7; CHECK-LABEL: vst4_v2i32:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: .save {r4, r5, r6, lr}10; CHECK-NEXT: push {r4, r5, r6, lr}11; CHECK-NEXT: add.w r6, r0, #1612; CHECK-NEXT: ldrd lr, r12, [r0]13; CHECK-NEXT: ldrd r3, r2, [r0, #8]14; CHECK-NEXT: ldm r6, {r4, r5, r6}15; CHECK-NEXT: vmov q1[2], q1[0], lr, r316; CHECK-NEXT: ldr r0, [r0, #28]17; CHECK-NEXT: vmov q1[3], q1[1], r12, r218; CHECK-NEXT: vmov q0[2], q0[0], r4, r619; CHECK-NEXT: vmov.f32 s8, s420; CHECK-NEXT: vmov q0[3], q0[1], r5, r021; CHECK-NEXT: vmov.f32 s9, s622; CHECK-NEXT: vmov.f32 s4, s523; CHECK-NEXT: vmov.f32 s5, s724; CHECK-NEXT: vmov.f32 s10, s025; CHECK-NEXT: vmov.f32 s11, s226; CHECK-NEXT: vmov.f32 s6, s127; CHECK-NEXT: vstrw.32 q2, [r1]28; CHECK-NEXT: vmov.f32 s7, s329; CHECK-NEXT: vstrw.32 q1, [r1, #16]30; CHECK-NEXT: pop {r4, r5, r6, pc}31entry:32 %l1 = load <2 x i32>, ptr %src, align 433 %s2 = getelementptr <2 x i32>, ptr %src, i32 134 %l2 = load <2 x i32>, ptr %s2, align 435 %s3 = getelementptr <2 x i32>, ptr %src, i32 236 %l3 = load <2 x i32>, ptr %s3, align 437 %s4 = getelementptr <2 x i32>, ptr %src, i32 338 %l4 = load <2 x i32>, ptr %s4, align 439 %t1 = shufflevector <2 x i32> %l1, <2 x i32> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>40 %t2 = shufflevector <2 x i32> %l3, <2 x i32> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>41 %s = shufflevector <4 x i32> %t1, <4 x i32> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>42 store <8 x i32> %s, ptr %dst, align 443 ret void44}45 46define void @vst4_v4i32(ptr %src, ptr %dst) {47; CHECK-LABEL: vst4_v4i32:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vldrw.u32 q3, [r0, #48]50; CHECK-NEXT: vldrw.u32 q2, [r0, #32]51; CHECK-NEXT: vldrw.u32 q1, [r0, #16]52; CHECK-NEXT: vldrw.u32 q0, [r0]53; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]54; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]55; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]56; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]57; CHECK-NEXT: bx lr58entry:59 %l1 = load <4 x i32>, ptr %src, align 460 %s2 = getelementptr <4 x i32>, ptr %src, i32 161 %l2 = load <4 x i32>, ptr %s2, align 462 %s3 = getelementptr <4 x i32>, ptr %src, i32 263 %l3 = load <4 x i32>, ptr %s3, align 464 %s4 = getelementptr <4 x i32>, ptr %src, i32 365 %l4 = load <4 x i32>, ptr %s4, align 466 %t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>67 %t2 = shufflevector <4 x i32> %l3, <4 x i32> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>68 %s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>69 store <16 x i32> %s, ptr %dst, align 470 ret void71}72 73define void @vst4_v8i32(ptr %src, ptr %dst) {74; CHECK-LABEL: vst4_v8i32:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}77; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}78; CHECK-NEXT: vldrw.u32 q7, [r0, #96]79; CHECK-NEXT: vldrw.u32 q6, [r0, #64]80; CHECK-NEXT: vldrw.u32 q5, [r0, #32]81; CHECK-NEXT: vldrw.u32 q4, [r0]82; CHECK-NEXT: vldrw.u32 q3, [r0, #112]83; CHECK-NEXT: vldrw.u32 q2, [r0, #80]84; CHECK-NEXT: vldrw.u32 q1, [r0, #48]85; CHECK-NEXT: vldrw.u32 q0, [r0, #16]86; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]87; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]88; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]89; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]!90; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]91; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]92; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]93; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]94; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}95; CHECK-NEXT: bx lr96entry:97 %l1 = load <8 x i32>, ptr %src, align 498 %s2 = getelementptr <8 x i32>, ptr %src, i32 199 %l2 = load <8 x i32>, ptr %s2, align 4100 %s3 = getelementptr <8 x i32>, ptr %src, i32 2101 %l3 = load <8 x i32>, ptr %s3, align 4102 %s4 = getelementptr <8 x i32>, ptr %src, i32 3103 %l4 = load <8 x i32>, ptr %s4, align 4104 %t1 = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>105 %t2 = shufflevector <8 x i32> %l3, <8 x i32> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>106 %s = shufflevector <16 x i32> %t1, <16 x i32> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>107 store <32 x i32> %s, ptr %dst, align 4108 ret void109}110 111define void @vst4_v16i32(ptr %src, ptr %dst) {112; CHECK-LABEL: vst4_v16i32:113; CHECK: @ %bb.0: @ %entry114; CHECK-NEXT: .save {r4, r5}115; CHECK-NEXT: push {r4, r5}116; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}117; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}118; CHECK-NEXT: .pad #192119; CHECK-NEXT: sub sp, #192120; CHECK-NEXT: vldrw.u32 q0, [r0, #16]121; CHECK-NEXT: add r2, sp, #64122; CHECK-NEXT: vldrw.u32 q3, [r0, #208]123; CHECK-NEXT: vldrw.u32 q2, [r0, #144]124; CHECK-NEXT: vldrw.u32 q1, [r0, #80]125; CHECK-NEXT: vstmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill126; CHECK-NEXT: vldrw.u32 q0, [r0]127; CHECK-NEXT: vldrw.u32 q2, [r0, #128]128; CHECK-NEXT: vldrw.u32 q3, [r0, #192]129; CHECK-NEXT: vldrw.u32 q1, [r0, #64]130; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill131; CHECK-NEXT: vldrw.u32 q6, [r0, #176]132; CHECK-NEXT: vldrw.u32 q2, [r0, #160]133; CHECK-NEXT: vldrw.u32 q4, [r0, #48]134; CHECK-NEXT: add r2, sp, #128135; CHECK-NEXT: vldrw.u32 q7, [r0, #240]136; CHECK-NEXT: vldrw.u32 q3, [r0, #224]137; CHECK-NEXT: vldrw.u32 q1, [r0, #96]138; CHECK-NEXT: vldrw.u32 q5, [r0, #112]139; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill140; CHECK-NEXT: vmov q6, q2141; CHECK-NEXT: vmov q5, q1142; CHECK-NEXT: vmov q7, q3143; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload144; CHECK-NEXT: add r2, sp, #64145; CHECK-NEXT: vldrw.u32 q4, [r0, #32]146; CHECK-NEXT: mov r0, r1147; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]148; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]149; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]150; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]!151; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload152; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]153; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]154; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]155; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]156; CHECK-NEXT: add.w r0, r1, #192157; CHECK-NEXT: adds r1, #128158; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]159; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]160; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]161; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]162; CHECK-NEXT: add r1, sp, #128163; CHECK-NEXT: vldmia r1, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload164; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]165; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]166; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]167; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]168; CHECK-NEXT: add sp, #192169; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}170; CHECK-NEXT: pop {r4, r5}171; CHECK-NEXT: bx lr172entry:173 %l1 = load <16 x i32>, ptr %src, align 4174 %s2 = getelementptr <16 x i32>, ptr %src, i32 1175 %l2 = load <16 x i32>, ptr %s2, align 4176 %s3 = getelementptr <16 x i32>, ptr %src, i32 2177 %l3 = load <16 x i32>, ptr %s3, align 4178 %s4 = getelementptr <16 x i32>, ptr %src, i32 3179 %l4 = load <16 x i32>, ptr %s4, align 4180 %t1 = shufflevector <16 x i32> %l1, <16 x i32> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>181 %t2 = shufflevector <16 x i32> %l3, <16 x i32> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>182 %s = shufflevector <32 x i32> %t1, <32 x i32> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>183 store <64 x i32> %s, ptr %dst, align 4184 ret void185}186 187define void @vst4_v4i32_align1(ptr %src, ptr %dst) {188; CHECK-LABEL: vst4_v4i32_align1:189; CHECK: @ %bb.0: @ %entry190; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}191; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}192; CHECK-NEXT: vldrw.u32 q1, [r0, #48]193; CHECK-NEXT: vldrw.u32 q0, [r0, #32]194; CHECK-NEXT: vldrw.u32 q2, [r0, #16]195; CHECK-NEXT: vldrw.u32 q4, [r0]196; CHECK-NEXT: vmov.f32 s14, s1197; CHECK-NEXT: vmov.f32 s22, s0198; CHECK-NEXT: vmov.f32 s26, s3199; CHECK-NEXT: vmov.f32 s12, s17200; CHECK-NEXT: vmov.f32 s13, s9201; CHECK-NEXT: vmov.f32 s15, s5202; CHECK-NEXT: vmov.f32 s20, s16203; CHECK-NEXT: vstrb.8 q3, [r1, #16]204; CHECK-NEXT: vmov.f32 s21, s8205; CHECK-NEXT: vmov.f32 s23, s4206; CHECK-NEXT: vmov.f32 s24, s19207; CHECK-NEXT: vstrb.8 q5, [r1]208; CHECK-NEXT: vmov.f32 s25, s11209; CHECK-NEXT: vmov.f32 s27, s7210; CHECK-NEXT: vmov.f32 s0, s18211; CHECK-NEXT: vstrb.8 q6, [r1, #48]212; CHECK-NEXT: vmov.f32 s1, s10213; CHECK-NEXT: vmov.f32 s3, s6214; CHECK-NEXT: vstrb.8 q0, [r1, #32]215; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}216; CHECK-NEXT: bx lr217entry:218 %l1 = load <4 x i32>, ptr %src, align 4219 %s2 = getelementptr <4 x i32>, ptr %src, i32 1220 %l2 = load <4 x i32>, ptr %s2, align 4221 %s3 = getelementptr <4 x i32>, ptr %src, i32 2222 %l3 = load <4 x i32>, ptr %s3, align 4223 %s4 = getelementptr <4 x i32>, ptr %src, i32 3224 %l4 = load <4 x i32>, ptr %s4, align 4225 %t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>226 %t2 = shufflevector <4 x i32> %l3, <4 x i32> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>227 %s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>228 store <16 x i32> %s, ptr %dst, align 1229 ret void230}231 232; i16233 234define void @vst4_v2i16(ptr %src, ptr %dst) {235; CHECK-LABEL: vst4_v2i16:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: .save {r4, r5, r6, lr}238; CHECK-NEXT: push {r4, r5, r6, lr}239; CHECK-NEXT: ldrh r2, [r0, #4]240; CHECK-NEXT: ldrh r3, [r0, #8]241; CHECK-NEXT: ldrh.w r12, [r0, #12]242; CHECK-NEXT: ldrh.w lr, [r0, #2]243; CHECK-NEXT: ldrh r4, [r0, #6]244; CHECK-NEXT: ldrh r5, [r0, #10]245; CHECK-NEXT: ldrh r6, [r0, #14]246; CHECK-NEXT: ldrh r0, [r0]247; CHECK-NEXT: vmov.16 q0[0], r0248; CHECK-NEXT: vmov.16 q0[1], r2249; CHECK-NEXT: vmov.16 q0[2], r3250; CHECK-NEXT: vmov.16 q0[3], r12251; CHECK-NEXT: vmov.16 q0[4], lr252; CHECK-NEXT: vmov.16 q0[5], r4253; CHECK-NEXT: vmov.16 q0[6], r5254; CHECK-NEXT: vmov.16 q0[7], r6255; CHECK-NEXT: vstrh.16 q0, [r1]256; CHECK-NEXT: pop {r4, r5, r6, pc}257entry:258 %l1 = load <2 x i16>, ptr %src, align 4259 %s2 = getelementptr <2 x i16>, ptr %src, i32 1260 %l2 = load <2 x i16>, ptr %s2, align 4261 %s3 = getelementptr <2 x i16>, ptr %src, i32 2262 %l3 = load <2 x i16>, ptr %s3, align 4263 %s4 = getelementptr <2 x i16>, ptr %src, i32 3264 %l4 = load <2 x i16>, ptr %s4, align 4265 %t1 = shufflevector <2 x i16> %l1, <2 x i16> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>266 %t2 = shufflevector <2 x i16> %l3, <2 x i16> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>267 %s = shufflevector <4 x i16> %t1, <4 x i16> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>268 store <8 x i16> %s, ptr %dst, align 2269 ret void270}271 272define void @vst4_v4i16(ptr %src, ptr %dst) {273; CHECK-LABEL: vst4_v4i16:274; CHECK: @ %bb.0: @ %entry275; CHECK-NEXT: .save {r4, r5, r6, lr}276; CHECK-NEXT: push {r4, r5, r6, lr}277; CHECK-NEXT: .vsave {d8, d9}278; CHECK-NEXT: vpush {d8, d9}279; CHECK-NEXT: vldrh.u32 q0, [r0]280; CHECK-NEXT: vldrh.u32 q3, [r0, #8]281; CHECK-NEXT: vldrh.u32 q1, [r0, #16]282; CHECK-NEXT: vldrh.u32 q4, [r0, #24]283; CHECK-NEXT: vmov r3, r4, d1284; CHECK-NEXT: vmov r5, r12, d0285; CHECK-NEXT: vmov.16 q2[0], r3286; CHECK-NEXT: vmov.16 q0[0], r5287; CHECK-NEXT: vmov r0, r5, d7288; CHECK-NEXT: vmov.16 q2[1], r0289; CHECK-NEXT: vmov r2, lr, d3290; CHECK-NEXT: vmov r0, r3, d9291; CHECK-NEXT: vmov.16 q2[2], r2292; CHECK-NEXT: vmov.16 q2[3], r0293; CHECK-NEXT: vmov r0, r6, d8294; CHECK-NEXT: vmov.16 q2[4], r4295; CHECK-NEXT: vmov.16 q2[5], r5296; CHECK-NEXT: vmov r4, r5, d6297; CHECK-NEXT: vmov.16 q2[6], lr298; CHECK-NEXT: vmov.16 q0[1], r4299; CHECK-NEXT: vmov.16 q2[7], r3300; CHECK-NEXT: vmov r3, r2, d2301; CHECK-NEXT: vmov.16 q0[2], r3302; CHECK-NEXT: vstrh.16 q2, [r1, #16]303; CHECK-NEXT: vmov.16 q0[3], r0304; CHECK-NEXT: vmov.16 q0[4], r12305; CHECK-NEXT: vmov.16 q0[5], r5306; CHECK-NEXT: vmov.16 q0[6], r2307; CHECK-NEXT: vmov.16 q0[7], r6308; CHECK-NEXT: vstrh.16 q0, [r1]309; CHECK-NEXT: vpop {d8, d9}310; CHECK-NEXT: pop {r4, r5, r6, pc}311entry:312 %l1 = load <4 x i16>, ptr %src, align 4313 %s2 = getelementptr <4 x i16>, ptr %src, i32 1314 %l2 = load <4 x i16>, ptr %s2, align 4315 %s3 = getelementptr <4 x i16>, ptr %src, i32 2316 %l3 = load <4 x i16>, ptr %s3, align 4317 %s4 = getelementptr <4 x i16>, ptr %src, i32 3318 %l4 = load <4 x i16>, ptr %s4, align 4319 %t1 = shufflevector <4 x i16> %l1, <4 x i16> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>320 %t2 = shufflevector <4 x i16> %l3, <4 x i16> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>321 %s = shufflevector <8 x i16> %t1, <8 x i16> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>322 store <16 x i16> %s, ptr %dst, align 2323 ret void324}325 326define void @vst4_v8i16(ptr %src, ptr %dst) {327; CHECK-LABEL: vst4_v8i16:328; CHECK: @ %bb.0: @ %entry329; CHECK-NEXT: vldrw.u32 q3, [r0, #48]330; CHECK-NEXT: vldrw.u32 q2, [r0, #32]331; CHECK-NEXT: vldrw.u32 q1, [r0, #16]332; CHECK-NEXT: vldrw.u32 q0, [r0]333; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]334; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]335; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]336; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]337; CHECK-NEXT: bx lr338entry:339 %l1 = load <8 x i16>, ptr %src, align 4340 %s2 = getelementptr <8 x i16>, ptr %src, i32 1341 %l2 = load <8 x i16>, ptr %s2, align 4342 %s3 = getelementptr <8 x i16>, ptr %src, i32 2343 %l3 = load <8 x i16>, ptr %s3, align 4344 %s4 = getelementptr <8 x i16>, ptr %src, i32 3345 %l4 = load <8 x i16>, ptr %s4, align 4346 %t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>347 %t2 = shufflevector <8 x i16> %l3, <8 x i16> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>348 %s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>349 store <32 x i16> %s, ptr %dst, align 2350 ret void351}352 353define void @vst4_v16i16(ptr %src, ptr %dst) {354; CHECK-LABEL: vst4_v16i16:355; CHECK: @ %bb.0: @ %entry356; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}357; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}358; CHECK-NEXT: vldrw.u32 q7, [r0, #96]359; CHECK-NEXT: vldrw.u32 q6, [r0, #64]360; CHECK-NEXT: vldrw.u32 q5, [r0, #32]361; CHECK-NEXT: vldrw.u32 q4, [r0]362; CHECK-NEXT: vldrw.u32 q3, [r0, #112]363; CHECK-NEXT: vldrw.u32 q2, [r0, #80]364; CHECK-NEXT: vldrw.u32 q1, [r0, #48]365; CHECK-NEXT: vldrw.u32 q0, [r0, #16]366; CHECK-NEXT: vst40.16 {q4, q5, q6, q7}, [r1]367; CHECK-NEXT: vst41.16 {q4, q5, q6, q7}, [r1]368; CHECK-NEXT: vst42.16 {q4, q5, q6, q7}, [r1]369; CHECK-NEXT: vst43.16 {q4, q5, q6, q7}, [r1]!370; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]371; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]372; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]373; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]374; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}375; CHECK-NEXT: bx lr376entry:377 %l1 = load <16 x i16>, ptr %src, align 4378 %s2 = getelementptr <16 x i16>, ptr %src, i32 1379 %l2 = load <16 x i16>, ptr %s2, align 4380 %s3 = getelementptr <16 x i16>, ptr %src, i32 2381 %l3 = load <16 x i16>, ptr %s3, align 4382 %s4 = getelementptr <16 x i16>, ptr %src, i32 3383 %l4 = load <16 x i16>, ptr %s4, align 4384 %t1 = shufflevector <16 x i16> %l1, <16 x i16> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>385 %t2 = shufflevector <16 x i16> %l3, <16 x i16> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>386 %s = shufflevector <32 x i16> %t1, <32 x i16> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>387 store <64 x i16> %s, ptr %dst, align 2388 ret void389}390 391define void @vst4_v8i16_align1(ptr %src, ptr %dst) {392; CHECK-LABEL: vst4_v8i16_align1:393; CHECK: @ %bb.0: @ %entry394; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}395; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}396; CHECK-NEXT: vldrw.u32 q1, [r0, #32]397; CHECK-NEXT: vldrw.u32 q2, [r0, #48]398; CHECK-NEXT: vldrw.u32 q3, [r0]399; CHECK-NEXT: vldrw.u32 q4, [r0, #16]400; CHECK-NEXT: vmovx.f16 s23, s4401; CHECK-NEXT: vins.f16 s4, s8402; CHECK-NEXT: vmov.f32 s21, s4403; CHECK-NEXT: vmovx.f16 s22, s12404; CHECK-NEXT: vmovx.f16 s4, s16405; CHECK-NEXT: vmovx.f16 s27, s7406; CHECK-NEXT: vins.f16 s22, s4407; CHECK-NEXT: vmovx.f16 s4, s11408; CHECK-NEXT: vins.f16 s7, s11409; CHECK-NEXT: vins.f16 s27, s4410; CHECK-NEXT: vmovx.f16 s26, s15411; CHECK-NEXT: vmovx.f16 s4, s19412; CHECK-NEXT: vmovx.f16 s3, s5413; CHECK-NEXT: vins.f16 s5, s9414; CHECK-NEXT: vmovx.f16 s0, s9415; CHECK-NEXT: vmov.f32 s25, s7416; CHECK-NEXT: vins.f16 s26, s4417; CHECK-NEXT: vmovx.f16 s7, s6418; CHECK-NEXT: vmovx.f16 s4, s10419; CHECK-NEXT: vins.f16 s6, s10420; CHECK-NEXT: vins.f16 s3, s0421; CHECK-NEXT: vmovx.f16 s2, s13422; CHECK-NEXT: vmovx.f16 s0, s17423; CHECK-NEXT: vmov.f32 s1, s5424; CHECK-NEXT: vmovx.f16 s8, s8425; CHECK-NEXT: vins.f16 s12, s16426; CHECK-NEXT: vins.f16 s15, s19427; CHECK-NEXT: vins.f16 s7, s4428; CHECK-NEXT: vmov.f32 s5, s6429; CHECK-NEXT: vmovx.f16 s6, s14430; CHECK-NEXT: vmovx.f16 s4, s18431; CHECK-NEXT: vins.f16 s13, s17432; CHECK-NEXT: vins.f16 s14, s18433; CHECK-NEXT: vins.f16 s2, s0434; CHECK-NEXT: vmov.f32 s0, s13435; CHECK-NEXT: vins.f16 s6, s4436; CHECK-NEXT: vmov.f32 s24, s15437; CHECK-NEXT: vins.f16 s23, s8438; CHECK-NEXT: vmov.f32 s20, s12439; CHECK-NEXT: vstrb.8 q6, [r1, #48]440; CHECK-NEXT: vmov.f32 s4, s14441; CHECK-NEXT: vstrb.8 q0, [r1, #16]442; CHECK-NEXT: vstrb.8 q1, [r1, #32]443; CHECK-NEXT: vstrb.8 q5, [r1]444; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}445; CHECK-NEXT: bx lr446entry:447 %l1 = load <8 x i16>, ptr %src, align 4448 %s2 = getelementptr <8 x i16>, ptr %src, i32 1449 %l2 = load <8 x i16>, ptr %s2, align 4450 %s3 = getelementptr <8 x i16>, ptr %src, i32 2451 %l3 = load <8 x i16>, ptr %s3, align 4452 %s4 = getelementptr <8 x i16>, ptr %src, i32 3453 %l4 = load <8 x i16>, ptr %s4, align 4454 %t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>455 %t2 = shufflevector <8 x i16> %l3, <8 x i16> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>456 %s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>457 store <32 x i16> %s, ptr %dst, align 1458 ret void459}460 461; i8462 463define void @vst4_v2i8(ptr %src, ptr %dst) {464; CHECK-LABEL: vst4_v2i8:465; CHECK: @ %bb.0: @ %entry466; CHECK-NEXT: .save {r4, r5, r6, lr}467; CHECK-NEXT: push {r4, r5, r6, lr}468; CHECK-NEXT: ldrb r4, [r0]469; CHECK-NEXT: ldrb r6, [r0, #2]470; CHECK-NEXT: vmov.16 q0[0], r4471; CHECK-NEXT: ldrb r2, [r0, #4]472; CHECK-NEXT: vmov.16 q0[1], r6473; CHECK-NEXT: ldrb r3, [r0, #6]474; CHECK-NEXT: vmov.16 q0[2], r2475; CHECK-NEXT: ldrb r5, [r0, #1]476; CHECK-NEXT: vmov.16 q0[3], r3477; CHECK-NEXT: ldrb.w r12, [r0, #5]478; CHECK-NEXT: ldrb.w lr, [r0, #7]479; CHECK-NEXT: vmov.16 q0[4], r5480; CHECK-NEXT: ldrb r0, [r0, #3]481; CHECK-NEXT: vmov.16 q0[5], r0482; CHECK-NEXT: vmov.16 q0[6], r12483; CHECK-NEXT: vmov.16 q0[7], lr484; CHECK-NEXT: vstrb.16 q0, [r1]485; CHECK-NEXT: pop {r4, r5, r6, pc}486entry:487 %l1 = load <2 x i8>, ptr %src, align 4488 %s2 = getelementptr <2 x i8>, ptr %src, i32 1489 %l2 = load <2 x i8>, ptr %s2, align 4490 %s3 = getelementptr <2 x i8>, ptr %src, i32 2491 %l3 = load <2 x i8>, ptr %s3, align 4492 %s4 = getelementptr <2 x i8>, ptr %src, i32 3493 %l4 = load <2 x i8>, ptr %s4, align 4494 %t1 = shufflevector <2 x i8> %l1, <2 x i8> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>495 %t2 = shufflevector <2 x i8> %l3, <2 x i8> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>496 %s = shufflevector <4 x i8> %t1, <4 x i8> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>497 store <8 x i8> %s, ptr %dst, align 1498 ret void499}500 501define void @vst4_v4i8(ptr %src, ptr %dst) {502; CHECK-LABEL: vst4_v4i8:503; CHECK: @ %bb.0: @ %entry504; CHECK-NEXT: .save {r4, r5, r6, r7, lr}505; CHECK-NEXT: push {r4, r5, r6, r7, lr}506; CHECK-NEXT: .pad #4507; CHECK-NEXT: sub sp, #4508; CHECK-NEXT: .vsave {d8, d9}509; CHECK-NEXT: vpush {d8, d9}510; CHECK-NEXT: vldrb.u32 q2, [r0]511; CHECK-NEXT: vldrb.u32 q3, [r0, #4]512; CHECK-NEXT: vldrb.u32 q1, [r0, #8]513; CHECK-NEXT: vldrb.u32 q4, [r0, #12]514; CHECK-NEXT: vmov r4, r5, d4515; CHECK-NEXT: vmov.8 q0[0], r4516; CHECK-NEXT: vmov r2, lr, d6517; CHECK-NEXT: vmov.8 q0[1], r2518; CHECK-NEXT: vmov r0, r4, d2519; CHECK-NEXT: vmov r3, r12, d8520; CHECK-NEXT: vmov.8 q0[2], r0521; CHECK-NEXT: vmov.8 q0[3], r3522; CHECK-NEXT: vmov r2, r7, d9523; CHECK-NEXT: vmov.8 q0[4], r5524; CHECK-NEXT: vmov r3, r5, d7525; CHECK-NEXT: vmov.8 q0[5], lr526; CHECK-NEXT: vmov.8 q0[6], r4527; CHECK-NEXT: vmov r4, r0, d5528; CHECK-NEXT: vmov.8 q0[7], r12529; CHECK-NEXT: vmov.8 q0[8], r4530; CHECK-NEXT: vmov r4, r6, d3531; CHECK-NEXT: vmov.8 q0[9], r3532; CHECK-NEXT: vmov.8 q0[10], r4533; CHECK-NEXT: vmov.8 q0[11], r2534; CHECK-NEXT: vmov.8 q0[12], r0535; CHECK-NEXT: vmov.8 q0[13], r5536; CHECK-NEXT: vmov.8 q0[14], r6537; CHECK-NEXT: vmov.8 q0[15], r7538; CHECK-NEXT: vstrb.8 q0, [r1]539; CHECK-NEXT: vpop {d8, d9}540; CHECK-NEXT: add sp, #4541; CHECK-NEXT: pop {r4, r5, r6, r7, pc}542entry:543 %l1 = load <4 x i8>, ptr %src, align 4544 %s2 = getelementptr <4 x i8>, ptr %src, i32 1545 %l2 = load <4 x i8>, ptr %s2, align 4546 %s3 = getelementptr <4 x i8>, ptr %src, i32 2547 %l3 = load <4 x i8>, ptr %s3, align 4548 %s4 = getelementptr <4 x i8>, ptr %src, i32 3549 %l4 = load <4 x i8>, ptr %s4, align 4550 %t1 = shufflevector <4 x i8> %l1, <4 x i8> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>551 %t2 = shufflevector <4 x i8> %l3, <4 x i8> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>552 %s = shufflevector <8 x i8> %t1, <8 x i8> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>553 store <16 x i8> %s, ptr %dst, align 1554 ret void555}556 557define void @vst4_v8i8(ptr %src, ptr %dst) {558; CHECK-LABEL: vst4_v8i8:559; CHECK: @ %bb.0: @ %entry560; CHECK-NEXT: .vsave {d8, d9, d10, d11}561; CHECK-NEXT: vpush {d8, d9, d10, d11}562; CHECK-NEXT: vldrb.u16 q1, [r0]563; CHECK-NEXT: vldrb.u16 q2, [r0, #8]564; CHECK-NEXT: vldrb.u16 q3, [r0, #16]565; CHECK-NEXT: vldrb.u16 q4, [r0, #24]566; CHECK-NEXT: vmov.u16 r2, q1[4]567; CHECK-NEXT: vmov.8 q0[0], r2568; CHECK-NEXT: vmov.u16 r2, q2[4]569; CHECK-NEXT: vmov.8 q0[1], r2570; CHECK-NEXT: vmov.u16 r2, q3[4]571; CHECK-NEXT: vmov.8 q0[2], r2572; CHECK-NEXT: vmov.u16 r0, q4[4]573; CHECK-NEXT: vmov.8 q0[3], r0574; CHECK-NEXT: vmov.u16 r0, q1[5]575; CHECK-NEXT: vmov.8 q0[4], r0576; CHECK-NEXT: vmov.u16 r0, q2[5]577; CHECK-NEXT: vmov.8 q0[5], r0578; CHECK-NEXT: vmov.u16 r0, q3[5]579; CHECK-NEXT: vmov.8 q0[6], r0580; CHECK-NEXT: vmov.u16 r0, q4[5]581; CHECK-NEXT: vmov.8 q0[7], r0582; CHECK-NEXT: vmov.u16 r0, q1[6]583; CHECK-NEXT: vmov.8 q0[8], r0584; CHECK-NEXT: vmov.u16 r0, q2[6]585; CHECK-NEXT: vmov.8 q0[9], r0586; CHECK-NEXT: vmov.u16 r0, q3[6]587; CHECK-NEXT: vmov.8 q0[10], r0588; CHECK-NEXT: vmov.u16 r0, q4[6]589; CHECK-NEXT: vmov.8 q0[11], r0590; CHECK-NEXT: vmov.u16 r0, q1[7]591; CHECK-NEXT: vmov.8 q0[12], r0592; CHECK-NEXT: vmov.u16 r0, q2[7]593; CHECK-NEXT: vmov.8 q0[13], r0594; CHECK-NEXT: vmov.u16 r0, q3[7]595; CHECK-NEXT: vmov.8 q0[14], r0596; CHECK-NEXT: vmov.u16 r0, q4[7]597; CHECK-NEXT: vmov.8 q0[15], r0598; CHECK-NEXT: vmov.u16 r0, q1[0]599; CHECK-NEXT: vmov.8 q5[0], r0600; CHECK-NEXT: vmov.u16 r0, q2[0]601; CHECK-NEXT: vmov.8 q5[1], r0602; CHECK-NEXT: vmov.u16 r0, q3[0]603; CHECK-NEXT: vmov.8 q5[2], r0604; CHECK-NEXT: vmov.u16 r0, q4[0]605; CHECK-NEXT: vmov.8 q5[3], r0606; CHECK-NEXT: vmov.u16 r0, q1[1]607; CHECK-NEXT: vmov.8 q5[4], r0608; CHECK-NEXT: vmov.u16 r0, q2[1]609; CHECK-NEXT: vmov.8 q5[5], r0610; CHECK-NEXT: vmov.u16 r0, q3[1]611; CHECK-NEXT: vmov.8 q5[6], r0612; CHECK-NEXT: vmov.u16 r0, q4[1]613; CHECK-NEXT: vmov.8 q5[7], r0614; CHECK-NEXT: vmov.u16 r0, q1[2]615; CHECK-NEXT: vmov.8 q5[8], r0616; CHECK-NEXT: vmov.u16 r0, q2[2]617; CHECK-NEXT: vmov.8 q5[9], r0618; CHECK-NEXT: vmov.u16 r0, q3[2]619; CHECK-NEXT: vmov.8 q5[10], r0620; CHECK-NEXT: vmov.u16 r0, q4[2]621; CHECK-NEXT: vmov.8 q5[11], r0622; CHECK-NEXT: vmov.u16 r0, q1[3]623; CHECK-NEXT: vmov.8 q5[12], r0624; CHECK-NEXT: vmov.u16 r0, q2[3]625; CHECK-NEXT: vmov.8 q5[13], r0626; CHECK-NEXT: vmov.u16 r0, q3[3]627; CHECK-NEXT: vmov.8 q5[14], r0628; CHECK-NEXT: vmov.u16 r0, q4[3]629; CHECK-NEXT: vmov.8 q5[15], r0630; CHECK-NEXT: vstrb.8 q0, [r1, #16]631; CHECK-NEXT: vstrb.8 q5, [r1]632; CHECK-NEXT: vpop {d8, d9, d10, d11}633; CHECK-NEXT: bx lr634entry:635 %l1 = load <8 x i8>, ptr %src, align 4636 %s2 = getelementptr <8 x i8>, ptr %src, i32 1637 %l2 = load <8 x i8>, ptr %s2, align 4638 %s3 = getelementptr <8 x i8>, ptr %src, i32 2639 %l3 = load <8 x i8>, ptr %s3, align 4640 %s4 = getelementptr <8 x i8>, ptr %src, i32 3641 %l4 = load <8 x i8>, ptr %s4, align 4642 %t1 = shufflevector <8 x i8> %l1, <8 x i8> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>643 %t2 = shufflevector <8 x i8> %l3, <8 x i8> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>644 %s = shufflevector <16 x i8> %t1, <16 x i8> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>645 store <32 x i8> %s, ptr %dst, align 1646 ret void647}648 649define void @vst4_v16i8(ptr %src, ptr %dst) {650; CHECK-LABEL: vst4_v16i8:651; CHECK: @ %bb.0: @ %entry652; CHECK-NEXT: vldrw.u32 q3, [r0, #48]653; CHECK-NEXT: vldrw.u32 q2, [r0, #32]654; CHECK-NEXT: vldrw.u32 q1, [r0, #16]655; CHECK-NEXT: vldrw.u32 q0, [r0]656; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r1]657; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r1]658; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r1]659; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r1]660; CHECK-NEXT: bx lr661entry:662 %l1 = load <16 x i8>, ptr %src, align 4663 %s2 = getelementptr <16 x i8>, ptr %src, i32 1664 %l2 = load <16 x i8>, ptr %s2, align 4665 %s3 = getelementptr <16 x i8>, ptr %src, i32 2666 %l3 = load <16 x i8>, ptr %s3, align 4667 %s4 = getelementptr <16 x i8>, ptr %src, i32 3668 %l4 = load <16 x i8>, ptr %s4, align 4669 %t1 = shufflevector <16 x i8> %l1, <16 x i8> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>670 %t2 = shufflevector <16 x i8> %l3, <16 x i8> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>671 %s = shufflevector <32 x i8> %t1, <32 x i8> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>672 store <64 x i8> %s, ptr %dst, align 1673 ret void674}675 676; i64677 678define void @vst4_v2i64(ptr %src, ptr %dst) {679; CHECK-LABEL: vst4_v2i64:680; CHECK: @ %bb.0: @ %entry681; CHECK-NEXT: .vsave {d8, d9, d10, d11}682; CHECK-NEXT: vpush {d8, d9, d10, d11}683; CHECK-NEXT: vldrw.u32 q0, [r0, #48]684; CHECK-NEXT: vldrw.u32 q1, [r0, #32]685; CHECK-NEXT: vldrw.u32 q2, [r0, #16]686; CHECK-NEXT: vldrw.u32 q3, [r0]687; CHECK-NEXT: vmov.f64 d9, d0688; CHECK-NEXT: vmov.f64 d8, d2689; CHECK-NEXT: vmov.f64 d11, d4690; CHECK-NEXT: vstrw.32 q4, [r1, #16]691; CHECK-NEXT: vmov.f64 d10, d6692; CHECK-NEXT: vmov.f64 d0, d3693; CHECK-NEXT: vstrw.32 q5, [r1]694; CHECK-NEXT: vmov.f64 d4, d7695; CHECK-NEXT: vstrw.32 q0, [r1, #48]696; CHECK-NEXT: vstrw.32 q2, [r1, #32]697; CHECK-NEXT: vpop {d8, d9, d10, d11}698; CHECK-NEXT: bx lr699entry:700 %l1 = load <2 x i64>, ptr %src, align 4701 %s2 = getelementptr <2 x i64>, ptr %src, i32 1702 %l2 = load <2 x i64>, ptr %s2, align 4703 %s3 = getelementptr <2 x i64>, ptr %src, i32 2704 %l3 = load <2 x i64>, ptr %s3, align 4705 %s4 = getelementptr <2 x i64>, ptr %src, i32 3706 %l4 = load <2 x i64>, ptr %s4, align 4707 %t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>708 %t2 = shufflevector <2 x i64> %l3, <2 x i64> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>709 %s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>710 store <8 x i64> %s, ptr %dst, align 8711 ret void712}713 714define void @vst4_v4i64(ptr %src, ptr %dst) {715; CHECK-LABEL: vst4_v4i64:716; CHECK: @ %bb.0: @ %entry717; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}718; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}719; CHECK-NEXT: .pad #64720; CHECK-NEXT: sub sp, #64721; CHECK-NEXT: vldrw.u32 q7, [r0, #80]722; CHECK-NEXT: vldrw.u32 q4, [r0, #32]723; CHECK-NEXT: vldrw.u32 q2, [r0]724; CHECK-NEXT: vldrw.u32 q1, [r0, #96]725; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill726; CHECK-NEXT: vmov.f64 d15, d8727; CHECK-NEXT: vldrw.u32 q6, [r0, #64]728; CHECK-NEXT: vldrw.u32 q0, [r0, #16]729; CHECK-NEXT: vldrw.u32 q3, [r0, #48]730; CHECK-NEXT: vldrw.u32 q5, [r0, #112]731; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill732; CHECK-NEXT: vmov.f64 d14, d4733; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill734; CHECK-NEXT: vmov.f64 d15, d2735; CHECK-NEXT: vmov.f64 d14, d12736; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill737; CHECK-NEXT: vmov.f64 d4, d0738; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload739; CHECK-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload740; CHECK-NEXT: vmov.f64 d8, d5741; CHECK-NEXT: vmov.f64 d2, d13742; CHECK-NEXT: vstrw.32 q4, [r1, #32]743; CHECK-NEXT: vmov.f64 d5, d6744; CHECK-NEXT: vstrw.32 q1, [r1, #48]745; CHECK-NEXT: vmov.f64 d13, d10746; CHECK-NEXT: vstrw.32 q2, [r1, #64]747; CHECK-NEXT: vmov.f64 d12, d0748; CHECK-NEXT: vmov.f64 d10, d1749; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload750; CHECK-NEXT: vstrw.32 q6, [r1, #80]751; CHECK-NEXT: vstrw.32 q0, [r1]752; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload753; CHECK-NEXT: vmov.f64 d6, d15754; CHECK-NEXT: vstrw.32 q5, [r1, #112]755; CHECK-NEXT: vstrw.32 q0, [r1, #16]756; CHECK-NEXT: vstrw.32 q3, [r1, #96]757; CHECK-NEXT: add sp, #64758; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}759; CHECK-NEXT: bx lr760entry:761 %l1 = load <4 x i64>, ptr %src, align 4762 %s2 = getelementptr <4 x i64>, ptr %src, i32 1763 %l2 = load <4 x i64>, ptr %s2, align 4764 %s3 = getelementptr <4 x i64>, ptr %src, i32 2765 %l3 = load <4 x i64>, ptr %s3, align 4766 %s4 = getelementptr <4 x i64>, ptr %src, i32 3767 %l4 = load <4 x i64>, ptr %s4, align 4768 %t1 = shufflevector <4 x i64> %l1, <4 x i64> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>769 %t2 = shufflevector <4 x i64> %l3, <4 x i64> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>770 %s = shufflevector <8 x i64> %t1, <8 x i64> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>771 store <16 x i64> %s, ptr %dst, align 8772 ret void773}774 775; f32776 777define void @vst4_v2f32(ptr %src, ptr %dst) {778; CHECK-LABEL: vst4_v2f32:779; CHECK: @ %bb.0: @ %entry780; CHECK-NEXT: vldr s0, [r0]781; CHECK-NEXT: vldr s4, [r0, #4]782; CHECK-NEXT: vldr s1, [r0, #8]783; CHECK-NEXT: vldr s5, [r0, #12]784; CHECK-NEXT: vldr s2, [r0, #16]785; CHECK-NEXT: vldr s6, [r0, #20]786; CHECK-NEXT: vldr s3, [r0, #24]787; CHECK-NEXT: vldr s7, [r0, #28]788; CHECK-NEXT: vstrw.32 q0, [r1]789; CHECK-NEXT: vstrw.32 q1, [r1, #16]790; CHECK-NEXT: bx lr791entry:792 %l1 = load <2 x float>, ptr %src, align 4793 %s2 = getelementptr <2 x float>, ptr %src, i32 1794 %l2 = load <2 x float>, ptr %s2, align 4795 %s3 = getelementptr <2 x float>, ptr %src, i32 2796 %l3 = load <2 x float>, ptr %s3, align 4797 %s4 = getelementptr <2 x float>, ptr %src, i32 3798 %l4 = load <2 x float>, ptr %s4, align 4799 %t1 = shufflevector <2 x float> %l1, <2 x float> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>800 %t2 = shufflevector <2 x float> %l3, <2 x float> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>801 %s = shufflevector <4 x float> %t1, <4 x float> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>802 store <8 x float> %s, ptr %dst, align 4803 ret void804}805 806define void @vst4_v4f32(ptr %src, ptr %dst) {807; CHECK-LABEL: vst4_v4f32:808; CHECK: @ %bb.0: @ %entry809; CHECK-NEXT: vldrw.u32 q3, [r0, #48]810; CHECK-NEXT: vldrw.u32 q2, [r0, #32]811; CHECK-NEXT: vldrw.u32 q1, [r0, #16]812; CHECK-NEXT: vldrw.u32 q0, [r0]813; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]814; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]815; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]816; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]817; CHECK-NEXT: bx lr818entry:819 %l1 = load <4 x float>, ptr %src, align 4820 %s2 = getelementptr <4 x float>, ptr %src, i32 1821 %l2 = load <4 x float>, ptr %s2, align 4822 %s3 = getelementptr <4 x float>, ptr %src, i32 2823 %l3 = load <4 x float>, ptr %s3, align 4824 %s4 = getelementptr <4 x float>, ptr %src, i32 3825 %l4 = load <4 x float>, ptr %s4, align 4826 %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>827 %t2 = shufflevector <4 x float> %l3, <4 x float> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>828 %s = shufflevector <8 x float> %t1, <8 x float> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>829 store <16 x float> %s, ptr %dst, align 4830 ret void831}832 833define void @vst4_v8f32(ptr %src, ptr %dst) {834; CHECK-LABEL: vst4_v8f32:835; CHECK: @ %bb.0: @ %entry836; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}837; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}838; CHECK-NEXT: vldrw.u32 q7, [r0, #96]839; CHECK-NEXT: vldrw.u32 q6, [r0, #64]840; CHECK-NEXT: vldrw.u32 q5, [r0, #32]841; CHECK-NEXT: vldrw.u32 q4, [r0]842; CHECK-NEXT: vldrw.u32 q3, [r0, #112]843; CHECK-NEXT: vldrw.u32 q2, [r0, #80]844; CHECK-NEXT: vldrw.u32 q1, [r0, #48]845; CHECK-NEXT: vldrw.u32 q0, [r0, #16]846; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]847; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]848; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]849; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]!850; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]851; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]852; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]853; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]854; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}855; CHECK-NEXT: bx lr856entry:857 %l1 = load <8 x float>, ptr %src, align 4858 %s2 = getelementptr <8 x float>, ptr %src, i32 1859 %l2 = load <8 x float>, ptr %s2, align 4860 %s3 = getelementptr <8 x float>, ptr %src, i32 2861 %l3 = load <8 x float>, ptr %s3, align 4862 %s4 = getelementptr <8 x float>, ptr %src, i32 3863 %l4 = load <8 x float>, ptr %s4, align 4864 %t1 = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>865 %t2 = shufflevector <8 x float> %l3, <8 x float> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>866 %s = shufflevector <16 x float> %t1, <16 x float> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>867 store <32 x float> %s, ptr %dst, align 4868 ret void869}870 871define void @vst4_v16f32(ptr %src, ptr %dst) {872; CHECK-LABEL: vst4_v16f32:873; CHECK: @ %bb.0: @ %entry874; CHECK-NEXT: .save {r4, r5}875; CHECK-NEXT: push {r4, r5}876; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}877; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}878; CHECK-NEXT: .pad #192879; CHECK-NEXT: sub sp, #192880; CHECK-NEXT: vldrw.u32 q0, [r0, #16]881; CHECK-NEXT: add r2, sp, #64882; CHECK-NEXT: vldrw.u32 q3, [r0, #208]883; CHECK-NEXT: vldrw.u32 q2, [r0, #144]884; CHECK-NEXT: vldrw.u32 q1, [r0, #80]885; CHECK-NEXT: vstmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill886; CHECK-NEXT: vldrw.u32 q0, [r0]887; CHECK-NEXT: vldrw.u32 q2, [r0, #128]888; CHECK-NEXT: vldrw.u32 q3, [r0, #192]889; CHECK-NEXT: vldrw.u32 q1, [r0, #64]890; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill891; CHECK-NEXT: vldrw.u32 q6, [r0, #176]892; CHECK-NEXT: vldrw.u32 q2, [r0, #160]893; CHECK-NEXT: vldrw.u32 q4, [r0, #48]894; CHECK-NEXT: add r2, sp, #128895; CHECK-NEXT: vldrw.u32 q7, [r0, #240]896; CHECK-NEXT: vldrw.u32 q3, [r0, #224]897; CHECK-NEXT: vldrw.u32 q1, [r0, #96]898; CHECK-NEXT: vldrw.u32 q5, [r0, #112]899; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill900; CHECK-NEXT: vmov q6, q2901; CHECK-NEXT: vmov q5, q1902; CHECK-NEXT: vmov q7, q3903; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload904; CHECK-NEXT: add r2, sp, #64905; CHECK-NEXT: vldrw.u32 q4, [r0, #32]906; CHECK-NEXT: mov r0, r1907; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]908; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]909; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]910; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]!911; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload912; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]913; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]914; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]915; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]916; CHECK-NEXT: add.w r0, r1, #192917; CHECK-NEXT: adds r1, #128918; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]919; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]920; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]921; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]922; CHECK-NEXT: add r1, sp, #128923; CHECK-NEXT: vldmia r1, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload924; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]925; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]926; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]927; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]928; CHECK-NEXT: add sp, #192929; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}930; CHECK-NEXT: pop {r4, r5}931; CHECK-NEXT: bx lr932entry:933 %l1 = load <16 x float>, ptr %src, align 4934 %s2 = getelementptr <16 x float>, ptr %src, i32 1935 %l2 = load <16 x float>, ptr %s2, align 4936 %s3 = getelementptr <16 x float>, ptr %src, i32 2937 %l3 = load <16 x float>, ptr %s3, align 4938 %s4 = getelementptr <16 x float>, ptr %src, i32 3939 %l4 = load <16 x float>, ptr %s4, align 4940 %t1 = shufflevector <16 x float> %l1, <16 x float> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>941 %t2 = shufflevector <16 x float> %l3, <16 x float> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>942 %s = shufflevector <32 x float> %t1, <32 x float> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>943 store <64 x float> %s, ptr %dst, align 4944 ret void945}946 947define void @vst4_v4f32_align1(ptr %src, ptr %dst) {948; CHECK-LABEL: vst4_v4f32_align1:949; CHECK: @ %bb.0: @ %entry950; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}951; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}952; CHECK-NEXT: vldrw.u32 q1, [r0, #48]953; CHECK-NEXT: vldrw.u32 q0, [r0, #32]954; CHECK-NEXT: vldrw.u32 q2, [r0, #16]955; CHECK-NEXT: vldrw.u32 q4, [r0]956; CHECK-NEXT: vmov.f32 s14, s1957; CHECK-NEXT: vmov.f32 s22, s0958; CHECK-NEXT: vmov.f32 s26, s3959; CHECK-NEXT: vmov.f32 s12, s17960; CHECK-NEXT: vmov.f32 s13, s9961; CHECK-NEXT: vmov.f32 s15, s5962; CHECK-NEXT: vmov.f32 s20, s16963; CHECK-NEXT: vstrb.8 q3, [r1, #16]964; CHECK-NEXT: vmov.f32 s21, s8965; CHECK-NEXT: vmov.f32 s23, s4966; CHECK-NEXT: vmov.f32 s24, s19967; CHECK-NEXT: vstrb.8 q5, [r1]968; CHECK-NEXT: vmov.f32 s25, s11969; CHECK-NEXT: vmov.f32 s27, s7970; CHECK-NEXT: vmov.f32 s0, s18971; CHECK-NEXT: vstrb.8 q6, [r1, #48]972; CHECK-NEXT: vmov.f32 s1, s10973; CHECK-NEXT: vmov.f32 s3, s6974; CHECK-NEXT: vstrb.8 q0, [r1, #32]975; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}976; CHECK-NEXT: bx lr977entry:978 %l1 = load <4 x float>, ptr %src, align 4979 %s2 = getelementptr <4 x float>, ptr %src, i32 1980 %l2 = load <4 x float>, ptr %s2, align 4981 %s3 = getelementptr <4 x float>, ptr %src, i32 2982 %l3 = load <4 x float>, ptr %s3, align 4983 %s4 = getelementptr <4 x float>, ptr %src, i32 3984 %l4 = load <4 x float>, ptr %s4, align 4985 %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>986 %t2 = shufflevector <4 x float> %l3, <4 x float> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>987 %s = shufflevector <8 x float> %t1, <8 x float> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>988 store <16 x float> %s, ptr %dst, align 1989 ret void990}991 992; f16993 994define void @vst4_v2f16(ptr %src, ptr %dst) {995; CHECK-LABEL: vst4_v2f16:996; CHECK: @ %bb.0: @ %entry997; CHECK-NEXT: .vsave {d8, d9}998; CHECK-NEXT: vpush {d8, d9}999; CHECK-NEXT: ldm.w r0, {r2, r3, r12}1000; CHECK-NEXT: vmov.32 q3[0], r121001; CHECK-NEXT: vmov q4, q31002; CHECK-NEXT: vmov.f32 s1, s121003; CHECK-NEXT: ldr r0, [r0, #12]1004; CHECK-NEXT: vmovx.f16 s3, s121005; CHECK-NEXT: vmov.32 q1[0], r21006; CHECK-NEXT: vmov q2, q11007; CHECK-NEXT: vmov.32 q4[1], r01008; CHECK-NEXT: vmov.32 q2[1], r31009; CHECK-NEXT: vmov.f32 s0, s41010; CHECK-NEXT: vmovx.f16 s2, s41011; CHECK-NEXT: vmovx.f16 s6, s91012; CHECK-NEXT: vmovx.f16 s4, s171013; CHECK-NEXT: vins.f16 s0, s91014; CHECK-NEXT: vins.f16 s1, s171015; CHECK-NEXT: vins.f16 s2, s61016; CHECK-NEXT: vins.f16 s3, s41017; CHECK-NEXT: vstrh.16 q0, [r1]1018; CHECK-NEXT: vpop {d8, d9}1019; CHECK-NEXT: bx lr1020entry:1021 %l1 = load <2 x half>, ptr %src, align 41022 %s2 = getelementptr <2 x half>, ptr %src, i32 11023 %l2 = load <2 x half>, ptr %s2, align 41024 %s3 = getelementptr <2 x half>, ptr %src, i32 21025 %l3 = load <2 x half>, ptr %s3, align 41026 %s4 = getelementptr <2 x half>, ptr %src, i32 31027 %l4 = load <2 x half>, ptr %s4, align 41028 %t1 = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1029 %t2 = shufflevector <2 x half> %l3, <2 x half> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1030 %s = shufflevector <4 x half> %t1, <4 x half> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>1031 store <8 x half> %s, ptr %dst, align 21032 ret void1033}1034 1035define void @vst4_v4f16(ptr %src, ptr %dst) {1036; CHECK-LABEL: vst4_v4f16:1037; CHECK: @ %bb.0: @ %entry1038; CHECK-NEXT: .save {r4, r5, r6, lr}1039; CHECK-NEXT: push {r4, r5, r6, lr}1040; CHECK-NEXT: add.w r6, r0, #161041; CHECK-NEXT: ldrd lr, r12, [r0]1042; CHECK-NEXT: ldrd r3, r2, [r0, #8]1043; CHECK-NEXT: ldm r6, {r4, r5, r6}1044; CHECK-NEXT: vmov q1[2], q1[0], lr, r31045; CHECK-NEXT: ldr r0, [r0, #28]1046; CHECK-NEXT: vmov q1[3], q1[1], r12, r21047; CHECK-NEXT: vmov q0[2], q0[0], r4, r61048; CHECK-NEXT: vmovx.f16 s10, s51049; CHECK-NEXT: vmov q0[3], q0[1], r5, r01050; CHECK-NEXT: vins.f16 s5, s71051; CHECK-NEXT: vmovx.f16 s12, s01052; CHECK-NEXT: vins.f16 s0, s21053; CHECK-NEXT: vmovx.f16 s2, s21054; CHECK-NEXT: vmovx.f16 s11, s11055; CHECK-NEXT: vins.f16 s12, s21056; CHECK-NEXT: vmovx.f16 s2, s31057; CHECK-NEXT: vins.f16 s11, s21058; CHECK-NEXT: vmov.f32 s2, s61059; CHECK-NEXT: vmovx.f16 s6, s41060; CHECK-NEXT: vins.f16 s4, s21061; CHECK-NEXT: vmovx.f16 s2, s21062; CHECK-NEXT: vins.f16 s1, s31063; CHECK-NEXT: vins.f16 s6, s21064; CHECK-NEXT: vmovx.f16 s2, s71065; CHECK-NEXT: vmov.f32 s8, s51066; CHECK-NEXT: vins.f16 s10, s21067; CHECK-NEXT: vmov.f32 s9, s11068; CHECK-NEXT: vmov.f32 s5, s01069; CHECK-NEXT: vstrh.16 q2, [r1, #16]1070; CHECK-NEXT: vmov.f32 s7, s121071; CHECK-NEXT: vstrh.16 q1, [r1]1072; CHECK-NEXT: pop {r4, r5, r6, pc}1073entry:1074 %l1 = load <4 x half>, ptr %src, align 41075 %s2 = getelementptr <4 x half>, ptr %src, i32 11076 %l2 = load <4 x half>, ptr %s2, align 41077 %s3 = getelementptr <4 x half>, ptr %src, i32 21078 %l3 = load <4 x half>, ptr %s3, align 41079 %s4 = getelementptr <4 x half>, ptr %src, i32 31080 %l4 = load <4 x half>, ptr %s4, align 41081 %t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1082 %t2 = shufflevector <4 x half> %l3, <4 x half> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1083 %s = shufflevector <8 x half> %t1, <8 x half> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>1084 store <16 x half> %s, ptr %dst, align 21085 ret void1086}1087 1088define void @vst4_v8f16(ptr %src, ptr %dst) {1089; CHECK-LABEL: vst4_v8f16:1090; CHECK: @ %bb.0: @ %entry1091; CHECK-NEXT: vldrw.u32 q3, [r0, #48]1092; CHECK-NEXT: vldrw.u32 q2, [r0, #32]1093; CHECK-NEXT: vldrw.u32 q1, [r0, #16]1094; CHECK-NEXT: vldrw.u32 q0, [r0]1095; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]1096; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]1097; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]1098; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]1099; CHECK-NEXT: bx lr1100entry:1101 %l1 = load <8 x half>, ptr %src, align 41102 %s2 = getelementptr <8 x half>, ptr %src, i32 11103 %l2 = load <8 x half>, ptr %s2, align 41104 %s3 = getelementptr <8 x half>, ptr %src, i32 21105 %l3 = load <8 x half>, ptr %s3, align 41106 %s4 = getelementptr <8 x half>, ptr %src, i32 31107 %l4 = load <8 x half>, ptr %s4, align 41108 %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1109 %t2 = shufflevector <8 x half> %l3, <8 x half> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1110 %s = shufflevector <16 x half> %t1, <16 x half> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>1111 store <32 x half> %s, ptr %dst, align 21112 ret void1113}1114 1115define void @vst4_v16f16(ptr %src, ptr %dst) {1116; CHECK-LABEL: vst4_v16f16:1117; CHECK: @ %bb.0: @ %entry1118; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1119; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}1120; CHECK-NEXT: vldrw.u32 q7, [r0, #96]1121; CHECK-NEXT: vldrw.u32 q6, [r0, #64]1122; CHECK-NEXT: vldrw.u32 q5, [r0, #32]1123; CHECK-NEXT: vldrw.u32 q4, [r0]1124; CHECK-NEXT: vldrw.u32 q3, [r0, #112]1125; CHECK-NEXT: vldrw.u32 q2, [r0, #80]1126; CHECK-NEXT: vldrw.u32 q1, [r0, #48]1127; CHECK-NEXT: vldrw.u32 q0, [r0, #16]1128; CHECK-NEXT: vst40.16 {q4, q5, q6, q7}, [r1]1129; CHECK-NEXT: vst41.16 {q4, q5, q6, q7}, [r1]1130; CHECK-NEXT: vst42.16 {q4, q5, q6, q7}, [r1]1131; CHECK-NEXT: vst43.16 {q4, q5, q6, q7}, [r1]!1132; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]1133; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]1134; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]1135; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]1136; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1137; CHECK-NEXT: bx lr1138entry:1139 %l1 = load <16 x half>, ptr %src, align 41140 %s2 = getelementptr <16 x half>, ptr %src, i32 11141 %l2 = load <16 x half>, ptr %s2, align 41142 %s3 = getelementptr <16 x half>, ptr %src, i32 21143 %l3 = load <16 x half>, ptr %s3, align 41144 %s4 = getelementptr <16 x half>, ptr %src, i32 31145 %l4 = load <16 x half>, ptr %s4, align 41146 %t1 = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1147 %t2 = shufflevector <16 x half> %l3, <16 x half> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1148 %s = shufflevector <32 x half> %t1, <32 x half> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>1149 store <64 x half> %s, ptr %dst, align 21150 ret void1151}1152 1153define void @vst4_v8f16_align1(ptr %src, ptr %dst) {1154; CHECK-LABEL: vst4_v8f16_align1:1155; CHECK: @ %bb.0: @ %entry1156; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}1157; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}1158; CHECK-NEXT: vldrw.u32 q1, [r0, #32]1159; CHECK-NEXT: vldrw.u32 q4, [r0, #48]1160; CHECK-NEXT: vldrw.u32 q2, [r0]1161; CHECK-NEXT: vldrw.u32 q5, [r0, #16]1162; CHECK-NEXT: vmovx.f16 s3, s51163; CHECK-NEXT: vmovx.f16 s0, s171164; CHECK-NEXT: vins.f16 s3, s01165; CHECK-NEXT: vmovx.f16 s2, s91166; CHECK-NEXT: vmovx.f16 s0, s211167; CHECK-NEXT: vmovx.f16 s15, s41168; CHECK-NEXT: vins.f16 s2, s01169; CHECK-NEXT: vmovx.f16 s0, s161170; CHECK-NEXT: vins.f16 s15, s01171; CHECK-NEXT: vmovx.f16 s14, s81172; CHECK-NEXT: vmovx.f16 s0, s201173; CHECK-NEXT: vmovx.f16 s27, s71174; CHECK-NEXT: vins.f16 s14, s01175; CHECK-NEXT: vmovx.f16 s0, s191176; CHECK-NEXT: vins.f16 s27, s01177; CHECK-NEXT: vmovx.f16 s26, s111178; CHECK-NEXT: vmovx.f16 s0, s231179; CHECK-NEXT: vins.f16 s7, s191180; CHECK-NEXT: vins.f16 s26, s01181; CHECK-NEXT: vmovx.f16 s19, s61182; CHECK-NEXT: vmovx.f16 s0, s181183; CHECK-NEXT: vins.f16 s5, s171184; CHECK-NEXT: vins.f16 s6, s181185; CHECK-NEXT: vins.f16 s4, s161186; CHECK-NEXT: vins.f16 s8, s201187; CHECK-NEXT: vins.f16 s11, s231188; CHECK-NEXT: vins.f16 s19, s01189; CHECK-NEXT: vmovx.f16 s18, s101190; CHECK-NEXT: vins.f16 s10, s221191; CHECK-NEXT: vmovx.f16 s0, s221192; CHECK-NEXT: vins.f16 s9, s211193; CHECK-NEXT: vins.f16 s18, s01194; CHECK-NEXT: vmov.f32 s0, s91195; CHECK-NEXT: vmov.f32 s1, s51196; CHECK-NEXT: vmov.f32 s13, s41197; CHECK-NEXT: vstrb.8 q0, [r1, #16]1198; CHECK-NEXT: vmov.f32 s12, s81199; CHECK-NEXT: vmov.f32 s25, s71200; CHECK-NEXT: vstrb.8 q3, [r1]1201; CHECK-NEXT: vmov.f32 s24, s111202; CHECK-NEXT: vmov.f32 s17, s61203; CHECK-NEXT: vstrb.8 q6, [r1, #48]1204; CHECK-NEXT: vmov.f32 s16, s101205; CHECK-NEXT: vstrb.8 q4, [r1, #32]1206; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}1207; CHECK-NEXT: bx lr1208entry:1209 %l1 = load <8 x half>, ptr %src, align 41210 %s2 = getelementptr <8 x half>, ptr %src, i32 11211 %l2 = load <8 x half>, ptr %s2, align 41212 %s3 = getelementptr <8 x half>, ptr %src, i32 21213 %l3 = load <8 x half>, ptr %s3, align 41214 %s4 = getelementptr <8 x half>, ptr %src, i32 31215 %l4 = load <8 x half>, ptr %s4, align 41216 %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1217 %t2 = shufflevector <8 x half> %l3, <8 x half> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1218 %s = shufflevector <16 x half> %t1, <16 x half> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>1219 store <32 x half> %s, ptr %dst, align 11220 ret void1221}1222 1223; f641224 1225define void @vst4_v2f64(ptr %src, ptr %dst) {1226; CHECK-LABEL: vst4_v2f64:1227; CHECK: @ %bb.0: @ %entry1228; CHECK-NEXT: .vsave {d8, d9, d10, d11}1229; CHECK-NEXT: vpush {d8, d9, d10, d11}1230; CHECK-NEXT: vldrw.u32 q0, [r0, #48]1231; CHECK-NEXT: vldrw.u32 q1, [r0, #32]1232; CHECK-NEXT: vldrw.u32 q2, [r0, #16]1233; CHECK-NEXT: vldrw.u32 q3, [r0]1234; CHECK-NEXT: vmov.f64 d9, d01235; CHECK-NEXT: vmov.f64 d8, d21236; CHECK-NEXT: vmov.f64 d11, d41237; CHECK-NEXT: vstrw.32 q4, [r1, #16]1238; CHECK-NEXT: vmov.f64 d10, d61239; CHECK-NEXT: vmov.f64 d0, d31240; CHECK-NEXT: vstrw.32 q5, [r1]1241; CHECK-NEXT: vmov.f64 d4, d71242; CHECK-NEXT: vstrw.32 q0, [r1, #48]1243; CHECK-NEXT: vstrw.32 q2, [r1, #32]1244; CHECK-NEXT: vpop {d8, d9, d10, d11}1245; CHECK-NEXT: bx lr1246entry:1247 %l1 = load <2 x double>, ptr %src, align 41248 %s2 = getelementptr <2 x double>, ptr %src, i32 11249 %l2 = load <2 x double>, ptr %s2, align 41250 %s3 = getelementptr <2 x double>, ptr %src, i32 21251 %l3 = load <2 x double>, ptr %s3, align 41252 %s4 = getelementptr <2 x double>, ptr %src, i32 31253 %l4 = load <2 x double>, ptr %s4, align 41254 %t1 = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1255 %t2 = shufflevector <2 x double> %l3, <2 x double> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1256 %s = shufflevector <4 x double> %t1, <4 x double> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>1257 store <8 x double> %s, ptr %dst, align 81258 ret void1259}1260 1261define void @vst4_v4f64(ptr %src, ptr %dst) {1262; CHECK-LABEL: vst4_v4f64:1263; CHECK: @ %bb.0: @ %entry1264; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1265; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}1266; CHECK-NEXT: .pad #641267; CHECK-NEXT: sub sp, #641268; CHECK-NEXT: vldrw.u32 q7, [r0, #80]1269; CHECK-NEXT: vldrw.u32 q4, [r0, #32]1270; CHECK-NEXT: vldrw.u32 q2, [r0]1271; CHECK-NEXT: vldrw.u32 q1, [r0, #96]1272; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill1273; CHECK-NEXT: vmov.f64 d15, d81274; CHECK-NEXT: vldrw.u32 q6, [r0, #64]1275; CHECK-NEXT: vldrw.u32 q0, [r0, #16]1276; CHECK-NEXT: vldrw.u32 q3, [r0, #48]1277; CHECK-NEXT: vldrw.u32 q5, [r0, #112]1278; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill1279; CHECK-NEXT: vmov.f64 d14, d41280; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill1281; CHECK-NEXT: vmov.f64 d15, d21282; CHECK-NEXT: vmov.f64 d14, d121283; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill1284; CHECK-NEXT: vmov.f64 d4, d01285; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload1286; CHECK-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload1287; CHECK-NEXT: vmov.f64 d8, d51288; CHECK-NEXT: vmov.f64 d2, d131289; CHECK-NEXT: vstrw.32 q4, [r1, #32]1290; CHECK-NEXT: vmov.f64 d5, d61291; CHECK-NEXT: vstrw.32 q1, [r1, #48]1292; CHECK-NEXT: vmov.f64 d13, d101293; CHECK-NEXT: vstrw.32 q2, [r1, #64]1294; CHECK-NEXT: vmov.f64 d12, d01295; CHECK-NEXT: vmov.f64 d10, d11296; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload1297; CHECK-NEXT: vstrw.32 q6, [r1, #80]1298; CHECK-NEXT: vstrw.32 q0, [r1]1299; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload1300; CHECK-NEXT: vmov.f64 d6, d151301; CHECK-NEXT: vstrw.32 q5, [r1, #112]1302; CHECK-NEXT: vstrw.32 q0, [r1, #16]1303; CHECK-NEXT: vstrw.32 q3, [r1, #96]1304; CHECK-NEXT: add sp, #641305; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1306; CHECK-NEXT: bx lr1307entry:1308 %l1 = load <4 x double>, ptr %src, align 41309 %s2 = getelementptr <4 x double>, ptr %src, i32 11310 %l2 = load <4 x double>, ptr %s2, align 41311 %s3 = getelementptr <4 x double>, ptr %src, i32 21312 %l3 = load <4 x double>, ptr %s3, align 41313 %s4 = getelementptr <4 x double>, ptr %src, i32 31314 %l4 = load <4 x double>, ptr %s4, align 41315 %t1 = shufflevector <4 x double> %l1, <4 x double> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1316 %t2 = shufflevector <4 x double> %l3, <4 x double> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1317 %s = shufflevector <8 x double> %t1, <8 x double> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>1318 store <16 x double> %s, ptr %dst, align 81319 ret void1320}1321