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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: vsubqr_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vsub.i32 q0, q0, r08; CHECK-NEXT: bx lr9entry:10 %i = insertelement <4 x i32> undef, i32 %src2, i32 011 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer12 %c = sub <4 x i32> %src, %sp13 ret <4 x i32> %c14}15 16define arm_aapcs_vfpcc <8 x i16> @vsubqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {17; CHECK-LABEL: vsubqr_v8i16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vsub.i16 q0, q0, r020; CHECK-NEXT: bx lr21entry:22 %i = insertelement <8 x i16> undef, i16 %src2, i32 023 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer24 %c = sub <8 x i16> %src, %sp25 ret <8 x i16> %c26}27 28define arm_aapcs_vfpcc <16 x i8> @vsubqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {29; CHECK-LABEL: vsubqr_v16i8:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vsub.i8 q0, q0, r032; CHECK-NEXT: bx lr33entry:34 %i = insertelement <16 x i8> undef, i8 %src2, i32 035 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer36 %c = sub <16 x i8> %src, %sp37 ret <16 x i8> %c38}39 40define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32_2(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {41; CHECK-LABEL: vsubqr_v4i32_2:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vdup.32 q1, r044; CHECK-NEXT: vsub.i32 q0, q1, q045; CHECK-NEXT: bx lr46entry:47 %i = insertelement <4 x i32> undef, i32 %src2, i32 048 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer49 %c = sub <4 x i32> %sp, %src50 ret <4 x i32> %c51}52 53define arm_aapcs_vfpcc <8 x i16> @vsubqr_v8i16_2(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {54; CHECK-LABEL: vsubqr_v8i16_2:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vdup.16 q1, r057; CHECK-NEXT: vsub.i16 q0, q1, q058; CHECK-NEXT: bx lr59entry:60 %i = insertelement <8 x i16> undef, i16 %src2, i32 061 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer62 %c = sub <8 x i16> %sp, %src63 ret <8 x i16> %c64}65 66define arm_aapcs_vfpcc <16 x i8> @vsubqr_v16i8_2(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {67; CHECK-LABEL: vsubqr_v16i8_2:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: vdup.8 q1, r070; CHECK-NEXT: vsub.i8 q0, q1, q071; CHECK-NEXT: bx lr72entry:73 %i = insertelement <16 x i8> undef, i8 %src2, i32 074 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer75 %c = sub <16 x i8> %sp, %src76 ret <16 x i8> %c77}78