102 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <4 x float> @foo_v4i16(ptr nocapture readonly %pSrc, <4 x i16> %a) {5; CHECK-LABEL: foo_v4i16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmovlb.s16 q0, q08; CHECK-NEXT: vpt.s32 lt, q0, zr9; CHECK-NEXT: vldrht.u32 q0, [r0]10; CHECK-NEXT: vcvt.f32.u32 q0, q011; CHECK-NEXT: bx lr12entry:13 %active.lane.mask = icmp slt <4 x i16> %a, zeroinitializer14 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %pSrc, i32 2, <4 x i1> %active.lane.mask, <4 x i16> undef)15 %0 = uitofp <4 x i16> %wide.masked.load to <4 x float>16 ret <4 x float> %017}18 19define arm_aapcs_vfpcc <8 x half> @foo_v8i8(ptr nocapture readonly %pSrc, i32 %blockSize, <8 x i8> %a) {20; CHECK-LABEL: foo_v8i8:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vmovlb.s8 q0, q023; CHECK-NEXT: vpt.s16 lt, q0, zr24; CHECK-NEXT: vldrbt.u16 q0, [r0]25; CHECK-NEXT: vcvt.f16.u16 q0, q026; CHECK-NEXT: bx lr27entry:28 %active.lane.mask = icmp slt <8 x i8> %a, zeroinitializer29 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %pSrc, i32 1, <8 x i1> %active.lane.mask, <8 x i8> undef)30 %0 = uitofp <8 x i8> %wide.masked.load to <8 x half>31 ret <8 x half> %032}33 34define arm_aapcs_vfpcc <4 x float> @foo_v4i8(ptr nocapture readonly %pSrc, i32 %blockSize, <4 x i8> %a) {35; CHECK-LABEL: foo_v4i8:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vmovlb.s8 q0, q038; CHECK-NEXT: vmovlb.s16 q0, q039; CHECK-NEXT: vpt.s32 lt, q0, zr40; CHECK-NEXT: vldrbt.u32 q0, [r0]41; CHECK-NEXT: vcvt.f32.u32 q0, q042; CHECK-NEXT: bx lr43entry:44 %active.lane.mask = icmp slt <4 x i8> %a, zeroinitializer45 %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %pSrc, i32 1, <4 x i1> %active.lane.mask, <4 x i8> undef)46 %0 = uitofp <4 x i8> %wide.masked.load to <4 x float>47 ret <4 x float> %048}49 50define arm_aapcs_vfpcc <4 x double> @foo_v4i32(ptr nocapture readonly %pSrc, i32 %blockSize, <4 x i32> %a) {51; CHECK-LABEL: foo_v4i32:52; CHECK: @ %bb.0: @ %entry53; CHECK-NEXT: .save {r4, r5, r7, lr}54; CHECK-NEXT: push {r4, r5, r7, lr}55; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}56; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}57; CHECK-NEXT: vmov.i64 q5, #0xffffffff58; CHECK-NEXT: vpt.s32 lt, q0, zr59; CHECK-NEXT: vldrwt.u32 q4, [r0]60; CHECK-NEXT: vmov.f32 s0, s1661; CHECK-NEXT: vmov.f32 s2, s1762; CHECK-NEXT: vand q6, q0, q563; CHECK-NEXT: vmov r0, r1, d1364; CHECK-NEXT: bl __aeabi_ul2d65; CHECK-NEXT: vmov r2, r3, d1266; CHECK-NEXT: vmov.f32 s0, s1867; CHECK-NEXT: vmov.f32 s2, s1968; CHECK-NEXT: vmov d9, r0, r169; CHECK-NEXT: vand q5, q0, q570; CHECK-NEXT: vmov r4, r5, d1171; CHECK-NEXT: mov r0, r272; CHECK-NEXT: mov r1, r373; CHECK-NEXT: bl __aeabi_ul2d74; CHECK-NEXT: vmov d8, r0, r175; CHECK-NEXT: mov r0, r476; CHECK-NEXT: mov r1, r577; CHECK-NEXT: bl __aeabi_ul2d78; CHECK-NEXT: vmov r2, r3, d1079; CHECK-NEXT: vmov d11, r0, r180; CHECK-NEXT: mov r0, r281; CHECK-NEXT: mov r1, r382; CHECK-NEXT: bl __aeabi_ul2d83; CHECK-NEXT: vmov d10, r0, r184; CHECK-NEXT: vmov q0, q485; CHECK-NEXT: vmov q1, q586; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}87; CHECK-NEXT: pop {r4, r5, r7, pc}88entry:89 %active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer90 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)91 %0 = uitofp <4 x i32> %wide.masked.load to <4 x double>92 ret <4 x double> %093}94 95declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)96 97declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>)98 99declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32 immarg, <4 x i1>, <4 x i8>)100 101declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)102