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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mattr=+mve.fp,+fp64 -verify-machineinstrs < %s | FileCheck %s3 4; Check that peephole-opt doesn't introduce an invalid subregister use5 6target triple = "thumbv8.1m.main-none-none-eabi"7 8define <4 x float> @reg_sequence_subreg_compose_failure(<4 x float> %a, <2 x float> %b) {9; CHECK-LABEL: reg_sequence_subreg_compose_failure:10; CHECK: @ %bb.0: @ %entry11; CHECK-NEXT: vmov d0, r0, r112; CHECK-NEXT: mov r0, sp13; CHECK-NEXT: vmov d1, r2, r314; CHECK-NEXT: vldrw.u32 q1, [r0]15; CHECK-NEXT: vldr s0, .LCPI0_016; CHECK-NEXT: vmov.f32 s8, s117; CHECK-NEXT: vmov.f32 s9, s318; CHECK-NEXT: vmul.f32 q1, q2, q119; CHECK-NEXT: vmov.f32 s2, s020; CHECK-NEXT: vmov.f32 s1, s421; CHECK-NEXT: vmov.f32 s3, s522; CHECK-NEXT: vmov r0, r1, d023; CHECK-NEXT: vmov r2, r3, d124; CHECK-NEXT: bx lr25; CHECK-NEXT: .p2align 226; CHECK-NEXT: @ %bb.1:27; CHECK-NEXT: .LCPI0_0:28; CHECK-NEXT: .long 0x00000000 @ float 029entry:30 %a.imag = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>31 %mul = fmul <2 x float> %a.imag, %b32 %interleaved.vec = shufflevector <2 x float> zeroinitializer, <2 x float> %mul, <4 x i32> <i32 0, i32 2, i32 1, i32 3>33 ret <4 x float> %interleaved.vec34}35