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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -run-pass=pipeliner --pipeliner-force-issue-width=10 -o - %s | FileCheck %s --check-prefix=CHECK3 4--- |5 define hidden float @dot(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %sz) local_unnamed_addr #0 {6 entry:7 %cmp8 = icmp sgt i32 %sz, 08 br i1 %cmp8, label %for.body.preheader, label %for.end9 10 for.body.preheader: ; preds = %entry11 %scevgep = getelementptr float, ptr %b, i32 -112 %scevgep4 = getelementptr float, ptr %a, i32 -113 br label %for.body14 15 for.body: ; preds = %for.body.preheader, %for.body16 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]17 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]18 %lsr.iv = phi i32 [ %sz, %for.body.preheader ], [ %lsr.iv.next, %for.body ]19 %sum.010 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]20 %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 121 %0 = load float, ptr %scevgep7, align 422 %scevgep3 = getelementptr float, ptr %lsr.iv1, i32 123 %1 = load float, ptr %scevgep3, align 424 %mul = fmul fast float %1, %025 %add = fadd fast float %mul, %sum.01026 %lsr.iv.next = add i32 %lsr.iv, -127 %scevgep2 = getelementptr float, ptr %lsr.iv1, i32 128 %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 129 %exitcond.not = icmp ne i32 %lsr.iv.next, 030 br i1 %exitcond.not, label %for.body, label %for.end, !llvm.loop !031 32 for.end: ; preds = %for.body, %entry33 %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]34 ret float %sum.0.lcssa35 }36 37 !0 = distinct !{!0, !1, !2, !3}38 !1 = !{!"llvm.loop.mustprogress"}39 !2 = !{!"llvm.loop.unroll.disable"}40 !3 = !{!"llvm.loop.pipeline.initiationinterval", i32 3}41 42...43---44name: dot45alignment: 246tracksRegLiveness: true47registers:48 - { id: 25, class: spr, preferred-register: '' }49constants:50 - id: 051 value: 'float 0.000000e+00'52 alignment: 453 isTargetSpecific: false54body: |55 ; CHECK-LABEL: name: dot56 ; CHECK: bb.0.entry:57 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000)58 ; CHECK-NEXT: liveins: $r0, $r1, $r259 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r261 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r162 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r063 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr64 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr65 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: bb.1:67 ; CHECK-NEXT: successors: %bb.4(0x80000000)68 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)70 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg71 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: bb.2.for.body.preheader:73 ; CHECK-NEXT: successors: %bb.5(0x80000000)74 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY1]], 4, 14 /* CC::al */, $noreg, $noreg76 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnopc = COPY [[t2SUBri]]77 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[COPY2]], 4, 14 /* CC::al */, $noreg, $noreg78 ; CHECK-NEXT: [[VLDRS1:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)79 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprnopc = COPY [[t2SUBri1]]80 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: bb.5.for.body:82 ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.9(0x40000000)83 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY4]], 4, 14 /* CC::al */, $noreg, $noreg85 ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)86 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg87 ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)88 ; CHECK-NEXT: INLINEASM &nop, 0 /* attdialect */, 196618 /* regdef:SPR */, def %30, 2147483657 /* reguse tiedto:$0 */, [[VLDRS2]](tied-def 3)89 ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr90 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]]91 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprnopc = COPY [[t2ADDri1]]92 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gprnopc = COPY [[t2ADDri]]93 ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr94 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg95 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: bb.6.for.body:97 ; CHECK-NEXT: successors: %bb.7(0x80000000), %bb.8(0x00000000)98 ; CHECK-NEXT: {{ $}}99 ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], %30, 14 /* CC::al */, $noreg, implicit $fpscr_rm100 ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[COPY7]], 4, 14 /* CC::al */, $noreg, $noreg101 ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4)102 ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg103 ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[COPY6]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4)104 ; CHECK-NEXT: INLINEASM &nop, 0 /* attdialect */, 196618 /* regdef:SPR */, def %40, 2147483657 /* reguse tiedto:$0 */, [[VLDRS4]](tied-def 3)105 ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr106 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2SUBri3]]107 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2ADDri3]]108 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr = COPY [[t2ADDri2]]109 ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr110 ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: bb.7.for.body:113 ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.7(0x7c000000)114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY10]], %bb.6, %52, %bb.7116 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY9]], %bb.6, %53, %bb.7117 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, %54, %bb.7118 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %51, %bb.7119 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VLDRS5]], %bb.6, %47, %bb.7120 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI %40, %bb.6, %55, %bb.7121 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %45, %bb.7122 ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI4]], [[PHI5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm123 ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr124 ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4)125 ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4)126 ; CHECK-NEXT: [[t2ADDri4:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg127 ; CHECK-NEXT: [[t2ADDri5:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg128 ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm129 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]]130 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]]131 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]]132 ; CHECK-NEXT: INLINEASM &nop, 0 /* attdialect */, 196618 /* regdef:SPR */, def %55, 2147483657 /* reguse tiedto:$0 */, [[VLDRS7]](tied-def 3)133 ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr134 ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: bb.8:137 ; CHECK-NEXT: successors: %bb.9(0x80000000)138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7140 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS5]], %bb.6, [[VLDRS6]], %bb.7141 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI %40, %bb.6, %55, %bb.7142 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7143 ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: bb.9:146 ; CHECK-NEXT: successors: %bb.4(0x80000000)147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8149 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS3]], %bb.5, [[PHI8]], %bb.8150 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:spr = PHI %30, %bb.5, [[PHI9]], %bb.8151 ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI12]], [[PHI13]], 14 /* CC::al */, $noreg, implicit $fpscr_rm152 ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI11]], 14 /* CC::al */, $noreg, implicit $fpscr_rm153 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: bb.4.for.end:156 ; CHECK-NEXT: [[PHI14:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS2]], %bb.9157 ; CHECK-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[PHI14]], 14 /* CC::al */, $noreg158 ; CHECK-NEXT: $r0 = COPY [[VMOVRS]]159 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0160 bb.0.entry:161 successors: %bb.1(0x50000000), %bb.4(0x30000000)162 liveins: $r0, $r1, $r2163 164 %13:gprnopc = COPY $r2165 %12:gprnopc = COPY $r1166 %11:gprnopc = COPY $r0167 t2CMPri %13, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr168 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr169 170 bb.4:171 successors: %bb.3(0x80000000)172 173 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)174 t2B %bb.3, 14 /* CC::al */, $noreg175 176 bb.1.for.body.preheader:177 successors: %bb.2(0x80000000)178 179 %16:rgpr = t2SUBri %12, 4, 14 /* CC::al */, $noreg, $noreg180 %0:gpr = COPY %16181 %17:rgpr = t2SUBri %11, 4, 14 /* CC::al */, $noreg, $noreg182 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)183 %1:gpr = COPY %17184 185 bb.2.for.body:186 successors: %bb.3(0x04000000), %bb.2(0x7c000000)187 188 %2:gprnopc = PHI %1, %bb.1, %9, %bb.2189 %3:gprnopc = PHI %0, %bb.1, %8, %bb.2190 %4:gprnopc = PHI %13, %bb.1, %7, %bb.2191 %5:spr = PHI %15, %bb.1, %6, %bb.2192 %18:rgpr = t2ADDri %2, 4, 14 /* CC::al */, $noreg, $noreg193 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)194 %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg195 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)196 INLINEASM &nop, 0 /* attdialect */, 196618 /* regdef:SPR */, def %25, 2147483657 /* reguse tiedto:$0 */, %19(tied-def 3)197 %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %25, 14 /* CC::al */, $noreg, implicit $fpscr_rm198 %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm199 %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr200 %7:gpr = COPY %23201 %8:gpr = COPY %20202 %9:gpr = COPY %18203 t2Bcc %bb.3, 0 /* CC::eq */, $cpsr204 t2B %bb.2, 14 /* CC::al */, $noreg205 206 bb.3.for.end:207 %10:spr = PHI %14, %bb.4, %6, %bb.2208 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg209 $r0 = COPY %24210 tBX_RET 14 /* CC::al */, $noreg, implicit $r0211 212...213