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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv7-none-eabi -mcpu=cortex-m7 -O3 -run-pass=tbaa,pipeliner %s -o - | FileCheck %s3 4--- |5 ; ModuleID = 'test.ll'6 source_filename = "test.ll"7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"8 target triple = "thumbv7m-none-unknown-eabi"9 10 %struct.bar = type { i16, i16, i16, i16, i16, i16, i16, i16 }11 12 @bar = external local_unnamed_addr global [0 x %struct.bar], align 213 14 define i32 @foo() local_unnamed_addr #0 {15 entry:16 br label %do.body17 18 do.body: ; preds = %do.body, %entry19 %lsr.iv = phi ptr [ %uglygep, %do.body ], [ getelementptr (i8, ptr @bar, i32 -16), %entry ]20 %count.0 = phi i32 [ 0, %entry ], [ %count.4, %do.body ]21 %uglygep1 = getelementptr i8, ptr %lsr.iv, i32 1622 %0 = load i16, ptr %uglygep1, align 2, !tbaa !023 %conv = sext i16 %0 to i3224 %uglygep2 = getelementptr i8, ptr %uglygep1, i32 225 %1 = load i16, ptr %uglygep2, align 2, !tbaa !526 %conv2 = sext i16 %1 to i3227 %conv.frozen = freeze i32 %conv28 %conv2.frozen = freeze i32 %conv229 %div = sdiv i32 %conv.frozen, %conv2.frozen30 %conv3 = trunc i32 %div to i1631 %2 = zext i16 %conv3 to i3232 %uglygep3 = getelementptr i8, ptr %uglygep1, i32 1233 %3 = trunc i32 %2 to i1634 store i16 %3, ptr %uglygep3, align 2, !tbaa !635 %4 = mul i32 %div, %conv2.frozen36 %rem.decomposed = sub i32 %conv.frozen, %437 %conv8 = trunc i32 %rem.decomposed to i1638 %5 = zext i16 %conv8 to i3239 %uglygep4 = getelementptr i8, ptr %uglygep1, i32 1440 %6 = trunc i32 %5 to i1641 store i16 %6, ptr %uglygep4, align 2, !tbaa !742 %uglygep5 = getelementptr i8, ptr %uglygep1, i32 443 %7 = load i16, ptr %uglygep5, align 2, !tbaa !844 %8 = zext i16 %7 to i3245 %cmp.not = icmp ne i32 %8, %246 %inc = zext i1 %cmp.not to i3247 %spec.select = add nsw i32 %count.0, %inc48 %uglygep6 = getelementptr i8, ptr %uglygep1, i32 649 %9 = load i16, ptr %uglygep6, align 2, !tbaa !950 %10 = zext i16 %9 to i3251 %cmp16.not = icmp ne i32 %10, %552 %inc19 = zext i1 %cmp16.not to i3253 %count.2 = add nsw i32 %spec.select, %inc1954 %uglygep7 = getelementptr i8, ptr %uglygep1, i32 855 %11 = load i16, ptr %uglygep7, align 2, !tbaa !1056 %12 = zext i16 %11 to i3257 %cmp24.not = icmp ne i32 %12, %258 %inc27 = zext i1 %cmp24.not to i3259 %count.3 = add nsw i32 %count.2, %inc2760 %uglygep8 = getelementptr i8, ptr %uglygep1, i32 1061 %13 = load i16, ptr %uglygep8, align 2, !tbaa !1162 %14 = zext i16 %13 to i3263 %cmp32.not = icmp ne i32 %14, %564 %inc35 = zext i1 %cmp32.not to i3265 %count.4 = add nsw i32 %count.3, %inc3566 %uglygep9 = getelementptr i8, ptr %uglygep1, i32 1867 %15 = load i16, ptr %uglygep9, align 2, !tbaa !568 %tobool.not = icmp eq i16 %15, 069 %uglygep = getelementptr i8, ptr %lsr.iv, i32 1670 br i1 %tobool.not, label %do.end, label %do.body71 72 do.end: ; preds = %do.body73 ret i32 %count.474 }75 76 attributes #0 = { "target-cpu"="cortex-m7" }77 78 !0 = !{!1, !2, i64 0}79 !1 = !{!"bar", !2, i64 0, !2, i64 2, !2, i64 4, !2, i64 6, !2, i64 8, !2, i64 10, !2, i64 12, !2, i64 14}80 !2 = !{!"short", !3, i64 0}81 !3 = !{!"omnipotent char", !4, i64 0}82 !4 = !{!"Simple C/C++ TBAA"}83 !5 = !{!1, !2, i64 2}84 !6 = !{!1, !2, i64 12}85 !7 = !{!1, !2, i64 14}86 !8 = !{!1, !2, i64 4}87 !9 = !{!1, !2, i64 6}88 !10 = !{!1, !2, i64 8}89 !11 = !{!1, !2, i64 10}90 91...92---93name: foo94alignment: 295exposesReturnsTwice: false96legalized: false97regBankSelected: false98selected: false99failedISel: false100tracksRegLiveness: true101hasWinCFI: false102callsEHReturn: false103callsUnwindInit: false104hasEHContTarget: false105hasEHScopes: false106hasEHFunclets: false107failsVerification: false108tracksDebugUserValues: false109registers:110 - { id: 0, class: gpr, preferred-register: '' }111 - { id: 1, class: rgpr, preferred-register: '' }112 - { id: 2, class: gpr, preferred-register: '' }113 - { id: 3, class: gpr, preferred-register: '' }114 - { id: 4, class: gpr, preferred-register: '' }115 - { id: 5, class: gpr, preferred-register: '' }116 - { id: 6, class: rgpr, preferred-register: '' }117 - { id: 7, class: rgpr, preferred-register: '' }118 - { id: 8, class: rgpr, preferred-register: '' }119 - { id: 9, class: rgpr, preferred-register: '' }120 - { id: 10, class: rgpr, preferred-register: '' }121 - { id: 11, class: rgpr, preferred-register: '' }122 - { id: 12, class: rgpr, preferred-register: '' }123 - { id: 13, class: rgpr, preferred-register: '' }124 - { id: 14, class: rgpr, preferred-register: '' }125 - { id: 15, class: rgpr, preferred-register: '' }126 - { id: 16, class: rgpr, preferred-register: '' }127 - { id: 17, class: gprnopc, preferred-register: '' }128 - { id: 18, class: rgpr, preferred-register: '' }129 - { id: 19, class: rgpr, preferred-register: '' }130 - { id: 20, class: gprnopc, preferred-register: '' }131 - { id: 21, class: rgpr, preferred-register: '' }132 - { id: 22, class: rgpr, preferred-register: '' }133 - { id: 23, class: gprnopc, preferred-register: '' }134 - { id: 24, class: rgpr, preferred-register: '' }135 - { id: 25, class: rgpr, preferred-register: '' }136 - { id: 26, class: gprnopc, preferred-register: '' }137 - { id: 27, class: rgpr, preferred-register: '' }138 - { id: 28, class: rgpr, preferred-register: '' }139 - { id: 29, class: gprnopc, preferred-register: '' }140liveins: []141frameInfo:142 isFrameAddressTaken: false143 isReturnAddressTaken: false144 hasStackMap: false145 hasPatchPoint: false146 stackSize: 0147 offsetAdjustment: 0148 maxAlignment: 1149 adjustsStack: false150 hasCalls: false151 stackProtector: ''152 functionContext: ''153 maxCallFrameSize: 0154 cvBytesOfCalleeSavedRegisters: 0155 hasOpaqueSPAdjustment: false156 hasVAStart: false157 hasMustTailInVarArgFunc: false158 hasTailCall: false159 localFrameSize: 0160 savePoint: []161 restorePoint: []162fixedStack: []163stack: []164callSites: []165debugValueSubstitutions: []166constants: []167machineFunctionInfo: {}168body: |169 ; CHECK-LABEL: name: foo170 ; CHECK: bb.0.entry:171 ; CHECK-NEXT: successors: %bb.3(0x80000000)172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm @bar174 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2MOVi32imm]], 16, 14 /* CC::al */, $noreg, $noreg175 ; CHECK-NEXT: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg176 ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY [[t2MOVi]]177 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[t2SUBri]]178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: bb.3.do.body:180 ; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.5(0x00000000)181 ; CHECK-NEXT: {{ $}}182 ; CHECK-NEXT: [[t2LDRSH_PRE:%[0-9]+]]:rgpr, [[t2LDRSH_PRE1:%[0-9]+]]:gpr = t2LDRSH_PRE [[COPY1]], 16, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep1, !tbaa !0)183 ; CHECK-NEXT: [[t2LDRSHi12_:%[0-9]+]]:rgpr = t2LDRSHi12 [[t2LDRSH_PRE1]], 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep2, !tbaa !5)184 ; CHECK-NEXT: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[t2LDRSH_PRE]], [[t2LDRSHi12_]], 14 /* CC::al */, $noreg185 ; CHECK-NEXT: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[t2SDIV]], 0, 14 /* CC::al */, $noreg186 ; CHECK-NEXT: [[t2MLS:%[0-9]+]]:rgpr = t2MLS [[t2SDIV]], [[t2LDRSHi12_]], [[t2LDRSH_PRE]], 14 /* CC::al */, $noreg187 ; CHECK-NEXT: [[t2UXTH1:%[0-9]+]]:rgpr = t2UXTH [[t2MLS]], 0, 14 /* CC::al */, $noreg188 ; CHECK-NEXT: t2STRHi12 [[t2MLS]], [[t2LDRSH_PRE1]], 14, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep4, !tbaa !7)189 ; CHECK-NEXT: [[t2LDRHi12_:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 4, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep5, !tbaa !8)190 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_]], [[t2UXTH]], 14 /* CC::al */, $noreg, implicit-def $cpsr191 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[COPY]](tied-def 0)192 ; CHECK-NEXT: [[t2LDRHi12_1:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 6, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep6, !tbaa !9)193 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_1]], [[t2UXTH1]], 14 /* CC::al */, $noreg, implicit-def $cpsr194 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri]](tied-def 0)195 ; CHECK-NEXT: [[t2LDRHi12_2:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 8, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep7, !tbaa !10)196 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_2]], [[t2UXTH]], 14 /* CC::al */, $noreg, implicit-def $cpsr197 ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri1]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri1]](tied-def 0)198 ; CHECK-NEXT: [[t2LDRHi12_3:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 10, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep8, !tbaa !11)199 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_3]], [[t2UXTH1]], 14 /* CC::al */, $noreg, implicit-def $cpsr200 ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri2]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri2]](tied-def 0)201 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY [[t2ADDri3]]202 ; CHECK-NEXT: [[t2LDRHi12_4:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 18, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep9, !tbaa !5)203 ; CHECK-NEXT: t2CMPri [[t2LDRHi12_4]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr204 ; CHECK-NEXT: t2Bcc %bb.5, 0 /* CC::eq */, $cpsr205 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: bb.4.do.body:208 ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.4(0x7c000000)209 ; CHECK-NEXT: {{ $}}210 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, %48, %bb.4211 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.3, %63, %bb.4212 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, %48, %bb.4213 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:rgpr = PHI [[t2SDIV]], %bb.3, %53, %bb.4214 ; CHECK-NEXT: t2STRHi12 [[PHI3]], [[PHI2]], 12, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep3, !tbaa !6)215 ; CHECK-NEXT: [[t2LDRSH_PRE2:%[0-9]+]]:rgpr, [[t2LDRSH_PRE3:%[0-9]+]]:gpr = t2LDRSH_PRE [[PHI]], 16, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep1, align 2, !tbaa !0)216 ; CHECK-NEXT: [[t2LDRSHi12_1:%[0-9]+]]:rgpr = t2LDRSHi12 [[t2LDRSH_PRE3]], 2, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep2, align 2, !tbaa !5)217 ; CHECK-NEXT: [[t2LDRHi12_5:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 18, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep9, align 2, !tbaa !5)218 ; CHECK-NEXT: [[t2LDRHi12_6:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 8, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep7, align 2, !tbaa !10)219 ; CHECK-NEXT: [[t2LDRHi12_7:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 10, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep8, align 2, !tbaa !11)220 ; CHECK-NEXT: [[t2SDIV1:%[0-9]+]]:rgpr = t2SDIV [[t2LDRSH_PRE2]], [[t2LDRSHi12_1]], 14 /* CC::al */, $noreg221 ; CHECK-NEXT: [[t2LDRHi12_8:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 4, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep5, align 2, !tbaa !8)222 ; CHECK-NEXT: [[t2MLS1:%[0-9]+]]:rgpr = t2MLS [[t2SDIV1]], [[t2LDRSHi12_1]], [[t2LDRSH_PRE2]], 14 /* CC::al */, $noreg223 ; CHECK-NEXT: [[t2UXTH2:%[0-9]+]]:rgpr = t2UXTH [[t2SDIV1]], 0, 14 /* CC::al */, $noreg224 ; CHECK-NEXT: [[t2LDRHi12_9:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 6, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep6, align 2, !tbaa !9)225 ; CHECK-NEXT: [[t2UXTH3:%[0-9]+]]:rgpr = t2UXTH [[t2MLS1]], 0, 14 /* CC::al */, $noreg226 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_8]], [[t2UXTH2]], 14 /* CC::al */, $noreg, implicit-def $cpsr227 ; CHECK-NEXT: [[t2ADDri4:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[PHI1]](tied-def 0)228 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_9]], [[t2UXTH3]], 14 /* CC::al */, $noreg, implicit-def $cpsr229 ; CHECK-NEXT: [[t2ADDri5:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri4]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri4]](tied-def 0)230 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_6]], [[t2UXTH2]], 14 /* CC::al */, $noreg, implicit-def $cpsr231 ; CHECK-NEXT: [[t2ADDri6:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri5]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri5]](tied-def 0)232 ; CHECK-NEXT: t2CMPrr [[t2LDRHi12_7]], [[t2UXTH3]], 14 /* CC::al */, $noreg, implicit-def $cpsr233 ; CHECK-NEXT: [[t2ADDri7:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri6]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri6]](tied-def 0)234 ; CHECK-NEXT: t2CMPri [[t2LDRHi12_5]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr235 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[t2ADDri7]]236 ; CHECK-NEXT: t2STRHi12 [[t2MLS1]], [[t2LDRSH_PRE3]], 14, 14 /* CC::al */, $noreg :: (store unknown-size into %ir.uglygep4, align 2, !tbaa !7)237 ; CHECK-NEXT: t2Bcc %bb.4, 1 /* CC::ne */, $cpsr238 ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg239 ; CHECK-NEXT: {{ $}}240 ; CHECK-NEXT: bb.5:241 ; CHECK-NEXT: successors: %bb.2(0x80000000)242 ; CHECK-NEXT: {{ $}}243 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, [[t2LDRSH_PRE3]], %bb.4244 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:rgpr = PHI [[t2SDIV]], %bb.3, [[t2SDIV1]], %bb.4245 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.3, [[COPY3]], %bb.4246 ; CHECK-NEXT: t2STRHi12 [[PHI5]], [[PHI4]], 12, 14 /* CC::al */, $noreg :: (store unknown-size into %ir.uglygep3, align 2, !tbaa !6)247 ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg248 ; CHECK-NEXT: {{ $}}249 ; CHECK-NEXT: bb.2.do.end:250 ; CHECK-NEXT: $r0 = COPY [[PHI6]]251 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0252 bb.0.entry:253 successors: %bb.1(0x80000000)254 255 %6:rgpr = t2MOVi32imm @bar256 %7:rgpr = t2SUBri killed %6, 16, 14 /* CC::al */, $noreg, $noreg257 %8:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg258 %5:gpr = COPY %8259 %4:gpr = COPY %7260 261 bb.1.do.body:262 successors: %bb.2(0x04000000), %bb.1(0x7c000000)263 264 %0:gpr = PHI %4, %bb.0, %3, %bb.1265 %1:rgpr = PHI %5, %bb.0, %2, %bb.1266 %9:rgpr, %3:gpr = t2LDRSH_PRE %0, 16, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep1, !tbaa !0)267 %10:rgpr = t2LDRSHi12 %3, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep2, !tbaa !5)268 %13:rgpr = t2SDIV %9, %10, 14 /* CC::al */, $noreg269 %14:rgpr = t2UXTH %13, 0, 14 /* CC::al */, $noreg270 t2STRHi12 %13, %3, 12, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep3, !tbaa !6)271 %15:rgpr = t2MLS %13, %10, %9, 14 /* CC::al */, $noreg272 %16:rgpr = t2UXTH %15, 0, 14 /* CC::al */, $noreg273 t2STRHi12 %15, %3, 14, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep4, !tbaa !7)274 %17:gprnopc = t2LDRHi12 %3, 4, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep5, !tbaa !8)275 t2CMPrr killed %17, %14, 14 /* CC::al */, $noreg, implicit-def $cpsr276 %19:rgpr = t2ADDri %1, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %1(tied-def 0)277 %20:gprnopc = t2LDRHi12 %3, 6, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep6, !tbaa !9)278 t2CMPrr killed %20, %16, 14 /* CC::al */, $noreg, implicit-def $cpsr279 %22:rgpr = t2ADDri %19, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %19(tied-def 0)280 %23:gprnopc = t2LDRHi12 %3, 8, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep7, !tbaa !10)281 t2CMPrr killed %23, %14, 14 /* CC::al */, $noreg, implicit-def $cpsr282 %25:rgpr = t2ADDri %22, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %22(tied-def 0)283 %26:gprnopc = t2LDRHi12 %3, 10, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep8, !tbaa !11)284 t2CMPrr killed %26, %16, 14 /* CC::al */, $noreg, implicit-def $cpsr285 %28:rgpr = t2ADDri %25, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %25(tied-def 0)286 %2:gpr = COPY %28287 %29:gprnopc = t2LDRHi12 %3, 18, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep9, !tbaa !5)288 t2CMPri killed %29, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr289 t2Bcc %bb.1, 1 /* CC::ne */, $cpsr290 t2B %bb.2, 14 /* CC::al */, $noreg291 292 bb.2.do.end:293 $r0 = COPY %2294 tBX_RET 14 /* CC::al */, $noreg, implicit $r0295 296...297