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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - -verify-machineinstrs | FileCheck %s3 4--- |5 define ptr @t2LDRi12(ptr %x, i32 %y) { unreachable }6 define ptr @t2LDRHi12(ptr %x, i32 %y) { unreachable }7 define ptr @t2LDRSHi12(ptr %x, i32 %y) { unreachable }8 define ptr @t2LDRBi12(ptr %x, i32 %y) { unreachable }9 define ptr @t2LDRSBi12(ptr %x, i32 %y) { unreachable }10 define ptr @t2STRi12(ptr %x, i32 %y) { unreachable }11 define ptr @t2STRHi12(ptr %x, i32 %y) { unreachable }12 define ptr @t2STRBi12(ptr %x, i32 %y) { unreachable }13 14 define ptr @storedadd(ptr %x, i32 %y) { unreachable }15 define ptr @minsize2(ptr %x, i32 %y) minsize optsize { unreachable }16 define ptr @minsize3(ptr %x, i32 %y) minsize optsize { unreachable }17 18 define ptr @t2LDRi12_posoff(ptr %x, i32 %y) { unreachable }19 define ptr @t2LDRHi12_posoff(ptr %x, i32 %y) { unreachable }20 define ptr @t2LDRBi12_posoff(ptr %x, i32 %y) { unreachable }21 define ptr @t2STRi12_posoff(ptr %x, i32 %y) { unreachable }22 define ptr @t2STRHi12_posoff(ptr %x, i32 %y) { unreachable }23 define ptr @t2STRBi12_posoff(ptr %x, i32 %y) { unreachable }24 define ptr @t2LDRi12_negoff(ptr %x, i32 %y) { unreachable }25 define ptr @t2LDRHi12_negoff(ptr %x, i32 %y) { unreachable }26 define ptr @t2LDRBi12_negoff(ptr %x, i32 %y) { unreachable }27 define ptr @t2STRi12_negoff(ptr %x, i32 %y) { unreachable }28 define ptr @t2STRHi12_negoff(ptr %x, i32 %y) { unreachable }29 define ptr @t2STRBi12_negoff(ptr %x, i32 %y) { unreachable }30 31...32---33name: t2LDRi1234tracksRegLiveness: true35registers:36 - { id: 0, class: gprnopc, preferred-register: '' }37 - { id: 1, class: rgpr, preferred-register: '' }38 - { id: 2, class: rgpr, preferred-register: '' }39liveins:40 - { reg: '$r0', virtual-reg: '%0' }41body: |42 bb.0:43 liveins: $r044 45 ; CHECK-LABEL: name: t2LDRi1246 ; CHECK: liveins: $r047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r049 ; CHECK-NEXT: [[t2LDRi12_:%[0-9]+]]:rgpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))50 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg51 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]]52 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r053 %0:gprnopc = COPY $r054 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load (s32), align 4)55 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg56 $r0 = COPY %257 tBX_RET 14, $noreg, implicit $r058 59...60---61name: t2LDRHi1262tracksRegLiveness: true63registers:64 - { id: 0, class: gprnopc, preferred-register: '' }65 - { id: 1, class: rgpr, preferred-register: '' }66 - { id: 2, class: rgpr, preferred-register: '' }67liveins:68 - { reg: '$r0', virtual-reg: '%0' }69body: |70 bb.0:71 liveins: $r072 73 ; CHECK-LABEL: name: t2LDRHi1274 ; CHECK: liveins: $r075 ; CHECK-NEXT: {{ $}}76 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r077 ; CHECK-NEXT: [[t2LDRH_POST:%[0-9]+]]:rgpr, [[t2LDRH_POST1:%[0-9]+]]:rgpr = t2LDRH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))78 ; CHECK-NEXT: $r0 = COPY [[t2LDRH_POST1]]79 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r080 %0:gprnopc = COPY $r081 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load (s32), align 4)82 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg83 $r0 = COPY %284 tBX_RET 14, $noreg, implicit $r085 86...87---88name: t2LDRSHi1289tracksRegLiveness: true90registers:91 - { id: 0, class: gprnopc, preferred-register: '' }92 - { id: 1, class: rgpr, preferred-register: '' }93 - { id: 2, class: rgpr, preferred-register: '' }94liveins:95 - { reg: '$r0', virtual-reg: '%0' }96body: |97 bb.0:98 liveins: $r099 100 ; CHECK-LABEL: name: t2LDRSHi12101 ; CHECK: liveins: $r0102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0104 ; CHECK-NEXT: [[t2LDRSH_POST:%[0-9]+]]:rgpr, [[t2LDRSH_POST1:%[0-9]+]]:rgpr = t2LDRSH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))105 ; CHECK-NEXT: $r0 = COPY [[t2LDRSH_POST1]]106 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0107 %0:gprnopc = COPY $r0108 %1:rgpr = t2LDRSHi12 %0, 0, 14, $noreg :: (load (s32), align 4)109 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg110 $r0 = COPY %2111 tBX_RET 14, $noreg, implicit $r0112 113...114---115name: t2LDRBi12116tracksRegLiveness: true117registers:118 - { id: 0, class: gprnopc, preferred-register: '' }119 - { id: 1, class: rgpr, preferred-register: '' }120 - { id: 2, class: rgpr, preferred-register: '' }121liveins:122 - { reg: '$r0', virtual-reg: '%0' }123body: |124 bb.0:125 liveins: $r0126 127 ; CHECK-LABEL: name: t2LDRBi12128 ; CHECK: liveins: $r0129 ; CHECK-NEXT: {{ $}}130 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0131 ; CHECK-NEXT: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))132 ; CHECK-NEXT: $r0 = COPY [[t2LDRB_POST1]]133 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0134 %0:gprnopc = COPY $r0135 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4)136 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg137 $r0 = COPY %2138 tBX_RET 14, $noreg, implicit $r0139 140...141---142name: t2LDRSBi12143tracksRegLiveness: true144registers:145 - { id: 0, class: gprnopc, preferred-register: '' }146 - { id: 1, class: rgpr, preferred-register: '' }147 - { id: 2, class: rgpr, preferred-register: '' }148liveins:149 - { reg: '$r0', virtual-reg: '%0' }150body: |151 bb.0:152 liveins: $r0153 154 ; CHECK-LABEL: name: t2LDRSBi12155 ; CHECK: liveins: $r0156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0158 ; CHECK-NEXT: [[t2LDRSB_POST:%[0-9]+]]:rgpr, [[t2LDRSB_POST1:%[0-9]+]]:rgpr = t2LDRSB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))159 ; CHECK-NEXT: $r0 = COPY [[t2LDRSB_POST1]]160 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0161 %0:gprnopc = COPY $r0162 %1:rgpr = t2LDRSBi12 %0, 0, 14, $noreg :: (load (s32), align 4)163 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg164 $r0 = COPY %2165 tBX_RET 14, $noreg, implicit $r0166 167...168---169name: t2STRi12170tracksRegLiveness: true171registers:172 - { id: 0, class: gprnopc, preferred-register: '' }173 - { id: 1, class: rgpr, preferred-register: '' }174 - { id: 2, class: rgpr, preferred-register: '' }175liveins:176 - { reg: '$r0', virtual-reg: '%0' }177 - { reg: '$r1', virtual-reg: '%1' }178body: |179 bb.0:180 liveins: $r0, $r1181 182 ; CHECK-LABEL: name: t2STRi12183 ; CHECK: liveins: $r0, $r1184 ; CHECK-NEXT: {{ $}}185 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0186 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1187 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))188 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg189 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]]190 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0191 %0:gprnopc = COPY $r0192 %1:rgpr = COPY $r1193 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)194 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg195 $r0 = COPY %2196 tBX_RET 14, $noreg, implicit $r0197 198...199---200name: t2STRHi12201tracksRegLiveness: true202registers:203 - { id: 0, class: gprnopc, preferred-register: '' }204 - { id: 1, class: rgpr, preferred-register: '' }205 - { id: 2, class: rgpr, preferred-register: '' }206liveins:207 - { reg: '$r0', virtual-reg: '%0' }208 - { reg: '$r1', virtual-reg: '%1' }209body: |210 bb.0:211 liveins: $r0, $r1212 213 ; CHECK-LABEL: name: t2STRHi12214 ; CHECK: liveins: $r0, $r1215 ; CHECK-NEXT: {{ $}}216 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0217 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1218 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRH_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32))219 ; CHECK-NEXT: $r0 = COPY %2220 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0221 %0:gprnopc = COPY $r0222 %1:rgpr = COPY $r1223 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)224 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg225 $r0 = COPY %2226 tBX_RET 14, $noreg, implicit $r0227 228...229---230name: t2STRBi12231tracksRegLiveness: true232registers:233 - { id: 0, class: gprnopc, preferred-register: '' }234 - { id: 1, class: rgpr, preferred-register: '' }235 - { id: 2, class: rgpr, preferred-register: '' }236liveins:237 - { reg: '$r0', virtual-reg: '%0' }238 - { reg: '$r1', virtual-reg: '%1' }239body: |240 bb.0:241 liveins: $r0, $r1242 243 ; CHECK-LABEL: name: t2STRBi12244 ; CHECK: liveins: $r0, $r1245 ; CHECK-NEXT: {{ $}}246 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0247 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1248 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRB_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32))249 ; CHECK-NEXT: $r0 = COPY %2250 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0251 %0:gprnopc = COPY $r0252 %1:rgpr = COPY $r1253 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)254 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg255 $r0 = COPY %2256 tBX_RET 14, $noreg, implicit $r0257 258...259---260name: storedadd261tracksRegLiveness: true262registers:263 - { id: 0, class: gprnopc, preferred-register: '' }264 - { id: 1, class: rgpr, preferred-register: '' }265liveins:266 - { reg: '$r0', virtual-reg: '%0' }267body: |268 bb.0:269 liveins: $r0270 271 ; CHECK-LABEL: name: storedadd272 ; CHECK: liveins: $r0273 ; CHECK-NEXT: {{ $}}274 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0275 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg276 ; CHECK-NEXT: t2STRi12 [[t2ADDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))277 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]]278 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0279 %0:gprnopc = COPY $r0280 %1:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg281 t2STRi12 %1, %0, 0, 14, $noreg :: (store (s32), align 4)282 $r0 = COPY %1283 tBX_RET 14, $noreg, implicit $r0284 285...286---287name: minsize2288tracksRegLiveness: true289registers:290 - { id: 0, class: gprnopc, preferred-register: '' }291 - { id: 1, class: rgpr, preferred-register: '' }292 - { id: 2, class: rgpr, preferred-register: '' }293 - { id: 3, class: rgpr, preferred-register: '' }294liveins:295 - { reg: '$r0', virtual-reg: '%0' }296body: |297 bb.0:298 liveins: $r0299 300 ; CHECK-LABEL: name: minsize2301 ; CHECK: liveins: $r0302 ; CHECK-NEXT: {{ $}}303 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0304 ; CHECK-NEXT: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))305 ; CHECK-NEXT: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -30, 14 /* CC::al */, $noreg :: (load (s32))306 ; CHECK-NEXT: $r0 = COPY [[t2LDRB_POST1]]307 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0308 %0:gprnopc = COPY $r0309 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4)310 %3:rgpr = t2LDRBi12 %0, 2, 14, $noreg :: (load (s32), align 4)311 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg312 $r0 = COPY %2313 tBX_RET 14, $noreg, implicit $r0314 315...316---317name: minsize3318tracksRegLiveness: true319registers:320 - { id: 0, class: gprnopc, preferred-register: '' }321 - { id: 1, class: rgpr, preferred-register: '' }322 - { id: 2, class: rgpr, preferred-register: '' }323 - { id: 3, class: rgpr, preferred-register: '' }324 - { id: 4, class: rgpr, preferred-register: '' }325liveins:326 - { reg: '$r0', virtual-reg: '%0' }327body: |328 bb.0:329 liveins: $r0330 331 ; CHECK-LABEL: name: minsize3332 ; CHECK: liveins: $r0333 ; CHECK-NEXT: {{ $}}334 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0335 ; CHECK-NEXT: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))336 ; CHECK-NEXT: [[t2LDRBi12_1:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 2, 14 /* CC::al */, $noreg :: (load (s32))337 ; CHECK-NEXT: [[t2LDRBi12_2:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load (s32))338 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg339 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]]340 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0341 %0:gprnopc = COPY $r0342 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4)343 %3:rgpr = t2LDRBi12 %0, 2, 14, $noreg :: (load (s32), align 4)344 %4:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load (s32), align 4)345 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg346 $r0 = COPY %2347 tBX_RET 14, $noreg, implicit $r0348 349...350---351name: t2LDRi12_posoff352tracksRegLiveness: true353registers:354 - { id: 0, class: gprnopc, preferred-register: '' }355 - { id: 1, class: rgpr, preferred-register: '' }356 - { id: 2, class: rgpr, preferred-register: '' }357 - { id: 3, class: rgpr, preferred-register: '' }358 - { id: 4, class: rgpr, preferred-register: '' }359liveins:360 - { reg: '$r0', virtual-reg: '%0' }361body: |362 bb.0:363 liveins: $r0364 365 ; CHECK-LABEL: name: t2LDRi12_posoff366 ; CHECK: liveins: $r0367 ; CHECK-NEXT: {{ $}}368 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0369 ; CHECK-NEXT: [[t2LDRDi8_:%[0-9]+]]:rgpr, [[t2LDRDi8_1:%[0-9]+]]:rgpr = t2LDRDi8 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))370 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg371 ; CHECK-NEXT: [[t2LDRi8_:%[0-9]+]]:rgpr = t2LDRi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32))372 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]]373 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0374 %0:gprnopc = COPY $r0375 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load (s32), align 4)376 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg377 %3:rgpr = t2LDRi12 %0, 4, 14, $noreg :: (load (s32), align 4)378 %4:rgpr = t2LDRi8 %0, -8, 14, $noreg :: (load (s32), align 4)379 $r0 = COPY %2380 tBX_RET 14, $noreg, implicit $r0381 382...383---384name: t2LDRHi12_posoff385tracksRegLiveness: true386registers:387 - { id: 0, class: gprnopc, preferred-register: '' }388 - { id: 1, class: rgpr, preferred-register: '' }389 - { id: 2, class: rgpr, preferred-register: '' }390 - { id: 3, class: rgpr, preferred-register: '' }391 - { id: 4, class: rgpr, preferred-register: '' }392 - { id: 5, class: rgpr, preferred-register: '' }393liveins:394 - { reg: '$r0', virtual-reg: '%0' }395body: |396 bb.0:397 liveins: $r0398 399 ; CHECK-LABEL: name: t2LDRHi12_posoff400 ; CHECK: liveins: $r0401 ; CHECK-NEXT: {{ $}}402 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0403 ; CHECK-NEXT: [[t2LDRH_POST:%[0-9]+]]:rgpr, [[t2LDRH_POST1:%[0-9]+]]:rgpr = t2LDRH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))404 ; CHECK-NEXT: [[t2LDRHi8_:%[0-9]+]]:rgpr = t2LDRHi8 [[t2LDRH_POST1]], -28, 14 /* CC::al */, $noreg :: (load (s32))405 ; CHECK-NEXT: [[t2LDRHi8_1:%[0-9]+]]:rgpr = t2LDRHi8 [[t2LDRH_POST1]], -40, 14 /* CC::al */, $noreg :: (load (s32))406 ; CHECK-NEXT: [[t2LDRSHi8_:%[0-9]+]]:rgpr = t2LDRSHi8 [[t2LDRH_POST1]], -20, 14 /* CC::al */, $noreg :: (load (s32))407 ; CHECK-NEXT: $r0 = COPY [[t2LDRH_POST1]]408 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0409 %0:gprnopc = COPY $r0410 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load (s32), align 4)411 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg412 %3:rgpr = t2LDRHi12 %0, 4, 14, $noreg :: (load (s32), align 4)413 %4:rgpr = t2LDRHi8 %0, -8, 14, $noreg :: (load (s32), align 4)414 %5:rgpr = t2LDRSHi12 %0, 12, 14, $noreg :: (load (s32), align 4)415 $r0 = COPY %2416 tBX_RET 14, $noreg, implicit $r0417 418...419---420name: t2LDRBi12_posoff421tracksRegLiveness: true422registers:423 - { id: 0, class: gprnopc, preferred-register: '' }424 - { id: 1, class: rgpr, preferred-register: '' }425 - { id: 2, class: rgpr, preferred-register: '' }426 - { id: 3, class: rgpr, preferred-register: '' }427 - { id: 4, class: rgpr, preferred-register: '' }428 - { id: 5, class: rgpr, preferred-register: '' }429liveins:430 - { reg: '$r0', virtual-reg: '%0' }431body: |432 bb.0:433 liveins: $r0434 435 ; CHECK-LABEL: name: t2LDRBi12_posoff436 ; CHECK: liveins: $r0437 ; CHECK-NEXT: {{ $}}438 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0439 ; CHECK-NEXT: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32))440 ; CHECK-NEXT: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -28, 14 /* CC::al */, $noreg :: (load (s32))441 ; CHECK-NEXT: [[t2LDRBi8_1:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -40, 14 /* CC::al */, $noreg :: (load (s32))442 ; CHECK-NEXT: [[t2LDRSBi8_:%[0-9]+]]:rgpr = t2LDRSBi8 [[t2LDRB_POST1]], -20, 14 /* CC::al */, $noreg :: (load (s32))443 ; CHECK-NEXT: $r0 = COPY [[t2LDRB_POST1]]444 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0445 %0:gprnopc = COPY $r0446 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4)447 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg448 %3:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load (s32), align 4)449 %4:rgpr = t2LDRBi8 %0, -8, 14, $noreg :: (load (s32), align 4)450 %12:rgpr = t2LDRSBi12 %0, 12, 14, $noreg :: (load (s32), align 4)451 $r0 = COPY %2452 tBX_RET 14, $noreg, implicit $r0453 454...455---456name: t2STRi12_posoff457tracksRegLiveness: true458registers:459 - { id: 0, class: gprnopc, preferred-register: '' }460 - { id: 1, class: rgpr, preferred-register: '' }461 - { id: 2, class: rgpr, preferred-register: '' }462liveins:463 - { reg: '$r0', virtual-reg: '%0' }464 - { reg: '$r1', virtual-reg: '%1' }465body: |466 bb.0:467 liveins: $r0, $r1468 469 ; CHECK-LABEL: name: t2STRi12_posoff470 ; CHECK: liveins: $r0, $r1471 ; CHECK-NEXT: {{ $}}472 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0473 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1474 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg475 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))476 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32))477 ; CHECK-NEXT: t2STRi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32))478 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]]479 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0480 %0:gprnopc = COPY $r0481 %1:rgpr = COPY $r1482 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)483 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg484 t2STRi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4)485 t2STRi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4)486 $r0 = COPY %2487 tBX_RET 14, $noreg, implicit $r0488 489...490---491name: t2STRHi12_posoff492tracksRegLiveness: true493registers:494 - { id: 0, class: gprnopc, preferred-register: '' }495 - { id: 1, class: rgpr, preferred-register: '' }496 - { id: 2, class: rgpr, preferred-register: '' }497liveins:498 - { reg: '$r0', virtual-reg: '%0' }499 - { reg: '$r1', virtual-reg: '%1' }500body: |501 bb.0:502 liveins: $r0, $r1503 504 ; CHECK-LABEL: name: t2STRHi12_posoff505 ; CHECK: liveins: $r0, $r1506 ; CHECK-NEXT: {{ $}}507 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0508 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1509 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRH_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32))510 ; CHECK-NEXT: t2STRHi8 [[COPY1]], %2, -28, 14 /* CC::al */, $noreg :: (store (s32))511 ; CHECK-NEXT: t2STRHi8 [[COPY1]], %2, -40, 14 /* CC::al */, $noreg :: (store (s32))512 ; CHECK-NEXT: $r0 = COPY %2513 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0514 %0:gprnopc = COPY $r0515 %1:rgpr = COPY $r1516 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)517 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg518 t2STRHi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4)519 t2STRHi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4)520 $r0 = COPY %2521 tBX_RET 14, $noreg, implicit $r0522 523...524---525name: t2STRBi12_posoff526tracksRegLiveness: true527registers:528 - { id: 0, class: gprnopc, preferred-register: '' }529 - { id: 1, class: rgpr, preferred-register: '' }530 - { id: 2, class: rgpr, preferred-register: '' }531liveins:532 - { reg: '$r0', virtual-reg: '%0' }533 - { reg: '$r1', virtual-reg: '%1' }534body: |535 bb.0:536 liveins: $r0, $r1537 538 ; CHECK-LABEL: name: t2STRBi12_posoff539 ; CHECK: liveins: $r0, $r1540 ; CHECK-NEXT: {{ $}}541 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0542 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1543 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRB_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32))544 ; CHECK-NEXT: t2STRBi8 [[COPY1]], %2, -28, 14 /* CC::al */, $noreg :: (store (s32))545 ; CHECK-NEXT: t2STRBi8 [[COPY1]], %2, -40, 14 /* CC::al */, $noreg :: (store (s32))546 ; CHECK-NEXT: $r0 = COPY %2547 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0548 %0:gprnopc = COPY $r0549 %1:rgpr = COPY $r1550 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)551 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg552 t2STRBi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4)553 t2STRBi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4)554 $r0 = COPY %2555 tBX_RET 14, $noreg, implicit $r0556 557...558---559name: t2LDRi12_negoff560tracksRegLiveness: true561registers:562 - { id: 0, class: gprnopc, preferred-register: '' }563 - { id: 1, class: rgpr, preferred-register: '' }564 - { id: 2, class: rgpr, preferred-register: '' }565 - { id: 3, class: rgpr, preferred-register: '' }566 - { id: 4, class: rgpr, preferred-register: '' }567liveins:568 - { reg: '$r0', virtual-reg: '%0' }569body: |570 bb.0:571 liveins: $r0572 573 ; CHECK-LABEL: name: t2LDRi12_negoff574 ; CHECK: liveins: $r0575 ; CHECK-NEXT: {{ $}}576 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0577 ; CHECK-NEXT: [[t2LDRDi8_:%[0-9]+]]:rgpr, [[t2LDRDi8_1:%[0-9]+]]:rgpr = t2LDRDi8 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))578 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg579 ; CHECK-NEXT: [[t2LDRi8_:%[0-9]+]]:rgpr = t2LDRi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32))580 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]]581 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0582 %0:gprnopc = COPY $r0583 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load (s32), align 4)584 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg585 %3:rgpr = t2LDRi12 %0, 4, 14, $noreg :: (load (s32), align 4)586 %4:rgpr = t2LDRi8 %0, -8, 14, $noreg :: (load (s32), align 4)587 $r0 = COPY %2588 tBX_RET 14, $noreg, implicit $r0589 590...591---592name: t2LDRHi12_negoff593tracksRegLiveness: true594registers:595 - { id: 0, class: gprnopc, preferred-register: '' }596 - { id: 1, class: rgpr, preferred-register: '' }597 - { id: 2, class: rgpr, preferred-register: '' }598 - { id: 3, class: rgpr, preferred-register: '' }599 - { id: 4, class: rgpr, preferred-register: '' }600 - { id: 5, class: rgpr, preferred-register: '' }601liveins:602 - { reg: '$r0', virtual-reg: '%0' }603body: |604 bb.0:605 liveins: $r0606 607 ; CHECK-LABEL: name: t2LDRHi12_negoff608 ; CHECK: liveins: $r0609 ; CHECK-NEXT: {{ $}}610 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0611 ; CHECK-NEXT: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))612 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg613 ; CHECK-NEXT: [[t2LDRHi12_1:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load (s32))614 ; CHECK-NEXT: [[t2LDRHi8_:%[0-9]+]]:rgpr = t2LDRHi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32))615 ; CHECK-NEXT: [[t2LDRSHi12_:%[0-9]+]]:rgpr = t2LDRSHi12 [[COPY]], 12, 14 /* CC::al */, $noreg :: (load (s32))616 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]]617 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0618 %0:gprnopc = COPY $r0619 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load (s32), align 4)620 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg621 %3:rgpr = t2LDRHi12 %0, 4, 14, $noreg :: (load (s32), align 4)622 %4:rgpr = t2LDRHi8 %0, -8, 14, $noreg :: (load (s32), align 4)623 %5:rgpr = t2LDRSHi12 %0, 12, 14, $noreg :: (load (s32), align 4)624 $r0 = COPY %2625 tBX_RET 14, $noreg, implicit $r0626 627...628---629name: t2LDRBi12_negoff630tracksRegLiveness: true631registers:632 - { id: 0, class: gprnopc, preferred-register: '' }633 - { id: 1, class: rgpr, preferred-register: '' }634 - { id: 2, class: rgpr, preferred-register: '' }635 - { id: 3, class: rgpr, preferred-register: '' }636 - { id: 4, class: rgpr, preferred-register: '' }637 - { id: 5, class: rgpr, preferred-register: '' }638liveins:639 - { reg: '$r0', virtual-reg: '%0' }640body: |641 bb.0:642 liveins: $r0643 644 ; CHECK-LABEL: name: t2LDRBi12_negoff645 ; CHECK: liveins: $r0646 ; CHECK-NEXT: {{ $}}647 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0648 ; CHECK-NEXT: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))649 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg650 ; CHECK-NEXT: [[t2LDRBi12_1:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load (s32))651 ; CHECK-NEXT: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32))652 ; CHECK-NEXT: [[t2LDRSBi12_:%[0-9]+]]:rgpr = t2LDRSBi12 [[COPY]], 12, 14 /* CC::al */, $noreg :: (load (s32))653 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]]654 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0655 %0:gprnopc = COPY $r0656 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4)657 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg658 %3:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load (s32), align 4)659 %4:rgpr = t2LDRBi8 %0, -8, 14, $noreg :: (load (s32), align 4)660 %12:rgpr = t2LDRSBi12 %0, 12, 14, $noreg :: (load (s32), align 4)661 $r0 = COPY %2662 tBX_RET 14, $noreg, implicit $r0663 664...665---666name: t2STRi12_negoff667tracksRegLiveness: true668registers:669 - { id: 0, class: gprnopc, preferred-register: '' }670 - { id: 1, class: rgpr, preferred-register: '' }671 - { id: 2, class: rgpr, preferred-register: '' }672liveins:673 - { reg: '$r0', virtual-reg: '%0' }674 - { reg: '$r1', virtual-reg: '%1' }675body: |676 bb.0:677 liveins: $r0, $r1678 679 ; CHECK-LABEL: name: t2STRi12_negoff680 ; CHECK: liveins: $r0, $r1681 ; CHECK-NEXT: {{ $}}682 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0683 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1684 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg685 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))686 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32))687 ; CHECK-NEXT: t2STRi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32))688 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]]689 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0690 %0:gprnopc = COPY $r0691 %1:rgpr = COPY $r1692 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)693 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg694 t2STRi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4)695 t2STRi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4)696 $r0 = COPY %2697 tBX_RET 14, $noreg, implicit $r0698 699...700---701name: t2STRHi12_negoff702tracksRegLiveness: true703registers:704 - { id: 0, class: gprnopc, preferred-register: '' }705 - { id: 1, class: rgpr, preferred-register: '' }706 - { id: 2, class: rgpr, preferred-register: '' }707liveins:708 - { reg: '$r0', virtual-reg: '%0' }709 - { reg: '$r1', virtual-reg: '%1' }710body: |711 bb.0:712 liveins: $r0, $r1713 714 ; CHECK-LABEL: name: t2STRHi12_negoff715 ; CHECK: liveins: $r0, $r1716 ; CHECK-NEXT: {{ $}}717 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0718 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1719 ; CHECK-NEXT: t2STRHi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))720 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg721 ; CHECK-NEXT: t2STRHi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32))722 ; CHECK-NEXT: t2STRHi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32))723 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]]724 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0725 %0:gprnopc = COPY $r0726 %1:rgpr = COPY $r1727 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)728 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg729 t2STRHi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4)730 t2STRHi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4)731 $r0 = COPY %2732 tBX_RET 14, $noreg, implicit $r0733 734...735---736name: t2STRBi12_negoff737tracksRegLiveness: true738registers:739 - { id: 0, class: gprnopc, preferred-register: '' }740 - { id: 1, class: rgpr, preferred-register: '' }741 - { id: 2, class: rgpr, preferred-register: '' }742liveins:743 - { reg: '$r0', virtual-reg: '%0' }744 - { reg: '$r1', virtual-reg: '%1' }745body: |746 bb.0:747 liveins: $r0, $r1748 749 ; CHECK-LABEL: name: t2STRBi12_negoff750 ; CHECK: liveins: $r0, $r1751 ; CHECK-NEXT: {{ $}}752 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0753 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1754 ; CHECK-NEXT: t2STRBi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))755 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg756 ; CHECK-NEXT: t2STRBi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32))757 ; CHECK-NEXT: t2STRBi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32))758 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]]759 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0760 %0:gprnopc = COPY $r0761 %1:rgpr = COPY $r1762 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4)763 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg764 t2STRBi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4)765 t2STRBi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4)766 $r0 = COPY %2767 tBX_RET 14, $noreg, implicit $r0768 769...770