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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CHECK3; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -arm-data-bank-mask=-1 | FileCheck %s --check-prefix=NOBANK4 5; This tests the cortex-m7 bank conflict hazard recognizer.6; Normally both loads would be scheduled early (both in the first cycle) due to7; their latency. But will bank conflict to TCM so are scheduled in different8; cycles.9 10define i32 @test(ptr %x0, i32 %y, i32 %z) {11; CHECK-LABEL: test:12; CHECK: @ %bb.0: @ %entry13; CHECK-NEXT: ldr r3, [r0]14; CHECK-NEXT: subs r1, r3, r115; CHECK-NEXT: ldr r0, [r0, #8]16; CHECK-NEXT: subs r1, r1, r217; CHECK-NEXT: adds r1, #118; CHECK-NEXT: muls r0, r1, r019; CHECK-NEXT: bx lr20;21; NOBANK-LABEL: test:22; NOBANK: @ %bb.0: @ %entry23; NOBANK-NEXT: ldr r3, [r0]24; NOBANK-NEXT: ldr r0, [r0, #8]25; NOBANK-NEXT: subs r1, r3, r126; NOBANK-NEXT: subs r1, r1, r227; NOBANK-NEXT: adds r1, #128; NOBANK-NEXT: muls r0, r1, r029; NOBANK-NEXT: bx lr30entry:31 %0 = load i32, ptr %x0, align 432 %mul3 = add nsw i32 %0, 133 %mul = sub nsw i32 %mul3, %y34 %sub = sub nsw i32 %mul, %z35 %arrayidx1 = getelementptr inbounds i32, ptr %x0, i32 236 %1 = load i32, ptr %arrayidx1, align 437 %mul2 = mul nsw i32 %sub, %138 ret i32 %mul239}40