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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE3; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NON-MVE4 5define i64 @shift_left_reg(i64 %x, i64 %y) {6; CHECK-MVE-LABEL: shift_left_reg:7; CHECK-MVE: @ %bb.0: @ %entry8; CHECK-MVE-NEXT: lsll r0, r1, r29; CHECK-MVE-NEXT: bx lr10;11; CHECK-NON-MVE-LABEL: shift_left_reg:12; CHECK-NON-MVE: @ %bb.0: @ %entry13; CHECK-NON-MVE-NEXT: rsb.w r3, r2, #3214; CHECK-NON-MVE-NEXT: lsls r1, r215; CHECK-NON-MVE-NEXT: lsr.w r3, r0, r316; CHECK-NON-MVE-NEXT: orrs r1, r317; CHECK-NON-MVE-NEXT: subs.w r3, r2, #3218; CHECK-NON-MVE-NEXT: it pl19; CHECK-NON-MVE-NEXT: lslpl.w r1, r0, r320; CHECK-NON-MVE-NEXT: lsl.w r0, r0, r221; CHECK-NON-MVE-NEXT: it pl22; CHECK-NON-MVE-NEXT: movpl r0, #023; CHECK-NON-MVE-NEXT: bx lr24entry:25 %shl = shl i64 %x, %y26 ret i64 %shl27}28 29define i64 @shift_left_imm(i64 %x) {30; CHECK-MVE-LABEL: shift_left_imm:31; CHECK-MVE: @ %bb.0: @ %entry32; CHECK-MVE-NEXT: lsll r0, r1, #333; CHECK-MVE-NEXT: bx lr34;35; CHECK-NON-MVE-LABEL: shift_left_imm:36; CHECK-NON-MVE: @ %bb.0: @ %entry37; CHECK-NON-MVE-NEXT: lsls r1, r1, #338; CHECK-NON-MVE-NEXT: orr.w r1, r1, r0, lsr #2939; CHECK-NON-MVE-NEXT: lsls r0, r0, #340; CHECK-NON-MVE-NEXT: bx lr41entry:42 %shl = shl i64 %x, 343 ret i64 %shl44}45 46define i64 @shift_left_imm_big(i64 %x) {47; CHECK-LABEL: shift_left_imm_big:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: lsls r1, r0, #1650; CHECK-NEXT: movs r0, #051; CHECK-NEXT: bx lr52entry:53 %shl = shl i64 %x, 4854 ret i64 %shl55}56 57define i64 @shift_left_imm_big2(i64 %x) {58; CHECK-LABEL: shift_left_imm_big2:59; CHECK: @ %bb.0: @ %entry60; CHECK-NEXT: mov r1, r061; CHECK-NEXT: movs r0, #062; CHECK-NEXT: bx lr63entry:64 %shl = shl i64 %x, 3265 ret i64 %shl66}67 68define i64 @shift_left_imm_big3(i64 %x) {69; CHECK-LABEL: shift_left_imm_big3:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: lsls r1, r0, #172; CHECK-NEXT: movs r0, #073; CHECK-NEXT: bx lr74entry:75 %shl = shl i64 %x, 3376 ret i64 %shl77}78 79define i64 @shift_right_reg(i64 %x, i64 %y) {80; CHECK-MVE-LABEL: shift_right_reg:81; CHECK-MVE: @ %bb.0: @ %entry82; CHECK-MVE-NEXT: rsbs r2, r2, #083; CHECK-MVE-NEXT: lsll r0, r1, r284; CHECK-MVE-NEXT: bx lr85;86; CHECK-NON-MVE-LABEL: shift_right_reg:87; CHECK-NON-MVE: @ %bb.0: @ %entry88; CHECK-NON-MVE-NEXT: rsb.w r3, r2, #3289; CHECK-NON-MVE-NEXT: lsrs r0, r290; CHECK-NON-MVE-NEXT: lsl.w r3, r1, r391; CHECK-NON-MVE-NEXT: orrs r0, r392; CHECK-NON-MVE-NEXT: subs.w r3, r2, #3293; CHECK-NON-MVE-NEXT: it pl94; CHECK-NON-MVE-NEXT: lsrpl.w r0, r1, r395; CHECK-NON-MVE-NEXT: lsr.w r1, r1, r296; CHECK-NON-MVE-NEXT: it pl97; CHECK-NON-MVE-NEXT: movpl r1, #098; CHECK-NON-MVE-NEXT: bx lr99entry:100 %shr = lshr i64 %x, %y101 ret i64 %shr102}103 104define i64 @shift_right_imm(i64 %x) {105; CHECK-MVE-LABEL: shift_right_imm:106; CHECK-MVE: @ %bb.0: @ %entry107; CHECK-MVE-NEXT: lsrl r0, r1, #3108; CHECK-MVE-NEXT: bx lr109;110; CHECK-NON-MVE-LABEL: shift_right_imm:111; CHECK-NON-MVE: @ %bb.0: @ %entry112; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3113; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #29114; CHECK-NON-MVE-NEXT: lsrs r1, r1, #3115; CHECK-NON-MVE-NEXT: bx lr116entry:117 %shr = lshr i64 %x, 3118 ret i64 %shr119}120 121define i64 @shift_right_imm_big(i64 %x) {122; CHECK-LABEL: shift_right_imm_big:123; CHECK: @ %bb.0: @ %entry124; CHECK-NEXT: lsrs r0, r1, #16125; CHECK-NEXT: movs r1, #0126; CHECK-NEXT: bx lr127entry:128 %shr = lshr i64 %x, 48129 ret i64 %shr130}131 132define i64 @shift_right_imm_big2(i64 %x) {133; CHECK-LABEL: shift_right_imm_big2:134; CHECK: @ %bb.0: @ %entry135; CHECK-NEXT: mov r0, r1136; CHECK-NEXT: movs r1, #0137; CHECK-NEXT: bx lr138entry:139 %shr = lshr i64 %x, 32140 ret i64 %shr141}142 143define i64 @shift_right_imm_big3(i64 %x) {144; CHECK-LABEL: shift_right_imm_big3:145; CHECK: @ %bb.0: @ %entry146; CHECK-NEXT: lsrs r0, r1, #1147; CHECK-NEXT: movs r1, #0148; CHECK-NEXT: bx lr149entry:150 %shr = lshr i64 %x, 33151 ret i64 %shr152}153 154define i64 @shift_arithmetic_right_reg(i64 %x, i64 %y) {155; CHECK-MVE-LABEL: shift_arithmetic_right_reg:156; CHECK-MVE: @ %bb.0: @ %entry157; CHECK-MVE-NEXT: asrl r0, r1, r2158; CHECK-MVE-NEXT: bx lr159;160; CHECK-NON-MVE-LABEL: shift_arithmetic_right_reg:161; CHECK-NON-MVE: @ %bb.0: @ %entry162; CHECK-NON-MVE-NEXT: rsb.w r3, r2, #32163; CHECK-NON-MVE-NEXT: lsrs r0, r2164; CHECK-NON-MVE-NEXT: lsl.w r3, r1, r3165; CHECK-NON-MVE-NEXT: orrs r0, r3166; CHECK-NON-MVE-NEXT: subs.w r3, r2, #32167; CHECK-NON-MVE-NEXT: asr.w r2, r1, r2168; CHECK-NON-MVE-NEXT: it pl169; CHECK-NON-MVE-NEXT: asrpl.w r0, r1, r3170; CHECK-NON-MVE-NEXT: it pl171; CHECK-NON-MVE-NEXT: asrpl r2, r1, #31172; CHECK-NON-MVE-NEXT: mov r1, r2173; CHECK-NON-MVE-NEXT: bx lr174entry:175 %shr = ashr i64 %x, %y176 ret i64 %shr177}178 179define i64 @shift_arithmetic_right_imm(i64 %x) {180; CHECK-MVE-LABEL: shift_arithmetic_right_imm:181; CHECK-MVE: @ %bb.0: @ %entry182; CHECK-MVE-NEXT: asrl r0, r1, #3183; CHECK-MVE-NEXT: bx lr184;185; CHECK-NON-MVE-LABEL: shift_arithmetic_right_imm:186; CHECK-NON-MVE: @ %bb.0: @ %entry187; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3188; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #29189; CHECK-NON-MVE-NEXT: asrs r1, r1, #3190; CHECK-NON-MVE-NEXT: bx lr191entry:192 %shr = ashr i64 %x, 3193 ret i64 %shr194}195 196%struct.bar = type { i16, i8, [5 x i8] }197 198define arm_aapcs_vfpcc void @fn1(ptr nocapture %a) {199; CHECK-MVE-LABEL: fn1:200; CHECK-MVE: @ %bb.0: @ %entry201; CHECK-MVE-NEXT: ldr r2, [r0, #4]202; CHECK-MVE-NEXT: movs r1, #0203; CHECK-MVE-NEXT: lsll r2, r1, #8204; CHECK-MVE-NEXT: strb r1, [r0, #7]205; CHECK-MVE-NEXT: str.w r2, [r0, #3]206; CHECK-MVE-NEXT: bx lr207;208; CHECK-NON-MVE-LABEL: fn1:209; CHECK-NON-MVE: @ %bb.0: @ %entry210; CHECK-NON-MVE-NEXT: ldr r1, [r0, #4]211; CHECK-NON-MVE-NEXT: lsrs r2, r1, #24212; CHECK-NON-MVE-NEXT: lsls r1, r1, #8213; CHECK-NON-MVE-NEXT: strb r2, [r0, #7]214; CHECK-NON-MVE-NEXT: str.w r1, [r0, #3]215; CHECK-NON-MVE-NEXT: bx lr216entry:217 %carey = getelementptr inbounds %struct.bar, ptr %a, i32 0, i32 2218 %bf.load = load i40, ptr %carey, align 1219 %bf.clear = and i40 %bf.load, -256220 store i40 %bf.clear, ptr %carey, align 1221 ret void222}223 224%struct.a = type { i96 }225 226define void @lsll_128bit_shift(ptr nocapture %x) local_unnamed_addr #0 {227; CHECK-LABEL: lsll_128bit_shift:228; CHECK: @ %bb.0: @ %entry229; CHECK-NEXT: movs r1, #0230; CHECK-NEXT: strd r1, r1, [r0]231; CHECK-NEXT: str r1, [r0, #8]232; CHECK-NEXT: bx lr233entry:234 %bf.load = load i128, ptr %x, align 8235 %bf.clear4 = and i128 %bf.load, -79228162514264337593543950336236 store i128 %bf.clear4, ptr %x, align 8237 ret void238}239 240%struct.b = type { i184 }241 242define void @lsll_256bit_shift(ptr nocapture %x) local_unnamed_addr #0 {243; CHECK-LABEL: lsll_256bit_shift:244; CHECK: @ %bb.0: @ %entry245; CHECK-NEXT: movs r1, #0246; CHECK-NEXT: str r1, [r0, #16]247; CHECK-NEXT: strd r1, r1, [r0, #8]248; CHECK-NEXT: strd r1, r1, [r0]249; CHECK-NEXT: ldrb r1, [r0, #23]250; CHECK-NEXT: lsls r1, r1, #24251; CHECK-NEXT: str r1, [r0, #20]252; CHECK-NEXT: bx lr253entry:254 %bf.load = load i192, ptr %x, align 8255 %bf.clear4 = and i192 %bf.load, -24519928653854221733733552434404946937899825954937634816256 store i192 %bf.clear4, ptr %x, align 8257 ret void258}259 260 261define i32 @ashr_demand_bottom3(i64 %x) {262; CHECK-MVE-LABEL: ashr_demand_bottom3:263; CHECK-MVE: @ %bb.0: @ %entry264; CHECK-MVE-NEXT: lsrl r0, r1, #3265; CHECK-MVE-NEXT: bx lr266;267; CHECK-NON-MVE-LABEL: ashr_demand_bottom3:268; CHECK-NON-MVE: @ %bb.0: @ %entry269; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3270; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #29271; CHECK-NON-MVE-NEXT: bx lr272entry:273 %shr = ashr i64 %x, 3274 %t = trunc i64 %shr to i32275 ret i32 %t276}277 278define i32 @lshr_demand_bottom3(i64 %x) {279; CHECK-MVE-LABEL: lshr_demand_bottom3:280; CHECK-MVE: @ %bb.0: @ %entry281; CHECK-MVE-NEXT: lsrl r0, r1, #3282; CHECK-MVE-NEXT: bx lr283;284; CHECK-NON-MVE-LABEL: lshr_demand_bottom3:285; CHECK-NON-MVE: @ %bb.0: @ %entry286; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3287; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #29288; CHECK-NON-MVE-NEXT: bx lr289entry:290 %shr = lshr i64 %x, 3291 %t = trunc i64 %shr to i32292 ret i32 %t293}294 295define i32 @lsl_demand_bottom3(i64 %x) {296; CHECK-LABEL: lsl_demand_bottom3:297; CHECK: @ %bb.0: @ %entry298; CHECK-NEXT: lsls r0, r0, #3299; CHECK-NEXT: bx lr300entry:301 %shr = shl i64 %x, 3302 %t = trunc i64 %shr to i32303 ret i32 %t304}305 306 307define i32 @ashr_demand_bottom31(i64 %x) {308; CHECK-MVE-LABEL: ashr_demand_bottom31:309; CHECK-MVE: @ %bb.0: @ %entry310; CHECK-MVE-NEXT: lsrl r0, r1, #31311; CHECK-MVE-NEXT: bx lr312;313; CHECK-NON-MVE-LABEL: ashr_demand_bottom31:314; CHECK-NON-MVE: @ %bb.0: @ %entry315; CHECK-NON-MVE-NEXT: lsrs r0, r0, #31316; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #1317; CHECK-NON-MVE-NEXT: bx lr318entry:319 %shr = ashr i64 %x, 31320 %t = trunc i64 %shr to i32321 ret i32 %t322}323 324define i32 @lshr_demand_bottom31(i64 %x) {325; CHECK-MVE-LABEL: lshr_demand_bottom31:326; CHECK-MVE: @ %bb.0: @ %entry327; CHECK-MVE-NEXT: lsrl r0, r1, #31328; CHECK-MVE-NEXT: bx lr329;330; CHECK-NON-MVE-LABEL: lshr_demand_bottom31:331; CHECK-NON-MVE: @ %bb.0: @ %entry332; CHECK-NON-MVE-NEXT: lsrs r0, r0, #31333; CHECK-NON-MVE-NEXT: orr.w r0, r0, r1, lsl #1334; CHECK-NON-MVE-NEXT: bx lr335entry:336 %shr = lshr i64 %x, 31337 %t = trunc i64 %shr to i32338 ret i32 %t339}340 341define i32 @lsl_demand_bottom31(i64 %x) {342; CHECK-LABEL: lsl_demand_bottom31:343; CHECK: @ %bb.0: @ %entry344; CHECK-NEXT: lsls r0, r0, #31345; CHECK-NEXT: bx lr346entry:347 %shr = shl i64 %x, 31348 %t = trunc i64 %shr to i32349 ret i32 %t350}351 352 353define i32 @ashr_demand_bottom32(i64 %x) {354; CHECK-LABEL: ashr_demand_bottom32:355; CHECK: @ %bb.0: @ %entry356; CHECK-NEXT: mov r0, r1357; CHECK-NEXT: bx lr358entry:359 %shr = ashr i64 %x, 32360 %t = trunc i64 %shr to i32361 ret i32 %t362}363 364define i32 @lshr_demand_bottom32(i64 %x) {365; CHECK-LABEL: lshr_demand_bottom32:366; CHECK: @ %bb.0: @ %entry367; CHECK-NEXT: mov r0, r1368; CHECK-NEXT: bx lr369entry:370 %shr = lshr i64 %x, 32371 %t = trunc i64 %shr to i32372 ret i32 %t373}374 375define i32 @lsl_demand_bottom32(i64 %x) {376; CHECK-LABEL: lsl_demand_bottom32:377; CHECK: @ %bb.0: @ %entry378; CHECK-NEXT: movs r0, #0379; CHECK-NEXT: bx lr380entry:381 %shr = shl i64 %x, 32382 %t = trunc i64 %shr to i32383 ret i32 %t384}385 386 387define i32 @ashr_demand_bottom44(i64 %x) {388; CHECK-LABEL: ashr_demand_bottom44:389; CHECK: @ %bb.0: @ %entry390; CHECK-NEXT: asrs r0, r1, #12391; CHECK-NEXT: bx lr392entry:393 %shr = ashr i64 %x, 44394 %t = trunc i64 %shr to i32395 ret i32 %t396}397 398define i32 @lshr_demand_bottom44(i64 %x) {399; CHECK-LABEL: lshr_demand_bottom44:400; CHECK: @ %bb.0: @ %entry401; CHECK-NEXT: lsrs r0, r1, #12402; CHECK-NEXT: bx lr403entry:404 %shr = lshr i64 %x, 44405 %t = trunc i64 %shr to i32406 ret i32 %t407}408 409define i32 @lsl_demand_bottom44(i64 %x) {410; CHECK-LABEL: lsl_demand_bottom44:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: movs r0, #0413; CHECK-NEXT: bx lr414entry:415 %shr = shl i64 %x, 44416 %t = trunc i64 %shr to i32417 ret i32 %t418}419 420 421define i32 @ashr_demand_bottommask(i64 %x) {422; CHECK-LABEL: ashr_demand_bottommask:423; CHECK: @ %bb.0: @ %entry424; CHECK-NEXT: lsls r0, r1, #1425; CHECK-NEXT: bx lr426entry:427 %shr = ashr i64 %x, 31428 %t = trunc i64 %shr to i32429 %a = and i32 %t, -2430 ret i32 %a431}432 433define i32 @lshr_demand_bottommask(i64 %x) {434; CHECK-LABEL: lshr_demand_bottommask:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: lsls r0, r1, #1437; CHECK-NEXT: bx lr438entry:439 %shr = lshr i64 %x, 31440 %t = trunc i64 %shr to i32441 %a = and i32 %t, -2442 ret i32 %a443}444 445define i32 @lsl_demand_bottommask(i64 %x) {446; CHECK-LABEL: lsl_demand_bottommask:447; CHECK: @ %bb.0: @ %entry448; CHECK-NEXT: lsls r0, r0, #31449; CHECK-NEXT: bx lr450entry:451 %shr = shl i64 %x, 31452 %t = trunc i64 %shr to i32453 %a = and i32 %t, -2454 ret i32 %a455}456 457define i32 @ashr_demand_bottommask2(i64 %x) {458; CHECK-LABEL: ashr_demand_bottommask2:459; CHECK: @ %bb.0: @ %entry460; CHECK-NEXT: mvn r0, #2461; CHECK-NEXT: and.w r0, r0, r1, lsl #1462; CHECK-NEXT: bx lr463entry:464 %shr = ashr i64 %x, 31465 %t = trunc i64 %shr to i32466 %a = and i32 %t, -4467 ret i32 %a468}469 470define i32 @lshr_demand_bottommask2(i64 %x) {471; CHECK-LABEL: lshr_demand_bottommask2:472; CHECK: @ %bb.0: @ %entry473; CHECK-NEXT: mvn r0, #2474; CHECK-NEXT: and.w r0, r0, r1, lsl #1475; CHECK-NEXT: bx lr476entry:477 %shr = lshr i64 %x, 31478 %t = trunc i64 %shr to i32479 %a = and i32 %t, -4480 ret i32 %a481}482 483define i32 @lsl_demand_bottommask2(i64 %x) {484; CHECK-LABEL: lsl_demand_bottommask2:485; CHECK: @ %bb.0: @ %entry486; CHECK-NEXT: lsls r0, r0, #31487; CHECK-NEXT: bx lr488entry:489 %shr = shl i64 %x, 31490 %t = trunc i64 %shr to i32491 %a = and i32 %t, -4492 ret i32 %a493}494 495define i32 @lsl_demand_topmask(i64 %x) {496; CHECK-LABEL: lsl_demand_topmask:497; CHECK: @ %bb.0: @ %entry498; CHECK-NEXT: ubfx r0, r0, #1, #28499; CHECK-NEXT: bx lr500entry:501 %sh = shl i64 %x, 31502 %a = and i64 %sh, 1152921500311879680 ;0x0fffffff00000000503 %l = ashr i64 %a, 32504 %t = trunc i64 %l to i32505 ret i32 %t506}507