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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mcpu=cortex-m85 -mattr=+use-mipipeliner -run-pass=pipeliner --pipeliner-force-issue-width=10 -o - %s | FileCheck %s --check-prefix=CHECK3 4--- |5 define hidden float @dot(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %sz) local_unnamed_addr #0 {6 entry:7 %cmp8 = icmp sgt i32 %sz, 08 br i1 %cmp8, label %for.body.preheader, label %for.end9 10 for.body.preheader: ; preds = %entry11 %scevgep = getelementptr float, ptr %b, i32 -112 %scevgep4 = getelementptr float, ptr %a, i32 -113 br label %for.body14 15 for.body: ; preds = %for.body.preheader, %for.body16 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]17 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]18 %lsr.iv = phi i32 [ %sz, %for.body.preheader ], [ %lsr.iv.next, %for.body ]19 %sum.010 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]20 %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 121 %0 = load float, ptr %scevgep7, align 422 %scevgep3 = getelementptr float, ptr %lsr.iv1, i32 123 %1 = load float, ptr %scevgep3, align 424 %mul = fmul fast float %1, %025 %add = fadd fast float %mul, %sum.01026 %lsr.iv.next = add i32 %lsr.iv, -127 %scevgep2 = getelementptr float, ptr %lsr.iv1, i32 128 %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 129 %exitcond.not = icmp eq i32 %lsr.iv.next, 030 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !031 32 for.end: ; preds = %for.body, %entry33 %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]34 ret float %sum.0.lcssa35 }36 37 !0 = distinct !{!0, !1, !2, !3}38 !1 = !{!"llvm.loop.mustprogress"}39 !2 = !{!"llvm.loop.unroll.disable"}40 !3 = !{!"llvm.loop.pipeline.initiationinterval", i32 3}41 42...43---44name: dot45alignment: 246tracksRegLiveness: true47constants:48 - id: 049 value: 'float 0.000000e+00'50 alignment: 451 isTargetSpecific: false52body: |53 ; CHECK-LABEL: name: dot54 ; CHECK: bb.0.entry:55 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000)56 ; CHECK-NEXT: liveins: $r0, $r1, $r257 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprlr = COPY $r259 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r160 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r061 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr62 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr63 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: bb.1:65 ; CHECK-NEXT: successors: %bb.4(0x80000000)66 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)68 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg69 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: bb.2.for.body.preheader:71 ; CHECK-NEXT: successors: %bb.5(0x80000000)72 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY1]], 4, 14 /* CC::al */, $noreg, $noreg74 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnopc = COPY [[t2SUBri]]75 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[COPY2]], 4, 14 /* CC::al */, $noreg, $noreg76 ; CHECK-NEXT: [[VLDRS1:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)77 ; CHECK-NEXT: [[t2DoLoopStart:%[0-9]+]]:gprlr = t2DoLoopStart [[COPY]]78 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprnopc = COPY [[t2SUBri1]]79 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: bb.5.for.body:81 ; CHECK-NEXT: successors: %bb.6(0x80000000), %bb.7(0x00000000)82 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY4]], 4, 14 /* CC::al */, $noreg, $noreg84 ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)85 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg86 ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)87 ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm88 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprlr = COPY [[t2DoLoopStart]]89 ; CHECK-NEXT: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[COPY5]], 190 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2LoopDec]]91 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2ADDri1]]92 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2ADDri]]93 ; CHECK-NEXT: t2CMPri [[t2LoopDec]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr94 ; CHECK-NEXT: t2Bcc %bb.7, 0 /* CC::eq */, $cpsr95 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg96 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: bb.6.for.body:98 ; CHECK-NEXT: successors: %bb.7(0x04000000), %bb.6(0x7c000000)99 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.5, %43, %bb.6101 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.5, %44, %bb.6102 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr = PHI [[COPY6]], %bb.5, %47, %bb.6103 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, %46, %bb.6104 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, %45, %bb.6105 ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4)106 ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4)107 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gprlr = COPY [[PHI2]]108 ; CHECK-NEXT: [[t2LoopDec1:%[0-9]+]]:gprlr = t2LoopDec [[COPY9]], 1109 ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg110 ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg111 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr = COPY [[t2ADDri2]]112 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri3]]113 ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm114 ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI4]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm115 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2LoopDec1]]116 ; CHECK-NEXT: t2LoopEnd [[t2LoopDec1]], %bb.6, implicit-def $cpsr117 ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: bb.7:120 ; CHECK-NEXT: successors: %bb.4(0x80000000)121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS]], %bb.6123 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[VMULS1]], %bb.6124 ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm125 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: bb.4.for.end:128 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS1]], %bb.7129 ; CHECK-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[PHI7]], 14 /* CC::al */, $noreg130 ; CHECK-NEXT: $r0 = COPY [[VMOVRS]]131 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0132 bb.0.entry:133 successors: %bb.1(0x50000000), %bb.4(0x30000000)134 liveins: $r0, $r1, $r2135 136 %13:gprlr = COPY $r2137 %12:gprnopc = COPY $r1138 %11:gprnopc = COPY $r0139 t2CMPri %13, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr140 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr141 142 bb.4:143 successors: %bb.3(0x80000000)144 145 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)146 t2B %bb.3, 14 /* CC::al */, $noreg147 148 bb.1.for.body.preheader:149 successors: %bb.2(0x80000000)150 151 %16:rgpr = t2SUBri %12, 4, 14 /* CC::al */, $noreg, $noreg152 %0:gpr = COPY %16153 %17:rgpr = t2SUBri %11, 4, 14 /* CC::al */, $noreg, $noreg154 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)155 %44:gprlr = t2DoLoopStart %13156 %1:gpr = COPY %17157 158 bb.2.for.body:159 successors: %bb.3(0x04000000), %bb.2(0x7c000000)160 161 %2:gprnopc = PHI %1, %bb.1, %9, %bb.2162 %3:gprnopc = PHI %0, %bb.1, %8, %bb.2163 %4:gpr = PHI %44, %bb.1, %7, %bb.2164 %5:spr = PHI %15, %bb.1, %6, %bb.2165 %18:rgpr = t2ADDri %2, 4, 14 /* CC::al */, $noreg, $noreg166 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)167 %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg168 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)169 %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm170 %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm171 %42:gprlr = COPY %4172 %23:gprlr = t2LoopDec %42:gprlr, 1173 %7:gpr = COPY %23174 %8:gpr = COPY %20175 %9:gpr = COPY %18176 t2LoopEnd %23:gprlr, %bb.2, implicit-def dead $cpsr177 t2B %bb.3, 14 /* CC::al */, $noreg178 179 bb.3.for.end:180 %10:spr = PHI %14, %bb.4, %6, %bb.2181 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg182 $r0 = COPY %24183 tBX_RET 14 /* CC::al */, $noreg, implicit $r0184 185...186