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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -run-pass=pipeliner --pipeliner-force-issue-width=10 -o - %s | FileCheck %s --check-prefix=CHECK3 4# This test checks that too much register pressure will cause the modulo5# schedule to be rejected and that a test with the same resource usage6# but without register pressure is not rejected.7 8--- |9 define hidden float @high_pressure(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %sz) local_unnamed_addr #0 {10 entry:11 %cmp8 = icmp sgt i32 %sz, 012 br i1 %cmp8, label %for.body.preheader, label %for.end13 14 for.body.preheader: ; preds = %entry15 %scevgep = getelementptr float, ptr %b, i32 -116 %scevgep4 = getelementptr float, ptr %a, i32 -117 br label %for.body18 19 for.body: ; preds = %for.body.preheader, %for.body20 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]21 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]22 %lsr.iv = phi i32 [ %sz, %for.body.preheader ], [ %lsr.iv.next, %for.body ]23 %sum.010 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]24 %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 125 %0 = load float, ptr %scevgep7, align 426 %scevgep3 = getelementptr float, ptr %lsr.iv1, i32 127 %1 = load float, ptr %scevgep3, align 428 %mul = fmul fast float %1, %029 %add = fadd fast float %mul, %sum.01030 %lsr.iv.next = add i32 %lsr.iv, -131 %scevgep2 = getelementptr float, ptr %lsr.iv1, i32 132 %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 133 %exitcond.not = icmp eq i32 %lsr.iv.next, 034 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !035 36 for.end: ; preds = %for.body, %entry37 %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]38 ret float %sum.0.lcssa39 }40 41 !0 = distinct !{!0, !1, !2, !3}42 !1 = !{!"llvm.loop.mustprogress"}43 !2 = !{!"llvm.loop.unroll.disable"}44 !3 = !{!"llvm.loop.pipeline.initiationinterval", i32 3}45 46 47 define hidden float @low_pressure(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %sz) local_unnamed_addr #0 {48 entry:49 %cmp8 = icmp sgt i32 %sz, 050 br i1 %cmp8, label %for.body.preheader, label %for.end51 52 for.body.preheader: ; preds = %entry53 %scevgep = getelementptr float, ptr %b, i32 -154 %scevgep4 = getelementptr float, ptr %a, i32 -155 br label %for.body56 57 for.body: ; preds = %for.body.preheader, %for.body58 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]59 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]60 %lsr.iv = phi i32 [ %sz, %for.body.preheader ], [ %lsr.iv.next, %for.body ]61 %sum.010 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]62 %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 163 %0 = load float, ptr %scevgep7, align 464 %scevgep3 = getelementptr float, ptr %lsr.iv1, i32 165 %1 = load float, ptr %scevgep3, align 466 %mul = fmul fast float %1, %067 %add = fadd fast float %mul, %sum.01068 %lsr.iv.next = add i32 %lsr.iv, -169 %scevgep2 = getelementptr float, ptr %lsr.iv1, i32 170 %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 171 %exitcond.not = icmp eq i32 %lsr.iv.next, 072 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !473 74 for.end: ; preds = %for.body, %entry75 %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]76 ret float %sum.0.lcssa77 }78 79 !4 = distinct !{!4, !5, !6, !7}80 !5 = !{!"llvm.loop.mustprogress"}81 !6 = !{!"llvm.loop.unroll.disable"}82 !7 = !{!"llvm.loop.pipeline.initiationinterval", i32 3}83 84...85---86name: high_pressure87alignment: 288tracksRegLiveness: true89constants:90 - id: 091 value: 'float 0.000000e+00'92 alignment: 493 isTargetSpecific: false94body: |95 ; CHECK-LABEL: name: high_pressure96 ; CHECK: bb.0.entry:97 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000)98 ; CHECK-NEXT: liveins: $r0, $r1, $r299 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r2101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1102 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r0103 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr104 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: bb.1:107 ; CHECK-NEXT: successors: %bb.4(0x80000000)108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)110 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: bb.2.for.body.preheader:113 ; CHECK-NEXT: successors: %bb.3(0x80000000)114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY1]], 4, 14 /* CC::al */, $noreg, $noreg116 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[t2SUBri]]117 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[COPY2]], 4, 14 /* CC::al */, $noreg, $noreg118 ; CHECK-NEXT: [[VLDRS1:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)119 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[t2SUBri1]]120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: bb.3.for.body:122 ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %10, %bb.3125 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY3]], %bb.2, %12, %bb.3126 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY]], %bb.2, %14, %bb.3127 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.2, %16, %bb.3128 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %18, %bb.3129 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %20, %bb.3130 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %22, %bb.3131 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %24, %bb.3132 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %26, %bb.3133 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %28, %bb.3134 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %30, %bb.3135 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %32, %bb.3136 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %34, %bb.3137 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %36, %bb.3138 ; CHECK-NEXT: [[PHI14:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %38, %bb.3139 ; CHECK-NEXT: [[PHI15:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %40, %bb.3140 ; CHECK-NEXT: [[PHI16:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %42, %bb.3141 ; CHECK-NEXT: [[PHI17:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %44, %bb.3142 ; CHECK-NEXT: [[PHI18:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %46, %bb.3143 ; CHECK-NEXT: [[PHI19:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %48, %bb.3144 ; CHECK-NEXT: [[PHI20:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %50, %bb.3145 ; CHECK-NEXT: [[PHI21:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %52, %bb.3146 ; CHECK-NEXT: [[PHI22:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %54, %bb.3147 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg148 ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)149 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg150 ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)151 ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm152 ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm153 ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr154 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY [[t2SUBri2]]155 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2ADDri1]]156 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2ADDri]]157 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:rgpr = COPY [[PHI4]]158 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:rgpr = COPY [[PHI5]]159 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:rgpr = COPY [[PHI6]]160 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:rgpr = COPY [[PHI7]]161 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:rgpr = COPY [[PHI8]]162 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:rgpr = COPY [[PHI9]]163 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:rgpr = COPY [[PHI10]]164 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:rgpr = COPY [[PHI11]]165 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:rgpr = COPY [[PHI12]]166 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:rgpr = COPY [[PHI13]]167 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:rgpr = COPY [[PHI14]]168 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:rgpr = COPY [[PHI15]]169 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:rgpr = COPY [[PHI16]]170 ; CHECK-NEXT: [[COPY21:%[0-9]+]]:rgpr = COPY [[PHI17]]171 ; CHECK-NEXT: [[COPY22:%[0-9]+]]:rgpr = COPY [[PHI18]]172 ; CHECK-NEXT: [[COPY23:%[0-9]+]]:rgpr = COPY [[PHI19]]173 ; CHECK-NEXT: [[COPY24:%[0-9]+]]:rgpr = COPY [[PHI20]]174 ; CHECK-NEXT: [[COPY25:%[0-9]+]]:rgpr = COPY [[PHI21]]175 ; CHECK-NEXT: [[COPY26:%[0-9]+]]:rgpr = COPY [[PHI22]]176 ; CHECK-NEXT: t2Bcc %bb.3, 1 /* CC::ne */, $cpsr177 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: bb.4.for.end:180 ; CHECK-NEXT: [[PHI23:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS]], %bb.3181 ; CHECK-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[PHI23]], 14 /* CC::al */, $noreg182 ; CHECK-NEXT: $r0 = COPY [[VMOVRS]]183 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0184 bb.0.entry:185 successors: %bb.1(0x50000000), %bb.4(0x30000000)186 liveins: $r0, $r1, $r2187 188 %13:gprnopc = COPY $r2189 %12:gprnopc = COPY $r1190 %11:gprnopc = COPY $r0191 t2CMPri %13, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr192 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr193 194 bb.4:195 successors: %bb.3(0x80000000)196 197 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)198 t2B %bb.3, 14 /* CC::al */, $noreg199 200 bb.1.for.body.preheader:201 successors: %bb.2(0x80000000)202 203 %16:rgpr = t2SUBri %12, 4, 14 /* CC::al */, $noreg, $noreg204 %0:gpr = COPY %16205 %17:rgpr = t2SUBri %11, 4, 14 /* CC::al */, $noreg, $noreg206 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)207 %1:gpr = COPY %17208 209 bb.2.for.body:210 successors: %bb.3(0x04000000), %bb.2(0x7c000000)211 212 %2:gprnopc = PHI %1, %bb.1, %9, %bb.2213 %3:gprnopc = PHI %0, %bb.1, %8, %bb.2214 %4:gprnopc = PHI %13, %bb.1, %7, %bb.2215 %5:spr = PHI %15, %bb.1, %6, %bb.2216 %101:gprnopc = PHI %1, %bb.1, %201, %bb.2217 %102:gprnopc = PHI %1, %bb.1, %202, %bb.2218 %103:gprnopc = PHI %1, %bb.1, %203, %bb.2219 %104:gprnopc = PHI %1, %bb.1, %204, %bb.2220 %105:gprnopc = PHI %1, %bb.1, %205, %bb.2221 %106:gprnopc = PHI %1, %bb.1, %206, %bb.2222 %107:gprnopc = PHI %1, %bb.1, %207, %bb.2223 %108:gprnopc = PHI %1, %bb.1, %208, %bb.2224 %109:gprnopc = PHI %1, %bb.1, %209, %bb.2225 %110:gprnopc = PHI %1, %bb.1, %210, %bb.2226 %111:gprnopc = PHI %1, %bb.1, %211, %bb.2227 %112:gprnopc = PHI %1, %bb.1, %212, %bb.2228 %113:gprnopc = PHI %1, %bb.1, %213, %bb.2229 %114:gprnopc = PHI %1, %bb.1, %214, %bb.2230 %115:gprnopc = PHI %1, %bb.1, %215, %bb.2231 %116:gprnopc = PHI %1, %bb.1, %216, %bb.2232 %117:gprnopc = PHI %1, %bb.1, %217, %bb.2233 %118:gprnopc = PHI %1, %bb.1, %218, %bb.2234 %119:gprnopc = PHI %1, %bb.1, %219, %bb.2235 %18:rgpr = t2ADDri %2, 4, 14 /* CC::al */, $noreg, $noreg236 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)237 %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg238 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)239 %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm240 %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm241 %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr242 %7:gpr = COPY %23243 %8:gpr = COPY %20244 %9:gpr = COPY %18245 %201:rgpr = COPY %101246 %202:rgpr = COPY %102247 %203:rgpr = COPY %103248 %204:rgpr = COPY %104249 %205:rgpr = COPY %105250 %206:rgpr = COPY %106251 %207:rgpr = COPY %107252 %208:rgpr = COPY %108253 %209:rgpr = COPY %109254 %210:rgpr = COPY %110255 %211:rgpr = COPY %111256 %212:rgpr = COPY %112257 %213:rgpr = COPY %113258 %214:rgpr = COPY %114259 %215:rgpr = COPY %115260 %216:rgpr = COPY %116261 %217:rgpr = COPY %117262 %218:rgpr = COPY %118263 %219:rgpr = COPY %119264 t2Bcc %bb.2, 1 /* CC::ne */, $cpsr265 t2B %bb.3, 14 /* CC::al */, $noreg266 267 bb.3.for.end:268 %10:spr = PHI %14, %bb.4, %6, %bb.2269 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg270 $r0 = COPY %24271 tBX_RET 14 /* CC::al */, $noreg, implicit $r0272 273 274...275---276name: low_pressure277alignment: 2278tracksRegLiveness: true279constants:280 - id: 0281 value: 'float 0.000000e+00'282 alignment: 4283 isTargetSpecific: false284body: |285 ; CHECK-LABEL: name: low_pressure286 ; CHECK: bb.0.entry:287 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000)288 ; CHECK-NEXT: liveins: $r0, $r1, $r2289 ; CHECK-NEXT: {{ $}}290 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r2291 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1292 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r0293 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr294 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr295 ; CHECK-NEXT: {{ $}}296 ; CHECK-NEXT: bb.1:297 ; CHECK-NEXT: successors: %bb.4(0x80000000)298 ; CHECK-NEXT: {{ $}}299 ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)300 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg301 ; CHECK-NEXT: {{ $}}302 ; CHECK-NEXT: bb.2.for.body.preheader:303 ; CHECK-NEXT: successors: %bb.5(0x80000000)304 ; CHECK-NEXT: {{ $}}305 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY1]], 4, 14 /* CC::al */, $noreg, $noreg306 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnopc = COPY [[t2SUBri]]307 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[COPY2]], 4, 14 /* CC::al */, $noreg, $noreg308 ; CHECK-NEXT: [[VLDRS1:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)309 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprnopc = COPY [[t2SUBri1]]310 ; CHECK-NEXT: {{ $}}311 ; CHECK-NEXT: bb.5.for.body:312 ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.9(0x40000000)313 ; CHECK-NEXT: {{ $}}314 ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr315 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]]316 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY4]]317 ; CHECK-NEXT: dead [[COPY7:%[0-9]+]]:rgpr = COPY [[COPY4]]318 ; CHECK-NEXT: dead [[COPY8:%[0-9]+]]:rgpr = COPY [[COPY4]]319 ; CHECK-NEXT: dead [[COPY9:%[0-9]+]]:rgpr = COPY [[COPY4]]320 ; CHECK-NEXT: dead [[COPY10:%[0-9]+]]:rgpr = COPY [[COPY4]]321 ; CHECK-NEXT: dead [[COPY11:%[0-9]+]]:rgpr = COPY [[COPY4]]322 ; CHECK-NEXT: dead [[COPY12:%[0-9]+]]:rgpr = COPY [[COPY4]]323 ; CHECK-NEXT: dead [[COPY13:%[0-9]+]]:rgpr = COPY [[COPY4]]324 ; CHECK-NEXT: dead [[COPY14:%[0-9]+]]:rgpr = COPY [[COPY4]]325 ; CHECK-NEXT: dead [[COPY15:%[0-9]+]]:rgpr = COPY [[COPY4]]326 ; CHECK-NEXT: dead [[COPY16:%[0-9]+]]:rgpr = COPY [[COPY4]]327 ; CHECK-NEXT: dead [[COPY17:%[0-9]+]]:rgpr = COPY [[COPY4]]328 ; CHECK-NEXT: dead [[COPY18:%[0-9]+]]:rgpr = COPY [[COPY4]]329 ; CHECK-NEXT: dead [[COPY19:%[0-9]+]]:rgpr = COPY [[COPY4]]330 ; CHECK-NEXT: dead [[COPY20:%[0-9]+]]:rgpr = COPY [[COPY4]]331 ; CHECK-NEXT: dead [[COPY21:%[0-9]+]]:rgpr = COPY [[COPY4]]332 ; CHECK-NEXT: dead [[COPY22:%[0-9]+]]:rgpr = COPY [[COPY4]]333 ; CHECK-NEXT: dead [[COPY23:%[0-9]+]]:rgpr = COPY [[COPY4]]334 ; CHECK-NEXT: dead [[COPY24:%[0-9]+]]:rgpr = COPY [[COPY4]]335 ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr336 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg337 ; CHECK-NEXT: {{ $}}338 ; CHECK-NEXT: bb.6.for.body:339 ; CHECK-NEXT: successors: %bb.7(0x80000000), %bb.8(0x00000000)340 ; CHECK-NEXT: {{ $}}341 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY4]], 4, 14 /* CC::al */, $noreg, $noreg342 ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)343 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg344 ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)345 ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm346 ; CHECK-NEXT: [[COPY25:%[0-9]+]]:gpr = COPY [[t2ADDri1]]347 ; CHECK-NEXT: [[COPY26:%[0-9]+]]:gpr = COPY [[t2ADDri]]348 ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr349 ; CHECK-NEXT: [[COPY27:%[0-9]+]]:gpr = COPY [[t2SUBri3]]350 ; CHECK-NEXT: [[COPY28:%[0-9]+]]:rgpr = COPY [[COPY6]]351 ; CHECK-NEXT: dead [[COPY29:%[0-9]+]]:rgpr = COPY [[COPY6]]352 ; CHECK-NEXT: dead [[COPY30:%[0-9]+]]:rgpr = COPY [[COPY6]]353 ; CHECK-NEXT: dead [[COPY31:%[0-9]+]]:rgpr = COPY [[COPY6]]354 ; CHECK-NEXT: dead [[COPY32:%[0-9]+]]:rgpr = COPY [[COPY6]]355 ; CHECK-NEXT: dead [[COPY33:%[0-9]+]]:rgpr = COPY [[COPY6]]356 ; CHECK-NEXT: dead [[COPY34:%[0-9]+]]:rgpr = COPY [[COPY6]]357 ; CHECK-NEXT: dead [[COPY35:%[0-9]+]]:rgpr = COPY [[COPY6]]358 ; CHECK-NEXT: dead [[COPY36:%[0-9]+]]:rgpr = COPY [[COPY6]]359 ; CHECK-NEXT: dead [[COPY37:%[0-9]+]]:rgpr = COPY [[COPY6]]360 ; CHECK-NEXT: dead [[COPY38:%[0-9]+]]:rgpr = COPY [[COPY6]]361 ; CHECK-NEXT: dead [[COPY39:%[0-9]+]]:rgpr = COPY [[COPY6]]362 ; CHECK-NEXT: dead [[COPY40:%[0-9]+]]:rgpr = COPY [[COPY6]]363 ; CHECK-NEXT: dead [[COPY41:%[0-9]+]]:rgpr = COPY [[COPY6]]364 ; CHECK-NEXT: dead [[COPY42:%[0-9]+]]:rgpr = COPY [[COPY6]]365 ; CHECK-NEXT: dead [[COPY43:%[0-9]+]]:rgpr = COPY [[COPY6]]366 ; CHECK-NEXT: dead [[COPY44:%[0-9]+]]:rgpr = COPY [[COPY6]]367 ; CHECK-NEXT: dead [[COPY45:%[0-9]+]]:rgpr = COPY [[COPY6]]368 ; CHECK-NEXT: dead [[COPY46:%[0-9]+]]:rgpr = COPY [[COPY6]]369 ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr370 ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg371 ; CHECK-NEXT: {{ $}}372 ; CHECK-NEXT: bb.7.for.body:373 ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.7(0x7c000000)374 ; CHECK-NEXT: {{ $}}375 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY26]], %bb.6, %116, %bb.7376 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY25]], %bb.6, %117, %bb.7377 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY27]], %bb.6, %140, %bb.7378 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %137, %bb.7379 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY28]], %bb.6, %139, %bb.7380 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %118, %bb.7381 ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4)382 ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4)383 ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg384 ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg385 ; CHECK-NEXT: [[COPY47:%[0-9]+]]:gpr = COPY [[t2ADDri2]]386 ; CHECK-NEXT: [[COPY48:%[0-9]+]]:gpr = COPY [[t2ADDri3]]387 ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm388 ; CHECK-NEXT: dead [[COPY49:%[0-9]+]]:rgpr = COPY [[PHI4]]389 ; CHECK-NEXT: dead [[COPY50:%[0-9]+]]:rgpr = COPY [[PHI4]]390 ; CHECK-NEXT: dead [[COPY51:%[0-9]+]]:rgpr = COPY [[PHI4]]391 ; CHECK-NEXT: dead [[COPY52:%[0-9]+]]:rgpr = COPY [[PHI4]]392 ; CHECK-NEXT: dead [[COPY53:%[0-9]+]]:rgpr = COPY [[PHI4]]393 ; CHECK-NEXT: dead [[COPY54:%[0-9]+]]:rgpr = COPY [[PHI4]]394 ; CHECK-NEXT: dead [[COPY55:%[0-9]+]]:rgpr = COPY [[PHI4]]395 ; CHECK-NEXT: dead [[COPY56:%[0-9]+]]:rgpr = COPY [[PHI4]]396 ; CHECK-NEXT: dead [[COPY57:%[0-9]+]]:rgpr = COPY [[PHI4]]397 ; CHECK-NEXT: dead [[COPY58:%[0-9]+]]:rgpr = COPY [[PHI4]]398 ; CHECK-NEXT: dead [[COPY59:%[0-9]+]]:rgpr = COPY [[PHI4]]399 ; CHECK-NEXT: dead [[COPY60:%[0-9]+]]:rgpr = COPY [[PHI4]]400 ; CHECK-NEXT: dead [[COPY61:%[0-9]+]]:rgpr = COPY [[PHI4]]401 ; CHECK-NEXT: dead [[COPY62:%[0-9]+]]:rgpr = COPY [[PHI4]]402 ; CHECK-NEXT: dead [[COPY63:%[0-9]+]]:rgpr = COPY [[PHI4]]403 ; CHECK-NEXT: dead [[COPY64:%[0-9]+]]:rgpr = COPY [[PHI4]]404 ; CHECK-NEXT: dead [[COPY65:%[0-9]+]]:rgpr = COPY [[PHI4]]405 ; CHECK-NEXT: dead [[COPY66:%[0-9]+]]:rgpr = COPY [[PHI4]]406 ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm407 ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr408 ; CHECK-NEXT: [[COPY67:%[0-9]+]]:rgpr = COPY [[PHI4]]409 ; CHECK-NEXT: [[COPY68:%[0-9]+]]:gpr = COPY [[t2SUBri4]]410 ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr411 ; CHECK-NEXT: t2B %bb.8, 14 /* CC::al */, $noreg412 ; CHECK-NEXT: {{ $}}413 ; CHECK-NEXT: bb.8:414 ; CHECK-NEXT: successors: %bb.9(0x80000000)415 ; CHECK-NEXT: {{ $}}416 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY26]], %bb.6, [[COPY47]], %bb.7417 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY25]], %bb.6, [[COPY48]], %bb.7418 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7419 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7420 ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI9]], [[PHI8]], 14 /* CC::al */, $noreg, implicit $fpscr_rm421 ; CHECK-NEXT: {{ $}}422 ; CHECK-NEXT: bb.9:423 ; CHECK-NEXT: successors: %bb.4(0x80000000)424 ; CHECK-NEXT: {{ $}}425 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.5, [[PHI6]], %bb.8426 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:gprnopc = PHI [[COPY3]], %bb.5, [[PHI7]], %bb.8427 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8428 ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI10]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4)429 ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI11]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4)430 ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS7]], [[VLDRS6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm431 ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI12]], 14 /* CC::al */, $noreg, implicit $fpscr_rm432 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg433 ; CHECK-NEXT: {{ $}}434 ; CHECK-NEXT: bb.4.for.end:435 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS2]], %bb.9436 ; CHECK-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[PHI13]], 14 /* CC::al */, $noreg437 ; CHECK-NEXT: $r0 = COPY [[VMOVRS]]438 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0439 bb.0.entry:440 successors: %bb.1(0x50000000), %bb.4(0x30000000)441 liveins: $r0, $r1, $r2442 443 %13:gprnopc = COPY $r2444 %12:gprnopc = COPY $r1445 %11:gprnopc = COPY $r0446 t2CMPri %13, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr447 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr448 449 bb.4:450 successors: %bb.3(0x80000000)451 452 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)453 t2B %bb.3, 14 /* CC::al */, $noreg454 455 bb.1.for.body.preheader:456 successors: %bb.2(0x80000000)457 458 %16:rgpr = t2SUBri %12, 4, 14 /* CC::al */, $noreg, $noreg459 %0:gpr = COPY %16460 %17:rgpr = t2SUBri %11, 4, 14 /* CC::al */, $noreg, $noreg461 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)462 %1:gpr = COPY %17463 464 bb.2.for.body:465 successors: %bb.3(0x04000000), %bb.2(0x7c000000)466 467 %2:gprnopc = PHI %1, %bb.1, %9, %bb.2468 %3:gprnopc = PHI %0, %bb.1, %8, %bb.2469 %4:gprnopc = PHI %13, %bb.1, %7, %bb.2470 %5:spr = PHI %15, %bb.1, %6, %bb.2471 %101:gprnopc = PHI %1, %bb.1, %201, %bb.2472 %102:gprnopc = PHI %1, %bb.1, %201, %bb.2473 %103:gprnopc = PHI %1, %bb.1, %201, %bb.2474 %104:gprnopc = PHI %1, %bb.1, %201, %bb.2475 %105:gprnopc = PHI %1, %bb.1, %201, %bb.2476 %106:gprnopc = PHI %1, %bb.1, %201, %bb.2477 %107:gprnopc = PHI %1, %bb.1, %201, %bb.2478 %108:gprnopc = PHI %1, %bb.1, %201, %bb.2479 %109:gprnopc = PHI %1, %bb.1, %201, %bb.2480 %110:gprnopc = PHI %1, %bb.1, %201, %bb.2481 %111:gprnopc = PHI %1, %bb.1, %201, %bb.2482 %112:gprnopc = PHI %1, %bb.1, %201, %bb.2483 %113:gprnopc = PHI %1, %bb.1, %201, %bb.2484 %114:gprnopc = PHI %1, %bb.1, %201, %bb.2485 %115:gprnopc = PHI %1, %bb.1, %201, %bb.2486 %116:gprnopc = PHI %1, %bb.1, %201, %bb.2487 %117:gprnopc = PHI %1, %bb.1, %201, %bb.2488 %118:gprnopc = PHI %1, %bb.1, %201, %bb.2489 %119:gprnopc = PHI %1, %bb.1, %201, %bb.2490 %18:rgpr = t2ADDri %2, 4, 14 /* CC::al */, $noreg, $noreg491 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)492 %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg493 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)494 %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm495 %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm496 %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr497 %7:gpr = COPY %23498 %8:gpr = COPY %20499 %9:gpr = COPY %18500 %201:rgpr = COPY %101501 %202:rgpr = COPY %101502 %203:rgpr = COPY %101503 %204:rgpr = COPY %101504 %205:rgpr = COPY %101505 %206:rgpr = COPY %101506 %207:rgpr = COPY %101507 %208:rgpr = COPY %101508 %209:rgpr = COPY %101509 %210:rgpr = COPY %101510 %211:rgpr = COPY %101511 %212:rgpr = COPY %101512 %213:rgpr = COPY %101513 %214:rgpr = COPY %101514 %215:rgpr = COPY %101515 %216:rgpr = COPY %101516 %217:rgpr = COPY %101517 %218:rgpr = COPY %101518 %219:rgpr = COPY %101519 t2Bcc %bb.2, 1 /* CC::ne */, $cpsr520 t2B %bb.3, 14 /* CC::al */, $noreg521 522 bb.3.for.end:523 %10:spr = PHI %14, %bb.4, %6, %bb.2524 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg525 $r0 = COPY %24526 tBX_RET 14 /* CC::al */, $noreg, implicit $r0527 528...529