105 lines · plain
1; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=A82; RUN: llc -mtriple=thumb-eabi -mcpu=swift %s -o - | FileCheck %s --check-prefix=SWIFT3 4; rdar://128927075 6define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) {7; A8: t2ADDrs_lsl8; A8: add.w r0, r0, r1, lsl #169 %A = shl i32 %Y, 1610 %B = add i32 %X, %A11 ret i32 %B12}13 14define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) {15; A8: t2ADDrs_lsr16; A8: add.w r0, r0, r1, lsr #1617 %A = lshr i32 %Y, 1618 %B = add i32 %X, %A19 ret i32 %B20}21 22define i32 @t2ADDrs_asr(i32 %X, i32 %Y) {23; A8: t2ADDrs_asr24; A8: add.w r0, r0, r1, asr #1625 %A = ashr i32 %Y, 1626 %B = add i32 %X, %A27 ret i32 %B28}29 30; i32 ror(n) = (x >> n) | (x << (32 - n))31define i32 @t2ADDrs_ror(i32 %X, i32 %Y) {32; A8: t2ADDrs_ror33; A8: add.w r0, r0, r1, ror #1634 %A = lshr i32 %Y, 1635 %B = shl i32 %Y, 1636 %C = or i32 %B, %A37 %R = add i32 %X, %C38 ret i32 %R39}40 41define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) {42; A8: t2ADDrs_noRegShift43; A8: uxtb r2, r244; A8: lsls r1, r245; A8: add r0, r146 47; SWIFT: t2ADDrs_noRegShift48; SWIFT-NOT: lsls49; SWIFT: lsl.w50 %shift.upgrd.1 = zext i8 %sh to i3251 %A = shl i32 %Y, %shift.upgrd.152 %B = add i32 %X, %A53 ret i32 %B54}55 56define i32 @t2ADDrs_noRegShift2(i32 %X, i32 %Y, i8 %sh) {57; A8: t2ADDrs_noRegShift258; A8: uxtb r2, r259; A8: lsrs r1, r260; A8: add r0, r161 62; SWIFT: t2ADDrs_noRegShift263; SWIFT-NOT: lsrs64; SWIFT: lsr.w65 %shift.upgrd.1 = zext i8 %sh to i3266 %A = lshr i32 %Y, %shift.upgrd.167 %B = add i32 %X, %A68 ret i32 %B69}70 71define i32 @t2ADDrs_noRegShift3(i32 %X, i32 %Y, i8 %sh) {72; A8: t2ADDrs_noRegShift373; A8: uxtb r2, r274; A8: asrs r1, r275; A8: add r0, r176 77; SWIFT: t2ADDrs_noRegShift378; SWIFT-NOT: asrs79; SWIFT: asr.w80 %shift.upgrd.1 = zext i8 %sh to i3281 %A = ashr i32 %Y, %shift.upgrd.182 %B = add i32 %X, %A83 ret i32 %B84}85 86define i32 @t2ADDrs_optsize(i32 %X, i32 %Y, i8 %sh) optsize {87; SWIFT: t2ADDrs_optsize88; SWIFT-NOT: lsl.w89; SWIFT: lsls90 %shift.upgrd.1 = zext i8 %sh to i3291 %A = shl i32 %Y, %shift.upgrd.192 %B = add i32 %X, %A93 ret i32 %B94}95 96define i32 @t2ADDrs_minsize(i32 %X, i32 %Y, i8 %sh) minsize {97; SWIFT: t2ADDrs_minsize98; SWIFT-NOT: lsr.w99; SWIFT: lsrs100 %shift.upgrd.1 = zext i8 %sh to i32101 %A = lshr i32 %Y, %shift.upgrd.1102 %B = add i32 %X, %A103 ret i32 %B104}105