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1; RUN: llc < %s -mtriple=thumbv7-elf -mattr=+neon -arm-atomic-cfg-tidy=0 | FileCheck %s2; PR47893 4%bar = type { float, float, float }5%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }6%foo = type { <4 x float> }7%quux = type { ptr, ptr, i32 }8%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }9 10declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly11 12define void @aaa(ptr %this, ptr %block) {13; CHECK-LABEL: aaa:14; CHECK: bfc r4, #0, #415; CHECK: vst1.64 {{.*}}[{{.*}}:128]16; CHECK: vld1.64 {{.*}}[{{.*}}:128]17entry:18 %aligned_vec = alloca <4 x float>, align 1619 %"alloca point" = bitcast i32 0 to i3220 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %aligned_vec, i32 1) nounwind 21 store float 6.300000e+01, ptr undef, align 422 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind ; <<4 x float>> [#uses=1]23 store float 0.000000e+00, ptr undef, align 424 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind ; <<4 x float>> [#uses=1]25 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind26 store float 0.000000e+00, ptr undef, align 427 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind28 store float 0.000000e+00, ptr undef, align 429 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind30 store float 0.000000e+00, ptr undef, align 431 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind32 store float 0.000000e+00, ptr undef, align 433 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind34 store float 0.000000e+00, ptr undef, align 435 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind36 store float 0.000000e+00, ptr undef, align 437 %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind38 store float 0.000000e+00, ptr undef, align 439 %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind40 store float 0.000000e+00, ptr undef, align 441 %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind42 store float 0.000000e+00, ptr undef, align 443 %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind44 store float 0.000000e+00, ptr undef, align 445 %val173 = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1]46 br label %bb447 48bb4: ; preds = %bb193, %entry49 %besterror.0.2264 = phi <4 x float> [ undef, %entry ], [ %besterror.0.0, %bb193 ] ; <<4 x float>> [#uses=2]50 %part0.0.0261 = phi <4 x float> [ zeroinitializer, %entry ], [ %23, %bb193 ] ; <<4 x float>> [#uses=2]51 %3 = fmul <4 x float> zeroinitializer, %0 ; <<4 x float>> [#uses=2]52 %4 = fadd <4 x float> %3, %part0.0.0261 ; <<4 x float>> [#uses=1]53 %5 = shufflevector <4 x float> %3, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]54 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]55 %7 = fmul <4 x float> %1, %156 %8 = fadd <4 x float> %7, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]57 %9 = fptosi <4 x float> %8 to <4 x i32> ; <<4 x i32>> [#uses=1]58 %10 = sitofp <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]59 %11 = fmul <4 x float> %10, %2 ; <<4 x float>> [#uses=1]60 %12 = fmul <4 x float> %6, %661 %13 = fmul <4 x float> %11, %4 ; <<4 x float>> [#uses=1]62 %14 = fsub <4 x float> %12, %13 ; <<4 x float>> [#uses=1]63 %15 = fsub <4 x float> %14, %1464 %16 = fmul <4 x float> %15, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1]65 %17 = fadd <4 x float> %16, %1666 %18 = fmul <4 x float> %17, %val173 ; <<4 x float>> [#uses=1]67 %19 = shufflevector <4 x float> %18, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]68 %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]69 %tmp1 = fadd <4 x float> %20, %ld370 %tmp2 = fadd <4 x float> %tmp1, %ld471 %tmp3 = fadd <4 x float> %tmp2, %ld572 %tmp4 = fadd <4 x float> %tmp3, %ld673 %tmp5 = fadd <4 x float> %tmp4, %ld774 %tmp6 = fadd <4 x float> %tmp5, %ld875 %tmp7 = fadd <4 x float> %tmp6, %ld976 %tmp8 = fadd <4 x float> %tmp7, %ld1077 %tmp9 = fadd <4 x float> %tmp8, %ld1178 %21 = fadd <4 x float> %tmp9, %ld1279 %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0]80 %tmp = extractelement <4 x i1> %22, i32 081 br i1 %tmp, label %bb193, label %bb18682 83bb186: ; preds = %bb484 br label %bb19385 86bb193: ; preds = %bb186, %bb487 %besterror.0.0 = phi <4 x float> [ %21, %bb186 ], [ %besterror.0.2264, %bb4 ] ; <<4 x float>> [#uses=1]88 %23 = fadd <4 x float> %part0.0.0261, zeroinitializer ; <<4 x float>> [#uses=1]89 br label %bb490}91