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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-DSP3; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DSP4; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP5; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-NO-DSP6; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP7; rdar://113184388 9define zeroext i8 @test1(i32 %A.u) {10; CHECK-LABEL: test1:11; CHECK: @ %bb.0:12; CHECK-NEXT: uxtb r0, r013; CHECK-NEXT: bx lr14 %B.u = trunc i32 %A.u to i815 ret i8 %B.u16}17 18define zeroext i32 @test2(i32 %A.u, i32 %B.u) {19; CHECK-DSP-LABEL: test2:20; CHECK-DSP: @ %bb.0:21; CHECK-DSP-NEXT: uxtab r0, r0, r122; CHECK-DSP-NEXT: bx lr23;24; CHECK-NO-DSP-LABEL: test2:25; CHECK-NO-DSP: @ %bb.0:26; CHECK-NO-DSP-NEXT: uxtb r1, r127; CHECK-NO-DSP-NEXT: add r0, r128; CHECK-NO-DSP-NEXT: bx lr29 %C.u = trunc i32 %B.u to i830 %D.u = zext i8 %C.u to i3231 %E.u = add i32 %A.u, %D.u32 ret i32 %E.u33}34 35define zeroext i32 @test3(i32 %A.u) {36; CHECK-LABEL: test3:37; CHECK: @ %bb.0:38; CHECK-NEXT: ubfx r0, r0, #8, #1639; CHECK-NEXT: bx lr40 %B.u = lshr i32 %A.u, 841 %C.u = shl i32 %A.u, 2442 %D.u = or i32 %B.u, %C.u43 %E.u = trunc i32 %D.u to i1644 %F.u = zext i16 %E.u to i3245 ret i32 %F.u46}47 48define i32 @test4(i32 %A, i32 %X) {49; CHECK-DSP-LABEL: test4:50; CHECK-DSP: @ %bb.0:51; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #1652; CHECK-DSP-NEXT: bx lr53;54; CHECK-NO-DSP-LABEL: test4:55; CHECK-NO-DSP: @ %bb.0:56; CHECK-NO-DSP-NEXT: ubfx r1, r1, #16, #857; CHECK-NO-DSP-NEXT: add r0, r158; CHECK-NO-DSP-NEXT: bx lr59 %X.hi = lshr i32 %X, 1660 %X.trunc = trunc i32 %X.hi to i861 %addend = zext i8 %X.trunc to i3262 %sum = add i32 %A, %addend63 ret i32 %sum64}65 66define i32 @test5(i32 %A, i32 %X) {67; CHECK-DSP-LABEL: test5:68; CHECK-DSP: @ %bb.0:69; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #870; CHECK-DSP-NEXT: bx lr71;72; CHECK-NO-DSP-LABEL: test5:73; CHECK-NO-DSP: @ %bb.0:74; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #1675; CHECK-NO-DSP-NEXT: add r0, r176; CHECK-NO-DSP-NEXT: bx lr77 %X.hi = lshr i32 %X, 878 %X.trunc = trunc i32 %X.hi to i1679 %addend = zext i16 %X.trunc to i3280 %sum = add i32 %A, %addend81 ret i32 %sum82}83 84define i32 @test6(i32 %A, i32 %X) {85; CHECK-DSP-LABEL: test6:86; CHECK-DSP: @ %bb.0:87; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #888; CHECK-DSP-NEXT: bx lr89;90; CHECK-NO-DSP-LABEL: test6:91; CHECK-NO-DSP: @ %bb.0:92; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #893; CHECK-NO-DSP-NEXT: add r0, r194; CHECK-NO-DSP-NEXT: bx lr95 %X.hi = lshr i32 %X, 896 %X.trunc = trunc i32 %X.hi to i897 %addend = zext i8 %X.trunc to i3298 %sum = add i32 %A, %addend99 ret i32 %sum100}101 102define i32 @test7(i32 %A, i32 %X) {103; CHECK-DSP-LABEL: test7:104; CHECK-DSP: @ %bb.0:105; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24106; CHECK-DSP-NEXT: bx lr107;108; CHECK-NO-DSP-LABEL: test7:109; CHECK-NO-DSP: @ %bb.0:110; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24111; CHECK-NO-DSP-NEXT: uxth r1, r1112; CHECK-NO-DSP-NEXT: add r0, r1113; CHECK-NO-DSP-NEXT: bx lr114 %lshr = lshr i32 %X, 24115 %shl = shl i32 %X, 8116 %or = or i32 %lshr, %shl117 %trunc = trunc i32 %or to i16118 %zext = zext i16 %trunc to i32119 %add = add i32 %A, %zext120 ret i32 %add121}122 123define i32 @test8(i32 %A, i32 %X) {124; CHECK-DSP-LABEL: test8:125; CHECK-DSP: @ %bb.0:126; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24127; CHECK-DSP-NEXT: bx lr128;129; CHECK-NO-DSP-LABEL: test8:130; CHECK-NO-DSP: @ %bb.0:131; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24132; CHECK-NO-DSP-NEXT: uxth r1, r1133; CHECK-NO-DSP-NEXT: add r0, r1134; CHECK-NO-DSP-NEXT: bx lr135 %lshr = lshr i32 %X, 24136 %shl = shl i32 %X, 8137 %or = or i32 %lshr, %shl138 %and = and i32 %or, 65535139 %add = add i32 %A, %and140 ret i32 %add141}142