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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s3 4define fastcc <512 x i32> @brd_v512i32(i32 %s) {5; CHECK-LABEL: brd_v512i32:6; CHECK: # %bb.0:7; CHECK-NEXT: and %s0, %s0, (32)08; CHECK-NEXT: sll %s1, %s0, 329; CHECK-NEXT: and %s0, %s0, (32)010; CHECK-NEXT: or %s0, %s0, %s111; CHECK-NEXT: lea %s1, 25612; CHECK-NEXT: lvl %s113; CHECK-NEXT: vbrd %v0, %s014; CHECK-NEXT: b.l.t (, %s10)15 %val = insertelement <512 x i32> undef, i32 %s, i32 016 %ret = shufflevector <512 x i32> %val, <512 x i32> undef, <512 x i32> zeroinitializer17 ret <512 x i32> %ret18}19 20define fastcc <512 x i32> @brdi_v512i32() {21; CHECK-LABEL: brdi_v512i32:22; CHECK: # %bb.0:23; CHECK-NEXT: or %s0, 17, (0)124; CHECK-NEXT: sll %s1, %s0, 3225; CHECK-NEXT: and %s0, %s0, (32)026; CHECK-NEXT: or %s0, %s0, %s127; CHECK-NEXT: lea %s1, 25628; CHECK-NEXT: lvl %s129; CHECK-NEXT: vbrd %v0, %s030; CHECK-NEXT: b.l.t (, %s10)31 %val = insertelement <512 x i32> undef, i32 17, i32 032 %ret = shufflevector <512 x i32> %val, <512 x i32> undef, <512 x i32> zeroinitializer33 ret <512 x i32> %ret34}35 36define fastcc <512 x float> @brd_v512f32(float %s) {37; CHECK-LABEL: brd_v512f32:38; CHECK: # %bb.0:39; CHECK-NEXT: and %s1, %s0, (32)140; CHECK-NEXT: srl %s0, %s0, 3241; CHECK-NEXT: or %s0, %s0, %s142; CHECK-NEXT: lea %s1, 25643; CHECK-NEXT: lvl %s144; CHECK-NEXT: vbrd %v0, %s045; CHECK-NEXT: b.l.t (, %s10)46 %val = insertelement <512 x float> undef, float %s, i32 047 %ret = shufflevector <512 x float> %val, <512 x float> undef, <512 x i32> zeroinitializer48 ret <512 x float> %ret49}50 51define fastcc <512 x float> @brdi_v512f32() {52; CHECK-LABEL: brdi_v512f32:53; CHECK: # %bb.0:54; CHECK-NEXT: lea.sl %s0, 055; CHECK-NEXT: and %s1, %s0, (32)156; CHECK-NEXT: srl %s0, %s0, 3257; CHECK-NEXT: or %s0, %s0, %s158; CHECK-NEXT: lea %s1, 25659; CHECK-NEXT: lvl %s160; CHECK-NEXT: vbrd %v0, %s061; CHECK-NEXT: b.l.t (, %s10)62 %val = insertelement <512 x float> undef, float 0.e+00, i32 063 %ret = shufflevector <512 x float> %val, <512 x float> undef, <512 x i32> zeroinitializer64 ret <512 x float> %ret65}66