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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <512 x i32> @llvm.vp.add.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)5 6define fastcc <512 x i32> @test_vp_add_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {7; CHECK-LABEL: test_vp_add_v512i32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: adds.w.sx %s0, 1, %s010; CHECK-NEXT: and %s0, %s0, (32)011; CHECK-NEXT: srl %s0, %s0, 112; CHECK-NEXT: lvl %s013; CHECK-NEXT: pvaddu %v0, %v0, %v1, %vm214; CHECK-NEXT: b.l.t (, %s10)15 %r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)16 ret <512 x i32> %r017}18 19define fastcc <512 x i32> @test_vp_add_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {20; CHECK-LABEL: test_vp_add_v512i32_rv:21; CHECK: # %bb.0:22; CHECK-NEXT: and %s0, %s0, (32)023; CHECK-NEXT: sll %s2, %s0, 3224; CHECK-NEXT: and %s0, %s0, (32)025; CHECK-NEXT: or %s0, %s0, %s226; CHECK-NEXT: adds.w.sx %s1, 1, %s127; CHECK-NEXT: and %s1, %s1, (32)028; CHECK-NEXT: srl %s1, %s1, 129; CHECK-NEXT: lvl %s130; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm231; CHECK-NEXT: b.l.t (, %s10)32 %xins = insertelement <512 x i32> undef, i32 %s0, i32 033 %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer34 %r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)35 ret <512 x i32> %r036}37 38define fastcc <512 x i32> @test_vp_add_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {39; CHECK-LABEL: test_vp_add_v512i32_vr:40; CHECK: # %bb.0:41; CHECK-NEXT: and %s0, %s0, (32)042; CHECK-NEXT: sll %s2, %s0, 3243; CHECK-NEXT: and %s0, %s0, (32)044; CHECK-NEXT: or %s0, %s0, %s245; CHECK-NEXT: adds.w.sx %s1, 1, %s146; CHECK-NEXT: and %s1, %s1, (32)047; CHECK-NEXT: srl %s1, %s1, 148; CHECK-NEXT: lvl %s149; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm250; CHECK-NEXT: b.l.t (, %s10)51 %yins = insertelement <512 x i32> undef, i32 %s1, i32 052 %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer53 %r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)54 ret <512 x i32> %r055}56