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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <512 x float> @llvm.vp.fmul.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)5 6define fastcc <512 x float> @test_vp_fmul_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {7; CHECK-LABEL: test_vp_fmul_v512f32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: adds.w.sx %s0, 1, %s010; CHECK-NEXT: and %s0, %s0, (32)011; CHECK-NEXT: srl %s0, %s0, 112; CHECK-NEXT: lvl %s013; CHECK-NEXT: pvfmul %v0, %v0, %v1, %vm214; CHECK-NEXT: b.l.t (, %s10)15 %r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)16 ret <512 x float> %r017}18 19define fastcc <512 x float> @test_vp_fmul_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {20; CHECK-LABEL: test_vp_fmul_v512f32_rv:21; CHECK: # %bb.0:22; CHECK-NEXT: and %s2, %s0, (32)123; CHECK-NEXT: srl %s0, %s0, 3224; CHECK-NEXT: or %s0, %s0, %s225; CHECK-NEXT: adds.w.sx %s1, 1, %s126; CHECK-NEXT: and %s1, %s1, (32)027; CHECK-NEXT: srl %s1, %s1, 128; CHECK-NEXT: lvl %s129; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm230; CHECK-NEXT: b.l.t (, %s10)31 %xins = insertelement <512 x float> undef, float %s0, i32 032 %i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer33 %r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)34 ret <512 x float> %r035}36 37define fastcc <512 x float> @test_vp_fmul_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {38; CHECK-LABEL: test_vp_fmul_v512f32_vr:39; CHECK: # %bb.0:40; CHECK-NEXT: and %s2, %s0, (32)141; CHECK-NEXT: srl %s0, %s0, 3242; CHECK-NEXT: or %s0, %s0, %s243; CHECK-NEXT: adds.w.sx %s1, 1, %s144; CHECK-NEXT: and %s1, %s1, (32)045; CHECK-NEXT: srl %s1, %s1, 146; CHECK-NEXT: lvl %s147; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm248; CHECK-NEXT: b.l.t (, %s10)49 %yins = insertelement <512 x float> undef, float %s1, i32 050 %i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer51 %r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)52 ret <512 x float> %r053}54