86 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <512 x i32> @llvm.vp.sdiv.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)5 6define fastcc <512 x i32> @test_vp_sdiv_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {7; CHECK-LABEL: test_vp_sdiv_v512i32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: adds.w.sx %s1, 1, %s010; CHECK-NEXT: and %s1, %s1, (32)011; CHECK-NEXT: srl %s1, %s1, 112; CHECK-NEXT: lvl %s113; CHECK-NEXT: vshf %v2, %v1, %v1, 014; CHECK-NEXT: vshf %v3, %v0, %v0, 015; CHECK-NEXT: vdivs.w.sx %v2, %v3, %v2, %vm216; CHECK-NEXT: and %s0, %s0, (32)017; CHECK-NEXT: srl %s0, %s0, 118; CHECK-NEXT: lvl %s019; CHECK-NEXT: vdivs.w.sx %v0, %v0, %v1, %vm320; CHECK-NEXT: lvl %s121; CHECK-NEXT: vshf %v0, %v0, %v2, 1322; CHECK-NEXT: b.l.t (, %s10)23 %r0 = call <512 x i32> @llvm.vp.sdiv.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)24 ret <512 x i32> %r025}26 27define fastcc <512 x i32> @test_vp_sdiv_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {28; CHECK-LABEL: test_vp_sdiv_v512i32_rv:29; CHECK: # %bb.0:30; CHECK-NEXT: and %s0, %s0, (32)031; CHECK-NEXT: sll %s2, %s0, 3232; CHECK-NEXT: and %s0, %s0, (32)033; CHECK-NEXT: or %s0, %s0, %s234; CHECK-NEXT: lea %s2, 25635; CHECK-NEXT: lvl %s236; CHECK-NEXT: vbrd %v1, %s037; CHECK-NEXT: adds.w.sx %s0, 1, %s138; CHECK-NEXT: and %s0, %s0, (32)039; CHECK-NEXT: srl %s0, %s0, 140; CHECK-NEXT: lvl %s041; CHECK-NEXT: vshf %v2, %v1, %v1, 042; CHECK-NEXT: vshf %v3, %v0, %v0, 043; CHECK-NEXT: vdivs.w.sx %v2, %v2, %v3, %vm244; CHECK-NEXT: and %s1, %s1, (32)045; CHECK-NEXT: srl %s1, %s1, 146; CHECK-NEXT: lvl %s147; CHECK-NEXT: vdivs.w.sx %v0, %v1, %v0, %vm348; CHECK-NEXT: lvl %s049; CHECK-NEXT: vshf %v0, %v0, %v2, 1350; CHECK-NEXT: b.l.t (, %s10)51 %xins = insertelement <512 x i32> undef, i32 %s0, i32 052 %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer53 %r0 = call <512 x i32> @llvm.vp.sdiv.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)54 ret <512 x i32> %r055}56 57define fastcc <512 x i32> @test_vp_sdiv_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {58; CHECK-LABEL: test_vp_sdiv_v512i32_vr:59; CHECK: # %bb.0:60; CHECK-NEXT: and %s0, %s0, (32)061; CHECK-NEXT: sll %s2, %s0, 3262; CHECK-NEXT: and %s0, %s0, (32)063; CHECK-NEXT: or %s0, %s0, %s264; CHECK-NEXT: lea %s2, 25665; CHECK-NEXT: lvl %s266; CHECK-NEXT: vbrd %v1, %s067; CHECK-NEXT: adds.w.sx %s0, 1, %s168; CHECK-NEXT: and %s0, %s0, (32)069; CHECK-NEXT: srl %s0, %s0, 170; CHECK-NEXT: lvl %s071; CHECK-NEXT: vshf %v2, %v1, %v1, 072; CHECK-NEXT: vshf %v3, %v0, %v0, 073; CHECK-NEXT: vdivs.w.sx %v2, %v3, %v2, %vm274; CHECK-NEXT: and %s1, %s1, (32)075; CHECK-NEXT: srl %s1, %s1, 176; CHECK-NEXT: lvl %s177; CHECK-NEXT: vdivs.w.sx %v0, %v0, %v1, %vm378; CHECK-NEXT: lvl %s079; CHECK-NEXT: vshf %v0, %v0, %v2, 1380; CHECK-NEXT: b.l.t (, %s10)81 %yins = insertelement <512 x i32> undef, i32 %s1, i32 082 %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer83 %r0 = call <512 x i32> @llvm.vp.sdiv.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)84 ret <512 x i32> %r085}86