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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s3 4define double @maxf64(double, double) {5; CHECK-LABEL: maxf64:6; CHECK: # %bb.0:7; CHECK-NEXT: fcmp.d %s2, %s0, %s18; CHECK-NEXT: cmov.d.gt %s1, %s0, %s29; CHECK-NEXT: or %s0, 0, %s110; CHECK-NEXT: b.l.t (, %s10)11 %3 = fcmp ogt double %0, %112 %4 = select i1 %3, double %0, double %113 ret double %414}15 16define double @maxf64_fast(double, double) {17; CHECK-LABEL: maxf64_fast:18; CHECK: # %bb.0:19; CHECK-NEXT: fmax.d %s0, %s0, %s120; CHECK-NEXT: b.l.t (, %s10)21 %3 = fcmp ogt double %0, %122 %4 = select nnan nsz i1 %3, double %0, double %123 ret double %424}25 26define double @max2f64(double, double) {27; CHECK-LABEL: max2f64:28; CHECK: # %bb.0:29; CHECK-NEXT: fcmp.d %s2, %s0, %s130; CHECK-NEXT: cmov.d.ge %s1, %s0, %s231; CHECK-NEXT: or %s0, 0, %s132; CHECK-NEXT: b.l.t (, %s10)33 %3 = fcmp oge double %0, %134 %4 = select i1 %3, double %0, double %135 ret double %436}37 38define double @max2f64_fast(double, double) {39; CHECK-LABEL: max2f64_fast:40; CHECK: # %bb.0:41; CHECK-NEXT: fmax.d %s0, %s0, %s142; CHECK-NEXT: b.l.t (, %s10)43 %3 = fcmp oge double %0, %144 %4 = select nnan nsz i1 %3, double %0, double %145 ret double %446}47 48; VE has no max for unordered comparison49define double @maxuf64(double, double) {50; CHECK-LABEL: maxuf64:51; CHECK: # %bb.0:52; CHECK-NEXT: fcmp.d %s2, %s0, %s153; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s254; CHECK-NEXT: or %s0, 0, %s155; CHECK-NEXT: b.l.t (, %s10)56 %3 = fcmp ugt double %0, %157 %4 = select i1 %3, double %0, double %158 ret double %459}60 61define double @maxuf64_fast(double, double) {62; CHECK-LABEL: maxuf64_fast:63; CHECK: # %bb.0:64; CHECK-NEXT: fmax.d %s0, %s0, %s165; CHECK-NEXT: b.l.t (, %s10)66 %3 = fcmp ugt double %0, %167 %4 = select nnan nsz i1 %3, double %0, double %168 ret double %469}70 71; VE has no max for unordered comparison72define double @max2uf64(double, double) {73; CHECK-LABEL: max2uf64:74; CHECK: # %bb.0:75; CHECK-NEXT: fcmp.d %s2, %s0, %s176; CHECK-NEXT: cmov.d.genan %s1, %s0, %s277; CHECK-NEXT: or %s0, 0, %s178; CHECK-NEXT: b.l.t (, %s10)79 %3 = fcmp uge double %0, %180 %4 = select i1 %3, double %0, double %181 ret double %482}83 84define double @max2uf64_fast(double, double) {85; CHECK-LABEL: max2uf64_fast:86; CHECK: # %bb.0:87; CHECK-NEXT: fmax.d %s0, %s0, %s188; CHECK-NEXT: b.l.t (, %s10)89 %3 = fcmp uge double %0, %190 %4 = select nnan nsz i1 %3, double %0, double %191 ret double %492}93 94define float @maxf32(float, float) {95; CHECK-LABEL: maxf32:96; CHECK: # %bb.0:97; CHECK-NEXT: fcmp.s %s2, %s0, %s198; CHECK-NEXT: cmov.s.gt %s1, %s0, %s299; CHECK-NEXT: or %s0, 0, %s1100; CHECK-NEXT: b.l.t (, %s10)101 %3 = fcmp ogt float %0, %1102 %4 = select i1 %3, float %0, float %1103 ret float %4104}105 106define float @maxf32_fast(float, float) {107; CHECK-LABEL: maxf32_fast:108; CHECK: # %bb.0:109; CHECK-NEXT: fmax.s %s0, %s0, %s1110; CHECK-NEXT: b.l.t (, %s10)111 %3 = fcmp ogt float %0, %1112 %4 = select nnan nsz i1 %3, float %0, float %1113 ret float %4114}115 116define float @max2f32(float, float) {117; CHECK-LABEL: max2f32:118; CHECK: # %bb.0:119; CHECK-NEXT: fcmp.s %s2, %s0, %s1120; CHECK-NEXT: cmov.s.ge %s1, %s0, %s2121; CHECK-NEXT: or %s0, 0, %s1122; CHECK-NEXT: b.l.t (, %s10)123 %3 = fcmp oge float %0, %1124 %4 = select i1 %3, float %0, float %1125 ret float %4126}127 128define float @max2f32_fast(float, float) {129; CHECK-LABEL: max2f32_fast:130; CHECK: # %bb.0:131; CHECK-NEXT: fmax.s %s0, %s0, %s1132; CHECK-NEXT: b.l.t (, %s10)133 %3 = fcmp oge float %0, %1134 %4 = select nnan nsz i1 %3, float %0, float %1135 ret float %4136}137 138define float @maxuf32(float, float) {139; CHECK-LABEL: maxuf32:140; CHECK: # %bb.0:141; CHECK-NEXT: fcmp.s %s2, %s0, %s1142; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2143; CHECK-NEXT: or %s0, 0, %s1144; CHECK-NEXT: b.l.t (, %s10)145 %3 = fcmp ugt float %0, %1146 %4 = select i1 %3, float %0, float %1147 ret float %4148}149 150define float @maxuf32_fast(float, float) {151; CHECK-LABEL: maxuf32_fast:152; CHECK: # %bb.0:153; CHECK-NEXT: fmax.s %s0, %s0, %s1154; CHECK-NEXT: b.l.t (, %s10)155 %3 = fcmp ugt float %0, %1156 %4 = select nnan nsz i1 %3, float %0, float %1157 ret float %4158}159 160define float @max2uf32(float, float) {161; CHECK-LABEL: max2uf32:162; CHECK: # %bb.0:163; CHECK-NEXT: fcmp.s %s2, %s0, %s1164; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2165; CHECK-NEXT: or %s0, 0, %s1166; CHECK-NEXT: b.l.t (, %s10)167 %3 = fcmp uge float %0, %1168 %4 = select i1 %3, float %0, float %1169 ret float %4170}171 172define float @max2uf32_fast(float, float) {173; CHECK-LABEL: max2uf32_fast:174; CHECK: # %bb.0:175; CHECK-NEXT: fmax.s %s0, %s0, %s1176; CHECK-NEXT: b.l.t (, %s10)177 %3 = fcmp uge float %0, %1178 %4 = select nnan nsz i1 %3, float %0, float %1179 ret float %4180}181 182define i64 @maxi64(i64, i64) {183; CHECK-LABEL: maxi64:184; CHECK: # %bb.0:185; CHECK-NEXT: maxs.l %s0, %s0, %s1186; CHECK-NEXT: b.l.t (, %s10)187 %3 = icmp sgt i64 %0, %1188 %4 = select i1 %3, i64 %0, i64 %1189 ret i64 %4190}191 192define i64 @max2i64(i64, i64) {193; CHECK-LABEL: max2i64:194; CHECK: # %bb.0:195; CHECK-NEXT: maxs.l %s0, %s0, %s1196; CHECK-NEXT: b.l.t (, %s10)197 %3 = icmp sge i64 %0, %1198 %4 = select i1 %3, i64 %0, i64 %1199 ret i64 %4200}201 202define i64 @maxu64(i64, i64) {203; CHECK-LABEL: maxu64:204; CHECK: # %bb.0:205; CHECK-NEXT: cmpu.l %s2, %s0, %s1206; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2207; CHECK-NEXT: or %s0, 0, %s1208; CHECK-NEXT: b.l.t (, %s10)209 %3 = icmp ugt i64 %0, %1210 %4 = select i1 %3, i64 %0, i64 %1211 ret i64 %4212}213 214define i64 @max2u64(i64, i64) {215; CHECK-LABEL: max2u64:216; CHECK: # %bb.0:217; CHECK-NEXT: cmpu.l %s2, %s0, %s1218; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2219; CHECK-NEXT: or %s0, 0, %s1220; CHECK-NEXT: b.l.t (, %s10)221 %3 = icmp uge i64 %0, %1222 %4 = select i1 %3, i64 %0, i64 %1223 ret i64 %4224}225 226define i32 @maxi32(i32, i32) {227; CHECK-LABEL: maxi32:228; CHECK: # %bb.0:229; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1230; CHECK-NEXT: b.l.t (, %s10)231 %3 = icmp sgt i32 %0, %1232 %4 = select i1 %3, i32 %0, i32 %1233 ret i32 %4234}235 236define i32 @max2i32(i32, i32) {237; CHECK-LABEL: max2i32:238; CHECK: # %bb.0:239; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1240; CHECK-NEXT: b.l.t (, %s10)241 %3 = icmp sge i32 %0, %1242 %4 = select i1 %3, i32 %0, i32 %1243 ret i32 %4244}245 246define i32 @maxu32(i32, i32) {247; CHECK-LABEL: maxu32:248; CHECK: # %bb.0:249; CHECK-NEXT: cmpu.w %s2, %s0, %s1250; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2251; CHECK-NEXT: or %s0, 0, %s1252; CHECK-NEXT: b.l.t (, %s10)253 %3 = icmp ugt i32 %0, %1254 %4 = select i1 %3, i32 %0, i32 %1255 ret i32 %4256}257 258define i32 @max2u32(i32, i32) {259; CHECK-LABEL: max2u32:260; CHECK: # %bb.0:261; CHECK-NEXT: cmpu.w %s2, %s0, %s1262; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2263; CHECK-NEXT: or %s0, 0, %s1264; CHECK-NEXT: b.l.t (, %s10)265 %3 = icmp uge i32 %0, %1266 %4 = select i1 %3, i32 %0, i32 %1267 ret i32 %4268}269 270define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {271; CHECK-LABEL: maxi1:272; CHECK: # %bb.0:273; CHECK-NEXT: or %s0, %s0, %s1274; CHECK-NEXT: and %s0, 1, %s0275; CHECK-NEXT: b.l.t (, %s10)276 %3 = xor i1 %1, true277 %4 = and i1 %3, %0278 %5 = select i1 %4, i1 %0, i1 %1279 ret i1 %5280}281