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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s3 4define double @minf64(double, double) {5; CHECK-LABEL: minf64:6; CHECK: # %bb.0:7; CHECK-NEXT: fcmp.d %s2, %s0, %s18; CHECK-NEXT: cmov.d.lt %s1, %s0, %s29; CHECK-NEXT: or %s0, 0, %s110; CHECK-NEXT: b.l.t (, %s10)11 %3 = fcmp olt double %0, %112 %4 = select i1 %3, double %0, double %113 ret double %414}15 16define double @minf64_fast(double, double) {17; CHECK-LABEL: minf64_fast:18; CHECK: # %bb.0:19; CHECK-NEXT: fmin.d %s0, %s0, %s120; CHECK-NEXT: b.l.t (, %s10)21 %3 = fcmp olt double %0, %122 %4 = select nnan nsz i1 %3, double %0, double %123 ret double %424}25 26define double @min2f64(double, double) {27; CHECK-LABEL: min2f64:28; CHECK: # %bb.0:29; CHECK-NEXT: fcmp.d %s2, %s0, %s130; CHECK-NEXT: cmov.d.le %s1, %s0, %s231; CHECK-NEXT: or %s0, 0, %s132; CHECK-NEXT: b.l.t (, %s10)33 %3 = fcmp ole double %0, %134 %4 = select i1 %3, double %0, double %135 ret double %436}37 38define double @min2f64_fast(double, double) {39; CHECK-LABEL: min2f64_fast:40; CHECK: # %bb.0:41; CHECK-NEXT: fmin.d %s0, %s0, %s142; CHECK-NEXT: b.l.t (, %s10)43 %3 = fcmp ole double %0, %144 %4 = select nnan nsz i1 %3, double %0, double %145 ret double %446}47 48define double @minuf64(double, double) {49; CHECK-LABEL: minuf64:50; CHECK: # %bb.0:51; CHECK-NEXT: fcmp.d %s2, %s0, %s152; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s253; CHECK-NEXT: or %s0, 0, %s154; CHECK-NEXT: b.l.t (, %s10)55 %3 = fcmp ult double %0, %156 %4 = select i1 %3, double %0, double %157 ret double %458}59 60define double @minuf64_fast(double, double) {61; CHECK-LABEL: minuf64_fast:62; CHECK: # %bb.0:63; CHECK-NEXT: fmin.d %s0, %s0, %s164; CHECK-NEXT: b.l.t (, %s10)65 %3 = fcmp ult double %0, %166 %4 = select nnan nsz i1 %3, double %0, double %167 ret double %468}69 70define double @min2uf64(double, double) {71; CHECK-LABEL: min2uf64:72; CHECK: # %bb.0:73; CHECK-NEXT: fcmp.d %s2, %s0, %s174; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s275; CHECK-NEXT: or %s0, 0, %s176; CHECK-NEXT: b.l.t (, %s10)77 %3 = fcmp ule double %0, %178 %4 = select i1 %3, double %0, double %179 ret double %480}81 82define double @min2uf64_fast(double, double) {83; CHECK-LABEL: min2uf64_fast:84; CHECK: # %bb.0:85; CHECK-NEXT: fmin.d %s0, %s0, %s186; CHECK-NEXT: b.l.t (, %s10)87 %3 = fcmp ule double %0, %188 %4 = select nnan nsz i1 %3, double %0, double %189 ret double %490}91 92define float @minf32(float, float) {93; CHECK-LABEL: minf32:94; CHECK: # %bb.0:95; CHECK-NEXT: fcmp.s %s2, %s0, %s196; CHECK-NEXT: cmov.s.lt %s1, %s0, %s297; CHECK-NEXT: or %s0, 0, %s198; CHECK-NEXT: b.l.t (, %s10)99 %3 = fcmp olt float %0, %1100 %4 = select i1 %3, float %0, float %1101 ret float %4102}103 104define float @minf32_fast(float, float) {105; CHECK-LABEL: minf32_fast:106; CHECK: # %bb.0:107; CHECK-NEXT: fmin.s %s0, %s0, %s1108; CHECK-NEXT: b.l.t (, %s10)109 %3 = fcmp olt float %0, %1110 %4 = select nnan nsz i1 %3, float %0, float %1111 ret float %4112}113 114define float @min2f32(float, float) {115; CHECK-LABEL: min2f32:116; CHECK: # %bb.0:117; CHECK-NEXT: fcmp.s %s2, %s0, %s1118; CHECK-NEXT: cmov.s.le %s1, %s0, %s2119; CHECK-NEXT: or %s0, 0, %s1120; CHECK-NEXT: b.l.t (, %s10)121 %3 = fcmp ole float %0, %1122 %4 = select i1 %3, float %0, float %1123 ret float %4124}125 126define float @min2f32_fast(float, float) {127; CHECK-LABEL: min2f32_fast:128; CHECK: # %bb.0:129; CHECK-NEXT: fmin.s %s0, %s0, %s1130; CHECK-NEXT: b.l.t (, %s10)131 %3 = fcmp ole float %0, %1132 %4 = select nnan nsz i1 %3, float %0, float %1133 ret float %4134}135 136define float @minuf32(float, float) {137; CHECK-LABEL: minuf32:138; CHECK: # %bb.0:139; CHECK-NEXT: fcmp.s %s2, %s0, %s1140; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2141; CHECK-NEXT: or %s0, 0, %s1142; CHECK-NEXT: b.l.t (, %s10)143 %3 = fcmp ult float %0, %1144 %4 = select i1 %3, float %0, float %1145 ret float %4146}147 148define float @minuf32_fast(float, float) {149; CHECK-LABEL: minuf32_fast:150; CHECK: # %bb.0:151; CHECK-NEXT: fmin.s %s0, %s0, %s1152; CHECK-NEXT: b.l.t (, %s10)153 %3 = fcmp ult float %0, %1154 %4 = select nnan nsz i1 %3, float %0, float %1155 ret float %4156}157 158define float @min2uf32(float, float) {159; CHECK-LABEL: min2uf32:160; CHECK: # %bb.0:161; CHECK-NEXT: fcmp.s %s2, %s0, %s1162; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2163; CHECK-NEXT: or %s0, 0, %s1164; CHECK-NEXT: b.l.t (, %s10)165 %3 = fcmp ule float %0, %1166 %4 = select i1 %3, float %0, float %1167 ret float %4168}169 170define float @min2uf32_fast(float, float) {171; CHECK-LABEL: min2uf32_fast:172; CHECK: # %bb.0:173; CHECK-NEXT: fmin.s %s0, %s0, %s1174; CHECK-NEXT: b.l.t (, %s10)175 %3 = fcmp ule float %0, %1176 %4 = select nnan nsz i1 %3, float %0, float %1177 ret float %4178}179 180define i64 @mini64(i64, i64) {181; CHECK-LABEL: mini64:182; CHECK: # %bb.0:183; CHECK-NEXT: mins.l %s0, %s0, %s1184; CHECK-NEXT: b.l.t (, %s10)185 %3 = icmp slt i64 %0, %1186 %4 = select i1 %3, i64 %0, i64 %1187 ret i64 %4188}189 190define i64 @min2i64(i64, i64) {191; CHECK-LABEL: min2i64:192; CHECK: # %bb.0:193; CHECK-NEXT: mins.l %s0, %s0, %s1194; CHECK-NEXT: b.l.t (, %s10)195 %3 = icmp sle i64 %0, %1196 %4 = select i1 %3, i64 %0, i64 %1197 ret i64 %4198}199 200define i64 @minu64(i64, i64) {201; CHECK-LABEL: minu64:202; CHECK: # %bb.0:203; CHECK-NEXT: cmpu.l %s2, %s0, %s1204; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2205; CHECK-NEXT: or %s0, 0, %s1206; CHECK-NEXT: b.l.t (, %s10)207 %3 = icmp ult i64 %0, %1208 %4 = select i1 %3, i64 %0, i64 %1209 ret i64 %4210}211 212define i64 @min2u64(i64, i64) {213; CHECK-LABEL: min2u64:214; CHECK: # %bb.0:215; CHECK-NEXT: cmpu.l %s2, %s0, %s1216; CHECK-NEXT: cmov.l.le %s1, %s0, %s2217; CHECK-NEXT: or %s0, 0, %s1218; CHECK-NEXT: b.l.t (, %s10)219 %3 = icmp ule i64 %0, %1220 %4 = select i1 %3, i64 %0, i64 %1221 ret i64 %4222}223 224define i32 @mini32(i32, i32) {225; CHECK-LABEL: mini32:226; CHECK: # %bb.0:227; CHECK-NEXT: mins.w.sx %s0, %s0, %s1228; CHECK-NEXT: b.l.t (, %s10)229 %3 = icmp slt i32 %0, %1230 %4 = select i1 %3, i32 %0, i32 %1231 ret i32 %4232}233 234define i32 @min2i32(i32, i32) {235; CHECK-LABEL: min2i32:236; CHECK: # %bb.0:237; CHECK-NEXT: mins.w.sx %s0, %s0, %s1238; CHECK-NEXT: b.l.t (, %s10)239 %3 = icmp sle i32 %0, %1240 %4 = select i1 %3, i32 %0, i32 %1241 ret i32 %4242}243 244define i32 @minu32(i32, i32) {245; CHECK-LABEL: minu32:246; CHECK: # %bb.0:247; CHECK-NEXT: cmpu.w %s2, %s0, %s1248; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2249; CHECK-NEXT: or %s0, 0, %s1250; CHECK-NEXT: b.l.t (, %s10)251 %3 = icmp ult i32 %0, %1252 %4 = select i1 %3, i32 %0, i32 %1253 ret i32 %4254}255 256define i32 @min2u32(i32, i32) {257; CHECK-LABEL: min2u32:258; CHECK: # %bb.0:259; CHECK-NEXT: cmpu.w %s2, %s0, %s1260; CHECK-NEXT: cmov.w.le %s1, %s0, %s2261; CHECK-NEXT: or %s0, 0, %s1262; CHECK-NEXT: b.l.t (, %s10)263 %3 = icmp ule i32 %0, %1264 %4 = select i1 %3, i32 %0, i32 %1265 ret i32 %4266}267 268define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {269; CHECK-LABEL: mini1:270; CHECK: # %bb.0:271; CHECK-NEXT: and %s2, 1, %s0272; CHECK-NEXT: and %s0, %s1, %s0273; CHECK-NEXT: cmov.w.ne %s0, %s1, %s2274; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1275; CHECK-NEXT: b.l.t (, %s10)276 %3 = xor i1 %0, true277 %4 = and i1 %3, %1278 %5 = select i1 %4, i1 %0, i1 %1279 ret i1 %5280}281