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1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test intrinsics for communication register4;;;5;;; Note:6;;; We test LCR, SCR, TSCR, and FIDCR instructions.7 8; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn9define i64 @lcr_sss(i64 noundef %0, i64 noundef %1) {10; CHECK-LABEL: lcr_sss:11; CHECK: # %bb.0:12; CHECK-NEXT: lcr %s0, %s0, %s113; CHECK-NEXT: b.l.t (, %s10)14 %3 = tail call i64 @llvm.ve.vl.lcr.sss(i64 %0, i64 %1)15 ret i64 %316}17 18; Function Attrs: nofree nosync nounwind readnone19declare i64 @llvm.ve.vl.lcr.sss(i64, i64)20 21; Function Attrs: nounwind22define void @scr_sss(i64 noundef %0, i64 noundef %1, i64 noundef %2) {23; CHECK-LABEL: scr_sss:24; CHECK: # %bb.0:25; CHECK-NEXT: scr %s0, %s1, %s226; CHECK-NEXT: b.l.t (, %s10)27 tail call void @llvm.ve.vl.scr.sss(i64 %0, i64 %1, i64 %2)28 ret void29}30 31; Function Attrs: nounwind32declare void @llvm.ve.vl.scr.sss(i64, i64, i64)33 34; Function Attrs: nounwind35define i64 @tscr_ssss(i64 noundef %0, i64 noundef %1, i64 noundef %2) {36; CHECK-LABEL: tscr_ssss:37; CHECK: # %bb.0:38; CHECK-NEXT: tscr %s0, %s1, %s239; CHECK-NEXT: b.l.t (, %s10)40 %4 = tail call i64 @llvm.ve.vl.tscr.ssss(i64 %0, i64 %1, i64 %2)41 ret i64 %442}43 44; Function Attrs: nounwind45declare i64 @llvm.ve.vl.tscr.ssss(i64, i64, i64)46 47; Function Attrs: nounwind48define i64 @fidcr_ss0(i64 noundef %0) {49; CHECK-LABEL: fidcr_ss0:50; CHECK: # %bb.0:51; CHECK-NEXT: fidcr %s0, %s0, 052; CHECK-NEXT: b.l.t (, %s10)53 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 0)54 ret i64 %255}56 57; Function Attrs: nounwind58declare i64 @llvm.ve.vl.fidcr.sss(i64, i32)59 60; Function Attrs: nounwind61define i64 @fidcr_ss1(i64 noundef %0) {62; CHECK-LABEL: fidcr_ss1:63; CHECK: # %bb.0:64; CHECK-NEXT: fidcr %s0, %s0, 165; CHECK-NEXT: b.l.t (, %s10)66 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 1)67 ret i64 %268}69 70; Function Attrs: nounwind71define i64 @fidcr_ss2(i64 noundef %0) {72; CHECK-LABEL: fidcr_ss2:73; CHECK: # %bb.0:74; CHECK-NEXT: fidcr %s0, %s0, 275; CHECK-NEXT: b.l.t (, %s10)76 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 2)77 ret i64 %278}79 80; Function Attrs: nounwind81define i64 @fidcr_ss3(i64 noundef %0) {82; CHECK-LABEL: fidcr_ss3:83; CHECK: # %bb.0:84; CHECK-NEXT: fidcr %s0, %s0, 385; CHECK-NEXT: b.l.t (, %s10)86 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 3)87 ret i64 %288}89 90; Function Attrs: nounwind91define i64 @fidcr_ss4(i64 noundef %0) {92; CHECK-LABEL: fidcr_ss4:93; CHECK: # %bb.0:94; CHECK-NEXT: fidcr %s0, %s0, 495; CHECK-NEXT: b.l.t (, %s10)96 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 4)97 ret i64 %298}99 100; Function Attrs: nounwind101define i64 @fidcr_ss5(i64 noundef %0) {102; CHECK-LABEL: fidcr_ss5:103; CHECK: # %bb.0:104; CHECK-NEXT: fidcr %s0, %s0, 5105; CHECK-NEXT: b.l.t (, %s10)106 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 5)107 ret i64 %2108}109 110; Function Attrs: nounwind111define i64 @fidcr_ss6(i64 noundef %0) {112; CHECK-LABEL: fidcr_ss6:113; CHECK: # %bb.0:114; CHECK-NEXT: fidcr %s0, %s0, 6115; CHECK-NEXT: b.l.t (, %s10)116 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 6)117 ret i64 %2118}119 120; Function Attrs: nounwind121define i64 @fidcr_ss7(i64 noundef %0) {122; CHECK-LABEL: fidcr_ss7:123; CHECK: # %bb.0:124; CHECK-NEXT: fidcr %s0, %s0, 7125; CHECK-NEXT: b.l.t (, %s10)126 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 7)127 ret i64 %2128}129 130!2 = !{!"clang version 15.0.0 (git@kaz7.github.com:sx-aurora-dev/llvm-project.git e0c5640dba6e9ba1cd29ed8d59b85c6378e48ac7)"}131