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1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test prefetch vector intrinsic instructions4;;;5;;; Note:6;;; We test PFCHVrrl, PFCHVirl, PFCHVNCrrl, and PFCHVNCirl instructions.7 8; Function Attrs: nounwind9define void @pfchv_vssl(ptr %0, i64 %1) {10; CHECK-LABEL: pfchv_vssl:11; CHECK: # %bb.0:12; CHECK-NEXT: lea %s2, 25613; CHECK-NEXT: lvl %s214; CHECK-NEXT: pfchv %s1, %s015; CHECK-NEXT: b.l.t (, %s10)16 tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, ptr %0, i32 256)17 ret void18}19 20; Function Attrs: inaccessiblemem_or_argmemonly nounwind21declare void @llvm.ve.vl.pfchv.ssl(i64, ptr, i32)22 23; Function Attrs: nounwind24define void @pfchv_vssl_imm(ptr %0) {25; CHECK-LABEL: pfchv_vssl_imm:26; CHECK: # %bb.0:27; CHECK-NEXT: lea %s1, 25628; CHECK-NEXT: lvl %s129; CHECK-NEXT: pfchv 8, %s030; CHECK-NEXT: b.l.t (, %s10)31 tail call void @llvm.ve.vl.pfchv.ssl(i64 8, ptr %0, i32 256)32 ret void33}34 35; Function Attrs: nounwind36define void @pfchvnc_vssl(ptr %0, i64 %1) {37; CHECK-LABEL: pfchvnc_vssl:38; CHECK: # %bb.0:39; CHECK-NEXT: lea %s2, 25640; CHECK-NEXT: lvl %s241; CHECK-NEXT: pfchv.nc %s1, %s042; CHECK-NEXT: b.l.t (, %s10)43 tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, ptr %0, i32 256)44 ret void45}46 47; Function Attrs: inaccessiblemem_or_argmemonly nounwind48declare void @llvm.ve.vl.pfchvnc.ssl(i64, ptr, i32)49 50; Function Attrs: nounwind51define void @pfchvnc_vssl_imm(ptr %0) {52; CHECK-LABEL: pfchvnc_vssl_imm:53; CHECK: # %bb.0:54; CHECK-NEXT: lea %s1, 25655; CHECK-NEXT: lvl %s156; CHECK-NEXT: pfchv.nc 8, %s057; CHECK-NEXT: b.l.t (, %s10)58 tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, ptr %0, i32 256)59 ret void60}61