439 lines · plain
1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector broadcast intrinsic instructions4;;;5;;; Note:6;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, and VLD*irl_v instructions.7 8; Function Attrs: nounwind9define void @vbrdd_vsl(double %0, ptr %1) {10; CHECK-LABEL: vbrdd_vsl:11; CHECK: # %bb.0:12; CHECK-NEXT: lea %s2, 25613; CHECK-NEXT: lvl %s214; CHECK-NEXT: vbrd %v0, %s015; CHECK-NEXT: #APP16; CHECK-NEXT: vst %v0, 8, %s117; CHECK-NEXT: #NO_APP18; CHECK-NEXT: b.l.t (, %s10)19 %3 = tail call fast <256 x double> @llvm.ve.vl.vbrdd.vsl(double %0, i32 256)20 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)21 ret void22}23 24; Function Attrs: nounwind readnone25declare <256 x double> @llvm.ve.vl.vbrdd.vsl(double, i32)26 27; Function Attrs: nounwind28define void @vbrdd_vsvl(double %0, ptr %1) {29; CHECK-LABEL: vbrdd_vsvl:30; CHECK: # %bb.0:31; CHECK-NEXT: lea %s2, 25632; CHECK-NEXT: lvl %s233; CHECK-NEXT: vld %v0, 8, %s134; CHECK-NEXT: vbrd %v0, %s035; CHECK-NEXT: vst %v0, 8, %s136; CHECK-NEXT: b.l.t (, %s10)37 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)38 %4 = tail call fast <256 x double> @llvm.ve.vl.vbrdd.vsvl(double %0, <256 x double> %3, i32 256)39 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)40 ret void41}42 43; Function Attrs: nounwind readonly44declare <256 x double> @llvm.ve.vl.vld.vssl(i64, ptr, i32)45 46; Function Attrs: nounwind readnone47declare <256 x double> @llvm.ve.vl.vbrdd.vsvl(double, <256 x double>, i32)48 49; Function Attrs: nounwind writeonly50declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, ptr, i32)51 52; Function Attrs: nounwind53define void @vbrdd_vsmvl(double %0, ptr %1) {54; CHECK-LABEL: vbrdd_vsmvl:55; CHECK: # %bb.0:56; CHECK-NEXT: lea %s2, 25657; CHECK-NEXT: lvl %s258; CHECK-NEXT: vld %v0, 8, %s159; CHECK-NEXT: lea.sl %s3, 113875353660; CHECK-NEXT: fcmp.d %s4, %s0, %s361; CHECK-NEXT: fsub.d %s3, %s0, %s362; CHECK-NEXT: cvt.l.d.rz %s3, %s363; CHECK-NEXT: xor %s3, %s3, (1)164; CHECK-NEXT: cvt.l.d.rz %s5, %s065; CHECK-NEXT: cmov.d.lt %s3, %s5, %s466; CHECK-NEXT: lvm %vm1, 3, %s367; CHECK-NEXT: vbrd %v0, %s0, %vm168; CHECK-NEXT: vst %v0, 8, %s169; CHECK-NEXT: b.l.t (, %s10)70 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)71 %4 = fptoui double %0 to i6472 %5 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %4)73 %6 = tail call fast <256 x double> @llvm.ve.vl.vbrdd.vsmvl(double %0, <256 x i1> %5, <256 x double> %3, i32 256)74 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %6, i64 8, ptr %1, i32 256)75 ret void76}77 78; Function Attrs: nounwind readnone79declare <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1>, i64, i64)80 81; Function Attrs: nounwind readnone82declare <256 x double> @llvm.ve.vl.vbrdd.vsmvl(double, <256 x i1>, <256 x double>, i32)83 84; Function Attrs: nounwind85define void @vbrdl_vsl(i64 %0, ptr %1) {86; CHECK-LABEL: vbrdl_vsl:87; CHECK: # %bb.0:88; CHECK-NEXT: lea %s2, 25689; CHECK-NEXT: lvl %s290; CHECK-NEXT: vbrd %v0, %s091; CHECK-NEXT: #APP92; CHECK-NEXT: vst %v0, 8, %s193; CHECK-NEXT: #NO_APP94; CHECK-NEXT: b.l.t (, %s10)95 %3 = tail call fast <256 x double> @llvm.ve.vl.vbrdl.vsl(i64 %0, i32 256)96 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)97 ret void98}99 100; Function Attrs: nounwind readnone101declare <256 x double> @llvm.ve.vl.vbrdl.vsl(i64, i32)102 103; Function Attrs: nounwind104define void @vbrdl_vsvl(i64 %0, ptr %1) {105; CHECK-LABEL: vbrdl_vsvl:106; CHECK: # %bb.0:107; CHECK-NEXT: lea %s2, 256108; CHECK-NEXT: lvl %s2109; CHECK-NEXT: vld %v0, 8, %s1110; CHECK-NEXT: vbrd %v0, %s0111; CHECK-NEXT: vst %v0, 8, %s1112; CHECK-NEXT: b.l.t (, %s10)113 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)114 %4 = tail call fast <256 x double> @llvm.ve.vl.vbrdl.vsvl(i64 %0, <256 x double> %3, i32 256)115 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)116 ret void117}118 119; Function Attrs: nounwind readnone120declare <256 x double> @llvm.ve.vl.vbrdl.vsvl(i64, <256 x double>, i32)121 122; Function Attrs: nounwind123define void @vbrdl_vsmvl(i64 %0, ptr %1) {124; CHECK-LABEL: vbrdl_vsmvl:125; CHECK: # %bb.0:126; CHECK-NEXT: lea %s2, 256127; CHECK-NEXT: lvl %s2128; CHECK-NEXT: vld %v0, 8, %s1129; CHECK-NEXT: lvm %vm1, 3, %s0130; CHECK-NEXT: vbrd %v0, %s0, %vm1131; CHECK-NEXT: vst %v0, 8, %s1132; CHECK-NEXT: b.l.t (, %s10)133 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)134 %4 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %0)135 %5 = tail call fast <256 x double> @llvm.ve.vl.vbrdl.vsmvl(i64 %0, <256 x i1> %4, <256 x double> %3, i32 256)136 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %5, i64 8, ptr %1, i32 256)137 ret void138}139 140; Function Attrs: nounwind readnone141declare <256 x double> @llvm.ve.vl.vbrdl.vsmvl(i64, <256 x i1>, <256 x double>, i32)142 143; Function Attrs: nounwind144define void @vbrdl_imm_vsl(i64 %0, ptr %1) {145; CHECK-LABEL: vbrdl_imm_vsl:146; CHECK: # %bb.0:147; CHECK-NEXT: lea %s0, 256148; CHECK-NEXT: lvl %s0149; CHECK-NEXT: vbrd %v0, 31150; CHECK-NEXT: #APP151; CHECK-NEXT: vst %v0, 8, %s1152; CHECK-NEXT: #NO_APP153; CHECK-NEXT: b.l.t (, %s10)154 %3 = tail call fast <256 x double> @llvm.ve.vl.vbrdl.vsl(i64 31, i32 256)155 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)156 ret void157}158 159; Function Attrs: nounwind160define void @vbrdl_imm_vsvl(i64 %0, ptr %1) {161; CHECK-LABEL: vbrdl_imm_vsvl:162; CHECK: # %bb.0:163; CHECK-NEXT: lea %s0, 256164; CHECK-NEXT: lvl %s0165; CHECK-NEXT: vld %v0, 8, %s1166; CHECK-NEXT: vbrd %v0, 31167; CHECK-NEXT: vst %v0, 8, %s1168; CHECK-NEXT: b.l.t (, %s10)169 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)170 %4 = tail call fast <256 x double> @llvm.ve.vl.vbrdl.vsvl(i64 31, <256 x double> %3, i32 256)171 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)172 ret void173}174 175; Function Attrs: nounwind176define void @vbrdl_imm_vsmvl(i64 %0, ptr %1) {177; CHECK-LABEL: vbrdl_imm_vsmvl:178; CHECK: # %bb.0:179; CHECK-NEXT: lea %s2, 256180; CHECK-NEXT: lvl %s2181; CHECK-NEXT: vld %v0, 8, %s1182; CHECK-NEXT: lvm %vm1, 3, %s0183; CHECK-NEXT: vbrd %v0, 31, %vm1184; CHECK-NEXT: vst %v0, 8, %s1185; CHECK-NEXT: b.l.t (, %s10)186 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)187 %4 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %0)188 %5 = tail call fast <256 x double> @llvm.ve.vl.vbrdl.vsmvl(i64 31, <256 x i1> %4, <256 x double> %3, i32 256)189 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %5, i64 8, ptr %1, i32 256)190 ret void191}192 193; Function Attrs: nounwind194define void @vbrds_vsl(float %0, ptr %1) {195; CHECK-LABEL: vbrds_vsl:196; CHECK: # %bb.0:197; CHECK-NEXT: lea %s2, 256198; CHECK-NEXT: lvl %s2199; CHECK-NEXT: vbrdu %v0, %s0200; CHECK-NEXT: #APP201; CHECK-NEXT: vst %v0, 8, %s1202; CHECK-NEXT: #NO_APP203; CHECK-NEXT: b.l.t (, %s10)204 %3 = tail call fast <256 x double> @llvm.ve.vl.vbrds.vsl(float %0, i32 256)205 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)206 ret void207}208 209; Function Attrs: nounwind readnone210declare <256 x double> @llvm.ve.vl.vbrds.vsl(float, i32)211 212; Function Attrs: nounwind213define void @vbrds_vsvl(float %0, ptr %1) {214; CHECK-LABEL: vbrds_vsvl:215; CHECK: # %bb.0:216; CHECK-NEXT: lea %s2, 256217; CHECK-NEXT: lvl %s2218; CHECK-NEXT: vld %v0, 8, %s1219; CHECK-NEXT: vbrdu %v0, %s0220; CHECK-NEXT: vst %v0, 8, %s1221; CHECK-NEXT: b.l.t (, %s10)222 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)223 %4 = tail call fast <256 x double> @llvm.ve.vl.vbrds.vsvl(float %0, <256 x double> %3, i32 256)224 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)225 ret void226}227 228; Function Attrs: nounwind readnone229declare <256 x double> @llvm.ve.vl.vbrds.vsvl(float, <256 x double>, i32)230 231; Function Attrs: nounwind232define void @vbrds_vsmvl(float %0, ptr %1) {233; CHECK-LABEL: vbrds_vsmvl:234; CHECK: # %bb.0:235; CHECK-NEXT: lea %s2, 256236; CHECK-NEXT: lvl %s2237; CHECK-NEXT: vld %v0, 8, %s1238; CHECK-NEXT: lea.sl %s3, 1593835520239; CHECK-NEXT: fcmp.s %s4, %s0, %s3240; CHECK-NEXT: fsub.s %s3, %s0, %s3241; CHECK-NEXT: cvt.d.s %s3, %s3242; CHECK-NEXT: cvt.l.d.rz %s3, %s3243; CHECK-NEXT: xor %s3, %s3, (1)1244; CHECK-NEXT: cvt.d.s %s5, %s0245; CHECK-NEXT: cvt.l.d.rz %s5, %s5246; CHECK-NEXT: cmov.s.lt %s3, %s5, %s4247; CHECK-NEXT: lvm %vm1, 3, %s3248; CHECK-NEXT: vbrdu %v0, %s0, %vm1249; CHECK-NEXT: vst %v0, 8, %s1250; CHECK-NEXT: b.l.t (, %s10)251 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)252 %4 = fptoui float %0 to i64253 %5 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %4)254 %6 = tail call fast <256 x double> @llvm.ve.vl.vbrds.vsmvl(float %0, <256 x i1> %5, <256 x double> %3, i32 256)255 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %6, i64 8, ptr %1, i32 256)256 ret void257}258 259; Function Attrs: nounwind readnone260declare <256 x double> @llvm.ve.vl.vbrds.vsmvl(float, <256 x i1>, <256 x double>, i32)261 262; Function Attrs: nounwind263define void @vbrdw_vsl(i32 signext %0, ptr %1) {264; CHECK-LABEL: vbrdw_vsl:265; CHECK: # %bb.0:266; CHECK-NEXT: and %s0, %s0, (32)0267; CHECK-NEXT: lea %s2, 256268; CHECK-NEXT: lvl %s2269; CHECK-NEXT: vbrdl %v0, %s0270; CHECK-NEXT: #APP271; CHECK-NEXT: vst %v0, 8, %s1272; CHECK-NEXT: #NO_APP273; CHECK-NEXT: b.l.t (, %s10)274 %3 = tail call fast <256 x double> @llvm.ve.vl.vbrdw.vsl(i32 %0, i32 256)275 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)276 ret void277}278 279; Function Attrs: nounwind readnone280declare <256 x double> @llvm.ve.vl.vbrdw.vsl(i32, i32)281 282; Function Attrs: nounwind283define void @vbrdw_vsvl(i32 signext %0, ptr %1) {284; CHECK-LABEL: vbrdw_vsvl:285; CHECK: # %bb.0:286; CHECK-NEXT: lea %s2, 256287; CHECK-NEXT: lvl %s2288; CHECK-NEXT: vld %v0, 8, %s1289; CHECK-NEXT: and %s0, %s0, (32)0290; CHECK-NEXT: vbrdl %v0, %s0291; CHECK-NEXT: vst %v0, 8, %s1292; CHECK-NEXT: b.l.t (, %s10)293 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)294 %4 = tail call fast <256 x double> @llvm.ve.vl.vbrdw.vsvl(i32 %0, <256 x double> %3, i32 256)295 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)296 ret void297}298 299; Function Attrs: nounwind readnone300declare <256 x double> @llvm.ve.vl.vbrdw.vsvl(i32, <256 x double>, i32)301 302; Function Attrs: nounwind303define void @vbrdw_vsmvl(i32 signext %0, ptr %1) {304; CHECK-LABEL: vbrdw_vsmvl:305; CHECK: # %bb.0:306; CHECK-NEXT: lea %s2, 256307; CHECK-NEXT: lvl %s2308; CHECK-NEXT: vld %v0, 8, %s1309; CHECK-NEXT: and %s3, %s0, (32)0310; CHECK-NEXT: lvm %vm1, 3, %s0311; CHECK-NEXT: vbrdl %v0, %s3, %vm1312; CHECK-NEXT: vst %v0, 8, %s1313; CHECK-NEXT: b.l.t (, %s10)314 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)315 %4 = sext i32 %0 to i64316 %5 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %4)317 %6 = tail call fast <256 x double> @llvm.ve.vl.vbrdw.vsmvl(i32 %0, <256 x i1> %5, <256 x double> %3, i32 256)318 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %6, i64 8, ptr %1, i32 256)319 ret void320}321 322; Function Attrs: nounwind readnone323declare <256 x double> @llvm.ve.vl.vbrdw.vsmvl(i32, <256 x i1>, <256 x double>, i32)324 325; Function Attrs: nounwind326define void @vbrdw_imm_vsl(i32 signext %0, ptr %1) {327; CHECK-LABEL: vbrdw_imm_vsl:328; CHECK: # %bb.0:329; CHECK-NEXT: lea %s0, 256330; CHECK-NEXT: lvl %s0331; CHECK-NEXT: vbrdl %v0, 31332; CHECK-NEXT: #APP333; CHECK-NEXT: vst %v0, 8, %s1334; CHECK-NEXT: #NO_APP335; CHECK-NEXT: b.l.t (, %s10)336 %3 = tail call fast <256 x double> @llvm.ve.vl.vbrdw.vsl(i32 31, i32 256)337 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)338 ret void339}340 341; Function Attrs: nounwind342define void @vbrdw_imm_vsvl(i32 signext %0, ptr %1) {343; CHECK-LABEL: vbrdw_imm_vsvl:344; CHECK: # %bb.0:345; CHECK-NEXT: lea %s0, 256346; CHECK-NEXT: lvl %s0347; CHECK-NEXT: vld %v0, 8, %s1348; CHECK-NEXT: vbrdl %v0, 31349; CHECK-NEXT: vst %v0, 8, %s1350; CHECK-NEXT: b.l.t (, %s10)351 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)352 %4 = tail call fast <256 x double> @llvm.ve.vl.vbrdw.vsvl(i32 31, <256 x double> %3, i32 256)353 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)354 ret void355}356 357; Function Attrs: nounwind358define void @vbrdw_imm_vsmvl(i32 signext %0, ptr %1) {359; CHECK-LABEL: vbrdw_imm_vsmvl:360; CHECK: # %bb.0:361; CHECK-NEXT: lea %s2, 256362; CHECK-NEXT: lvl %s2363; CHECK-NEXT: vld %v0, 8, %s1364; CHECK-NEXT: lvm %vm1, 3, %s0365; CHECK-NEXT: vbrdl %v0, 31, %vm1366; CHECK-NEXT: vst %v0, 8, %s1367; CHECK-NEXT: b.l.t (, %s10)368 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)369 %4 = sext i32 %0 to i64370 %5 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %4)371 %6 = tail call fast <256 x double> @llvm.ve.vl.vbrdw.vsmvl(i32 31, <256 x i1> %5, <256 x double> %3, i32 256)372 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %6, i64 8, ptr %1, i32 256)373 ret void374}375 376; Function Attrs: nounwind377define void @pvbrd_vsl(i64 %0, ptr %1) {378; CHECK-LABEL: pvbrd_vsl:379; CHECK: # %bb.0:380; CHECK-NEXT: lea %s2, 256381; CHECK-NEXT: lvl %s2382; CHECK-NEXT: pvbrd %v0, %s0383; CHECK-NEXT: #APP384; CHECK-NEXT: vst %v0, 8, %s1385; CHECK-NEXT: #NO_APP386; CHECK-NEXT: b.l.t (, %s10)387 %3 = tail call fast <256 x double> @llvm.ve.vl.pvbrd.vsl(i64 %0, i32 256)388 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %3, ptr %1)389 ret void390}391 392; Function Attrs: nounwind readnone393declare <256 x double> @llvm.ve.vl.pvbrd.vsl(i64, i32)394 395; Function Attrs: nounwind396define void @pvbrd_vsvl(i64 %0, ptr %1) {397; CHECK-LABEL: pvbrd_vsvl:398; CHECK: # %bb.0:399; CHECK-NEXT: lea %s2, 256400; CHECK-NEXT: lvl %s2401; CHECK-NEXT: vld %v0, 8, %s1402; CHECK-NEXT: pvbrd %v0, %s0403; CHECK-NEXT: vst %v0, 8, %s1404; CHECK-NEXT: b.l.t (, %s10)405 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)406 %4 = tail call fast <256 x double> @llvm.ve.vl.pvbrd.vsvl(i64 %0, <256 x double> %3, i32 256)407 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %1, i32 256)408 ret void409}410 411; Function Attrs: nounwind readnone412declare <256 x double> @llvm.ve.vl.pvbrd.vsvl(i64, <256 x double>, i32)413 414; Function Attrs: nounwind415define void @pvbrd_vsMvl(i64 %0, ptr %1) {416; CHECK-LABEL: pvbrd_vsMvl:417; CHECK: # %bb.0:418; CHECK-NEXT: lea %s2, 256419; CHECK-NEXT: lvl %s2420; CHECK-NEXT: vld %v0, 8, %s1421; CHECK-NEXT: lvm %vm3, 1, %s0422; CHECK-NEXT: lvm %vm2, 2, %s0423; CHECK-NEXT: pvbrd %v0, %s0, %vm2424; CHECK-NEXT: vst %v0, 8, %s1425; CHECK-NEXT: b.l.t (, %s10)426 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)427 %4 = tail call <512 x i1> @llvm.ve.vl.lvm.MMss(<512 x i1> undef, i64 1, i64 %0)428 %5 = tail call <512 x i1> @llvm.ve.vl.lvm.MMss(<512 x i1> %4, i64 6, i64 %0)429 %6 = tail call fast <256 x double> @llvm.ve.vl.pvbrd.vsMvl(i64 %0, <512 x i1> %5, <256 x double> %3, i32 256)430 tail call void @llvm.ve.vl.vst.vssl(<256 x double> %6, i64 8, ptr %1, i32 256)431 ret void432}433 434; Function Attrs: nounwind readnone435declare <512 x i1> @llvm.ve.vl.lvm.MMss(<512 x i1>, i64, i64)436 437; Function Attrs: nounwind readnone438declare <256 x double> @llvm.ve.vl.pvbrd.vsMvl(i64, <512 x i1>, <256 x double>, i32)439