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1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector load intrinsic instructions4;;;5;;; Note:6;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, and VLD*irl_v instructions.7 8; Function Attrs: nounwind9define void @vld_vssl(ptr %0, i64 %1) {10; CHECK-LABEL: vld_vssl:11; CHECK: # %bb.0:12; CHECK-NEXT: lea %s2, 25613; CHECK-NEXT: lvl %s214; CHECK-NEXT: vld %v0, %s1, %s015; CHECK-NEXT: #APP16; CHECK-NEXT: vst %v0, %s1, %s017; CHECK-NEXT: #NO_APP18; CHECK-NEXT: b.l.t (, %s10)19 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, ptr %0, i32 256)20 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)21 ret void22}23 24; Function Attrs: nounwind readonly25declare <256 x double> @llvm.ve.vl.vld.vssl(i64, ptr, i32)26 27; Function Attrs: nounwind28define void @vld_vssvl(ptr %0, i64 %1, ptr %2) {29; CHECK-LABEL: vld_vssvl:30; CHECK: # %bb.0:31; CHECK-NEXT: lea %s3, 25632; CHECK-NEXT: lvl %s333; CHECK-NEXT: vld %v0, %s1, %s234; CHECK-NEXT: vld %v0, %s1, %s035; CHECK-NEXT: #APP36; CHECK-NEXT: vst %v0, %s1, %s037; CHECK-NEXT: #NO_APP38; CHECK-NEXT: b.l.t (, %s10)39 %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, ptr %2, i32 256)40 %5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)41 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)42 ret void43}44 45; Function Attrs: nounwind readonly46declare <256 x double> @llvm.ve.vl.vld.vssvl(i64, ptr, <256 x double>, i32)47 48; Function Attrs: nounwind49define void @vld_vssl_imm(ptr %0) {50; CHECK-LABEL: vld_vssl_imm:51; CHECK: # %bb.0:52; CHECK-NEXT: lea %s1, 25653; CHECK-NEXT: lvl %s154; CHECK-NEXT: vld %v0, 8, %s055; CHECK-NEXT: #APP56; CHECK-NEXT: vst %v0, 8, %s057; CHECK-NEXT: #NO_APP58; CHECK-NEXT: b.l.t (, %s10)59 %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)60 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)61 ret void62}63 64; Function Attrs: nounwind65define void @vld_vssvl_imm(ptr %0, ptr %1) {66; CHECK-LABEL: vld_vssvl_imm:67; CHECK: # %bb.0:68; CHECK-NEXT: lea %s2, 25669; CHECK-NEXT: lvl %s270; CHECK-NEXT: vld %v0, 8, %s171; CHECK-NEXT: vld %v0, 8, %s072; CHECK-NEXT: #APP73; CHECK-NEXT: vst %v0, 8, %s074; CHECK-NEXT: #NO_APP75; CHECK-NEXT: b.l.t (, %s10)76 %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %1, i32 256)77 %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)78 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)79 ret void80}81 82; Function Attrs: nounwind83define void @vldnc_vssl(ptr %0, i64 %1) {84; CHECK-LABEL: vldnc_vssl:85; CHECK: # %bb.0:86; CHECK-NEXT: lea %s2, 25687; CHECK-NEXT: lvl %s288; CHECK-NEXT: vld.nc %v0, %s1, %s089; CHECK-NEXT: #APP90; CHECK-NEXT: vst %v0, %s1, %s091; CHECK-NEXT: #NO_APP92; CHECK-NEXT: b.l.t (, %s10)93 %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, ptr %0, i32 256)94 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)95 ret void96}97 98; Function Attrs: nounwind readonly99declare <256 x double> @llvm.ve.vl.vldnc.vssl(i64, ptr, i32)100 101; Function Attrs: nounwind102define void @vldnc_vssvl(ptr %0, i64 %1, ptr %2) {103; CHECK-LABEL: vldnc_vssvl:104; CHECK: # %bb.0:105; CHECK-NEXT: lea %s3, 256106; CHECK-NEXT: lvl %s3107; CHECK-NEXT: vld.nc %v0, %s1, %s2108; CHECK-NEXT: vld.nc %v0, %s1, %s0109; CHECK-NEXT: #APP110; CHECK-NEXT: vst %v0, %s1, %s0111; CHECK-NEXT: #NO_APP112; CHECK-NEXT: b.l.t (, %s10)113 %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, ptr %2, i32 256)114 %5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)115 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)116 ret void117}118 119; Function Attrs: nounwind readonly120declare <256 x double> @llvm.ve.vl.vldnc.vssvl(i64, ptr, <256 x double>, i32)121 122; Function Attrs: nounwind123define void @vldnc_vssl_imm(ptr %0) {124; CHECK-LABEL: vldnc_vssl_imm:125; CHECK: # %bb.0:126; CHECK-NEXT: lea %s1, 256127; CHECK-NEXT: lvl %s1128; CHECK-NEXT: vld.nc %v0, 8, %s0129; CHECK-NEXT: #APP130; CHECK-NEXT: vst %v0, 8, %s0131; CHECK-NEXT: #NO_APP132; CHECK-NEXT: b.l.t (, %s10)133 %2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, ptr %0, i32 256)134 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)135 ret void136}137 138; Function Attrs: nounwind139define void @vldnc_vssvl_imm(ptr %0, ptr %1) {140; CHECK-LABEL: vldnc_vssvl_imm:141; CHECK: # %bb.0:142; CHECK-NEXT: lea %s2, 256143; CHECK-NEXT: lvl %s2144; CHECK-NEXT: vld.nc %v0, 8, %s1145; CHECK-NEXT: vld.nc %v0, 8, %s0146; CHECK-NEXT: #APP147; CHECK-NEXT: vst %v0, 8, %s0148; CHECK-NEXT: #NO_APP149; CHECK-NEXT: b.l.t (, %s10)150 %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, ptr %1, i32 256)151 %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)152 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)153 ret void154}155 156; Function Attrs: nounwind157define void @vldu_vssl(ptr %0, i64 %1) {158; CHECK-LABEL: vldu_vssl:159; CHECK: # %bb.0:160; CHECK-NEXT: lea %s2, 256161; CHECK-NEXT: lvl %s2162; CHECK-NEXT: vldu %v0, %s1, %s0163; CHECK-NEXT: #APP164; CHECK-NEXT: vst %v0, %s1, %s0165; CHECK-NEXT: #NO_APP166; CHECK-NEXT: b.l.t (, %s10)167 %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, ptr %0, i32 256)168 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)169 ret void170}171 172; Function Attrs: nounwind readonly173declare <256 x double> @llvm.ve.vl.vldu.vssl(i64, ptr, i32)174 175; Function Attrs: nounwind176define void @vldu_vssvl(ptr %0, i64 %1, ptr %2) {177; CHECK-LABEL: vldu_vssvl:178; CHECK: # %bb.0:179; CHECK-NEXT: lea %s3, 256180; CHECK-NEXT: lvl %s3181; CHECK-NEXT: vldu %v0, %s1, %s2182; CHECK-NEXT: vldu %v0, %s1, %s0183; CHECK-NEXT: #APP184; CHECK-NEXT: vst %v0, %s1, %s0185; CHECK-NEXT: #NO_APP186; CHECK-NEXT: b.l.t (, %s10)187 %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, ptr %2, i32 256)188 %5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)189 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)190 ret void191}192 193; Function Attrs: nounwind readonly194declare <256 x double> @llvm.ve.vl.vldu.vssvl(i64, ptr, <256 x double>, i32)195 196; Function Attrs: nounwind197define void @vldu_vssl_imm(ptr %0) {198; CHECK-LABEL: vldu_vssl_imm:199; CHECK: # %bb.0:200; CHECK-NEXT: lea %s1, 256201; CHECK-NEXT: lvl %s1202; CHECK-NEXT: vldu %v0, 8, %s0203; CHECK-NEXT: #APP204; CHECK-NEXT: vst %v0, 8, %s0205; CHECK-NEXT: #NO_APP206; CHECK-NEXT: b.l.t (, %s10)207 %2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, ptr %0, i32 256)208 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)209 ret void210}211 212; Function Attrs: nounwind213define void @vldu_vssvl_imm(ptr %0, ptr %1) {214; CHECK-LABEL: vldu_vssvl_imm:215; CHECK: # %bb.0:216; CHECK-NEXT: lea %s2, 256217; CHECK-NEXT: lvl %s2218; CHECK-NEXT: vldu %v0, 8, %s1219; CHECK-NEXT: vldu %v0, 8, %s0220; CHECK-NEXT: #APP221; CHECK-NEXT: vst %v0, 8, %s0222; CHECK-NEXT: #NO_APP223; CHECK-NEXT: b.l.t (, %s10)224 %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, ptr %1, i32 256)225 %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)226 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)227 ret void228}229 230; Function Attrs: nounwind231define void @vldunc_vssl(ptr %0, i64 %1) {232; CHECK-LABEL: vldunc_vssl:233; CHECK: # %bb.0:234; CHECK-NEXT: lea %s2, 256235; CHECK-NEXT: lvl %s2236; CHECK-NEXT: vldu.nc %v0, %s1, %s0237; CHECK-NEXT: #APP238; CHECK-NEXT: vst %v0, %s1, %s0239; CHECK-NEXT: #NO_APP240; CHECK-NEXT: b.l.t (, %s10)241 %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, ptr %0, i32 256)242 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)243 ret void244}245 246; Function Attrs: nounwind readonly247declare <256 x double> @llvm.ve.vl.vldunc.vssl(i64, ptr, i32)248 249; Function Attrs: nounwind250define void @vldunc_vssvl(ptr %0, i64 %1, ptr %2) {251; CHECK-LABEL: vldunc_vssvl:252; CHECK: # %bb.0:253; CHECK-NEXT: lea %s3, 256254; CHECK-NEXT: lvl %s3255; CHECK-NEXT: vldu.nc %v0, %s1, %s2256; CHECK-NEXT: vldu.nc %v0, %s1, %s0257; CHECK-NEXT: #APP258; CHECK-NEXT: vst %v0, %s1, %s0259; CHECK-NEXT: #NO_APP260; CHECK-NEXT: b.l.t (, %s10)261 %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, ptr %2, i32 256)262 %5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)263 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)264 ret void265}266 267; Function Attrs: nounwind readonly268declare <256 x double> @llvm.ve.vl.vldunc.vssvl(i64, ptr, <256 x double>, i32)269 270; Function Attrs: nounwind271define void @vldunc_vssl_imm(ptr %0) {272; CHECK-LABEL: vldunc_vssl_imm:273; CHECK: # %bb.0:274; CHECK-NEXT: lea %s1, 256275; CHECK-NEXT: lvl %s1276; CHECK-NEXT: vldu.nc %v0, 8, %s0277; CHECK-NEXT: #APP278; CHECK-NEXT: vst %v0, 8, %s0279; CHECK-NEXT: #NO_APP280; CHECK-NEXT: b.l.t (, %s10)281 %2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, ptr %0, i32 256)282 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)283 ret void284}285 286; Function Attrs: nounwind287define void @vldunc_vssvl_imm(ptr %0, ptr %1) {288; CHECK-LABEL: vldunc_vssvl_imm:289; CHECK: # %bb.0:290; CHECK-NEXT: lea %s2, 256291; CHECK-NEXT: lvl %s2292; CHECK-NEXT: vldu.nc %v0, 8, %s1293; CHECK-NEXT: vldu.nc %v0, 8, %s0294; CHECK-NEXT: #APP295; CHECK-NEXT: vst %v0, 8, %s0296; CHECK-NEXT: #NO_APP297; CHECK-NEXT: b.l.t (, %s10)298 %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, ptr %1, i32 256)299 %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)300 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)301 ret void302}303 304; Function Attrs: nounwind305define void @vldlsx_vssl(ptr %0, i64 %1) {306; CHECK-LABEL: vldlsx_vssl:307; CHECK: # %bb.0:308; CHECK-NEXT: lea %s2, 256309; CHECK-NEXT: lvl %s2310; CHECK-NEXT: vldl.sx %v0, %s1, %s0311; CHECK-NEXT: #APP312; CHECK-NEXT: vst %v0, %s1, %s0313; CHECK-NEXT: #NO_APP314; CHECK-NEXT: b.l.t (, %s10)315 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, ptr %0, i32 256)316 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)317 ret void318}319 320; Function Attrs: nounwind readonly321declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, ptr, i32)322 323; Function Attrs: nounwind324define void @vldlsx_vssvl(ptr %0, i64 %1, ptr %2) {325; CHECK-LABEL: vldlsx_vssvl:326; CHECK: # %bb.0:327; CHECK-NEXT: lea %s3, 256328; CHECK-NEXT: lvl %s3329; CHECK-NEXT: vldl.sx %v0, %s1, %s2330; CHECK-NEXT: vldl.sx %v0, %s1, %s0331; CHECK-NEXT: #APP332; CHECK-NEXT: vst %v0, %s1, %s0333; CHECK-NEXT: #NO_APP334; CHECK-NEXT: b.l.t (, %s10)335 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, ptr %2, i32 256)336 %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)337 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)338 ret void339}340 341; Function Attrs: nounwind readonly342declare <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64, ptr, <256 x double>, i32)343 344; Function Attrs: nounwind345define void @vldlsx_vssl_imm(ptr %0) {346; CHECK-LABEL: vldlsx_vssl_imm:347; CHECK: # %bb.0:348; CHECK-NEXT: lea %s1, 256349; CHECK-NEXT: lvl %s1350; CHECK-NEXT: vldl.sx %v0, 8, %s0351; CHECK-NEXT: #APP352; CHECK-NEXT: vst %v0, 8, %s0353; CHECK-NEXT: #NO_APP354; CHECK-NEXT: b.l.t (, %s10)355 %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, ptr %0, i32 256)356 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)357 ret void358}359 360; Function Attrs: nounwind361define void @vldlsx_vssvl_imm(ptr %0, ptr %1) {362; CHECK-LABEL: vldlsx_vssvl_imm:363; CHECK: # %bb.0:364; CHECK-NEXT: lea %s2, 256365; CHECK-NEXT: lvl %s2366; CHECK-NEXT: vldl.sx %v0, 8, %s1367; CHECK-NEXT: vldl.sx %v0, 8, %s0368; CHECK-NEXT: #APP369; CHECK-NEXT: vst %v0, 8, %s0370; CHECK-NEXT: #NO_APP371; CHECK-NEXT: b.l.t (, %s10)372 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, ptr %1, i32 256)373 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)374 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)375 ret void376}377 378; Function Attrs: nounwind379define void @vldlsxnc_vssl(ptr %0, i64 %1) {380; CHECK-LABEL: vldlsxnc_vssl:381; CHECK: # %bb.0:382; CHECK-NEXT: lea %s2, 256383; CHECK-NEXT: lvl %s2384; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0385; CHECK-NEXT: #APP386; CHECK-NEXT: vst %v0, %s1, %s0387; CHECK-NEXT: #NO_APP388; CHECK-NEXT: b.l.t (, %s10)389 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, ptr %0, i32 256)390 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)391 ret void392}393 394; Function Attrs: nounwind readonly395declare <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64, ptr, i32)396 397; Function Attrs: nounwind398define void @vldlsxnc_vssvl(ptr %0, i64 %1, ptr %2) {399; CHECK-LABEL: vldlsxnc_vssvl:400; CHECK: # %bb.0:401; CHECK-NEXT: lea %s3, 256402; CHECK-NEXT: lvl %s3403; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s2404; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0405; CHECK-NEXT: #APP406; CHECK-NEXT: vst %v0, %s1, %s0407; CHECK-NEXT: #NO_APP408; CHECK-NEXT: b.l.t (, %s10)409 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, ptr %2, i32 256)410 %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)411 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)412 ret void413}414 415; Function Attrs: nounwind readonly416declare <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64, ptr, <256 x double>, i32)417 418; Function Attrs: nounwind419define void @vldlsxnc_vssl_imm(ptr %0) {420; CHECK-LABEL: vldlsxnc_vssl_imm:421; CHECK: # %bb.0:422; CHECK-NEXT: lea %s1, 256423; CHECK-NEXT: lvl %s1424; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0425; CHECK-NEXT: #APP426; CHECK-NEXT: vst %v0, 8, %s0427; CHECK-NEXT: #NO_APP428; CHECK-NEXT: b.l.t (, %s10)429 %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, ptr %0, i32 256)430 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)431 ret void432}433 434; Function Attrs: nounwind435define void @vldlsxnc_vssvl_imm(ptr %0, ptr %1) {436; CHECK-LABEL: vldlsxnc_vssvl_imm:437; CHECK: # %bb.0:438; CHECK-NEXT: lea %s2, 256439; CHECK-NEXT: lvl %s2440; CHECK-NEXT: vldl.sx.nc %v0, 8, %s1441; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0442; CHECK-NEXT: #APP443; CHECK-NEXT: vst %v0, 8, %s0444; CHECK-NEXT: #NO_APP445; CHECK-NEXT: b.l.t (, %s10)446 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, ptr %1, i32 256)447 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)448 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)449 ret void450}451 452; Function Attrs: nounwind453define void @vldlzx_vssl(ptr %0, i64 %1) {454; CHECK-LABEL: vldlzx_vssl:455; CHECK: # %bb.0:456; CHECK-NEXT: lea %s2, 256457; CHECK-NEXT: lvl %s2458; CHECK-NEXT: vldl.zx %v0, %s1, %s0459; CHECK-NEXT: #APP460; CHECK-NEXT: vst %v0, %s1, %s0461; CHECK-NEXT: #NO_APP462; CHECK-NEXT: b.l.t (, %s10)463 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, ptr %0, i32 256)464 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)465 ret void466}467 468; Function Attrs: nounwind readonly469declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, ptr, i32)470 471; Function Attrs: nounwind472define void @vldlzx_vssvl(ptr %0, i64 %1, ptr %2) {473; CHECK-LABEL: vldlzx_vssvl:474; CHECK: # %bb.0:475; CHECK-NEXT: lea %s3, 256476; CHECK-NEXT: lvl %s3477; CHECK-NEXT: vldl.zx %v0, %s1, %s2478; CHECK-NEXT: vldl.zx %v0, %s1, %s0479; CHECK-NEXT: #APP480; CHECK-NEXT: vst %v0, %s1, %s0481; CHECK-NEXT: #NO_APP482; CHECK-NEXT: b.l.t (, %s10)483 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, ptr %2, i32 256)484 %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)485 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)486 ret void487}488 489; Function Attrs: nounwind readonly490declare <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64, ptr, <256 x double>, i32)491 492; Function Attrs: nounwind493define void @vldlzx_vssl_imm(ptr %0) {494; CHECK-LABEL: vldlzx_vssl_imm:495; CHECK: # %bb.0:496; CHECK-NEXT: lea %s1, 256497; CHECK-NEXT: lvl %s1498; CHECK-NEXT: vldl.zx %v0, 8, %s0499; CHECK-NEXT: #APP500; CHECK-NEXT: vst %v0, 8, %s0501; CHECK-NEXT: #NO_APP502; CHECK-NEXT: b.l.t (, %s10)503 %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, ptr %0, i32 256)504 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)505 ret void506}507 508; Function Attrs: nounwind509define void @vldlzx_vssvl_imm(ptr %0, ptr %1) {510; CHECK-LABEL: vldlzx_vssvl_imm:511; CHECK: # %bb.0:512; CHECK-NEXT: lea %s2, 256513; CHECK-NEXT: lvl %s2514; CHECK-NEXT: vldl.zx %v0, 8, %s1515; CHECK-NEXT: vldl.zx %v0, 8, %s0516; CHECK-NEXT: #APP517; CHECK-NEXT: vst %v0, 8, %s0518; CHECK-NEXT: #NO_APP519; CHECK-NEXT: b.l.t (, %s10)520 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, ptr %1, i32 256)521 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)522 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)523 ret void524}525 526; Function Attrs: nounwind527define void @vldlzxnc_vssl(ptr %0, i64 %1) {528; CHECK-LABEL: vldlzxnc_vssl:529; CHECK: # %bb.0:530; CHECK-NEXT: lea %s2, 256531; CHECK-NEXT: lvl %s2532; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0533; CHECK-NEXT: #APP534; CHECK-NEXT: vst %v0, %s1, %s0535; CHECK-NEXT: #NO_APP536; CHECK-NEXT: b.l.t (, %s10)537 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, ptr %0, i32 256)538 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)539 ret void540}541 542; Function Attrs: nounwind readonly543declare <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64, ptr, i32)544 545; Function Attrs: nounwind546define void @vldlzxnc_vssvl(ptr %0, i64 %1, ptr %2) {547; CHECK-LABEL: vldlzxnc_vssvl:548; CHECK: # %bb.0:549; CHECK-NEXT: lea %s3, 256550; CHECK-NEXT: lvl %s3551; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s2552; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0553; CHECK-NEXT: #APP554; CHECK-NEXT: vst %v0, %s1, %s0555; CHECK-NEXT: #NO_APP556; CHECK-NEXT: b.l.t (, %s10)557 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, ptr %2, i32 256)558 %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)559 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)560 ret void561}562 563; Function Attrs: nounwind readonly564declare <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64, ptr, <256 x double>, i32)565 566; Function Attrs: nounwind567define void @vldlzxnc_vssl_imm(ptr %0) {568; CHECK-LABEL: vldlzxnc_vssl_imm:569; CHECK: # %bb.0:570; CHECK-NEXT: lea %s1, 256571; CHECK-NEXT: lvl %s1572; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0573; CHECK-NEXT: #APP574; CHECK-NEXT: vst %v0, 8, %s0575; CHECK-NEXT: #NO_APP576; CHECK-NEXT: b.l.t (, %s10)577 %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, ptr %0, i32 256)578 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)579 ret void580}581 582; Function Attrs: nounwind583define void @vldlzxnc_vssvl_imm(ptr %0, ptr %1) {584; CHECK-LABEL: vldlzxnc_vssvl_imm:585; CHECK: # %bb.0:586; CHECK-NEXT: lea %s2, 256587; CHECK-NEXT: lvl %s2588; CHECK-NEXT: vldl.zx.nc %v0, 8, %s1589; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0590; CHECK-NEXT: #APP591; CHECK-NEXT: vst %v0, 8, %s0592; CHECK-NEXT: #NO_APP593; CHECK-NEXT: b.l.t (, %s10)594 %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, ptr %1, i32 256)595 %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)596 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)597 ret void598}599 600; Function Attrs: nounwind601define void @vld2d_vssl(ptr %0, i64 %1) {602; CHECK-LABEL: vld2d_vssl:603; CHECK: # %bb.0:604; CHECK-NEXT: lea %s2, 256605; CHECK-NEXT: lvl %s2606; CHECK-NEXT: vld2d %v0, %s1, %s0607; CHECK-NEXT: #APP608; CHECK-NEXT: vst %v0, %s1, %s0609; CHECK-NEXT: #NO_APP610; CHECK-NEXT: b.l.t (, %s10)611 %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, ptr %0, i32 256)612 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)613 ret void614}615 616; Function Attrs: nounwind readonly617declare <256 x double> @llvm.ve.vl.vld2d.vssl(i64, ptr, i32)618 619; Function Attrs: nounwind620define void @vld2d_vssvl(ptr %0, i64 %1, ptr %2) {621; CHECK-LABEL: vld2d_vssvl:622; CHECK: # %bb.0:623; CHECK-NEXT: lea %s3, 256624; CHECK-NEXT: lvl %s3625; CHECK-NEXT: vld2d %v0, %s1, %s2626; CHECK-NEXT: vld2d %v0, %s1, %s0627; CHECK-NEXT: #APP628; CHECK-NEXT: vst %v0, %s1, %s0629; CHECK-NEXT: #NO_APP630; CHECK-NEXT: b.l.t (, %s10)631 %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, ptr %2, i32 256)632 %5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)633 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)634 ret void635}636 637; Function Attrs: nounwind readonly638declare <256 x double> @llvm.ve.vl.vld2d.vssvl(i64, ptr, <256 x double>, i32)639 640; Function Attrs: nounwind641define void @vld2d_vssl_imm(ptr %0) {642; CHECK-LABEL: vld2d_vssl_imm:643; CHECK: # %bb.0:644; CHECK-NEXT: lea %s1, 256645; CHECK-NEXT: lvl %s1646; CHECK-NEXT: vld2d %v0, 8, %s0647; CHECK-NEXT: #APP648; CHECK-NEXT: vst %v0, 8, %s0649; CHECK-NEXT: #NO_APP650; CHECK-NEXT: b.l.t (, %s10)651 %2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, ptr %0, i32 256)652 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)653 ret void654}655 656; Function Attrs: nounwind657define void @vld2d_vssvl_imm(ptr %0, ptr %1) {658; CHECK-LABEL: vld2d_vssvl_imm:659; CHECK: # %bb.0:660; CHECK-NEXT: lea %s2, 256661; CHECK-NEXT: lvl %s2662; CHECK-NEXT: vld2d %v0, 8, %s1663; CHECK-NEXT: vld2d %v0, 8, %s0664; CHECK-NEXT: #APP665; CHECK-NEXT: vst %v0, 8, %s0666; CHECK-NEXT: #NO_APP667; CHECK-NEXT: b.l.t (, %s10)668 %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, ptr %1, i32 256)669 %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)670 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)671 ret void672}673 674; Function Attrs: nounwind675define void @vld2dnc_vssl(ptr %0, i64 %1) {676; CHECK-LABEL: vld2dnc_vssl:677; CHECK: # %bb.0:678; CHECK-NEXT: lea %s2, 256679; CHECK-NEXT: lvl %s2680; CHECK-NEXT: vld2d.nc %v0, %s1, %s0681; CHECK-NEXT: #APP682; CHECK-NEXT: vst %v0, %s1, %s0683; CHECK-NEXT: #NO_APP684; CHECK-NEXT: b.l.t (, %s10)685 %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, ptr %0, i32 256)686 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)687 ret void688}689 690; Function Attrs: nounwind readonly691declare <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64, ptr, i32)692 693; Function Attrs: nounwind694define void @vld2dnc_vssvl(ptr %0, i64 %1, ptr %2) {695; CHECK-LABEL: vld2dnc_vssvl:696; CHECK: # %bb.0:697; CHECK-NEXT: lea %s3, 256698; CHECK-NEXT: lvl %s3699; CHECK-NEXT: vld2d.nc %v0, %s1, %s2700; CHECK-NEXT: vld2d.nc %v0, %s1, %s0701; CHECK-NEXT: #APP702; CHECK-NEXT: vst %v0, %s1, %s0703; CHECK-NEXT: #NO_APP704; CHECK-NEXT: b.l.t (, %s10)705 %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, ptr %2, i32 256)706 %5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)707 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)708 ret void709}710 711; Function Attrs: nounwind readonly712declare <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64, ptr, <256 x double>, i32)713 714; Function Attrs: nounwind715define void @vld2dnc_vssl_imm(ptr %0) {716; CHECK-LABEL: vld2dnc_vssl_imm:717; CHECK: # %bb.0:718; CHECK-NEXT: lea %s1, 256719; CHECK-NEXT: lvl %s1720; CHECK-NEXT: vld2d.nc %v0, 8, %s0721; CHECK-NEXT: #APP722; CHECK-NEXT: vst %v0, 8, %s0723; CHECK-NEXT: #NO_APP724; CHECK-NEXT: b.l.t (, %s10)725 %2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, ptr %0, i32 256)726 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)727 ret void728}729 730; Function Attrs: nounwind731define void @vld2dnc_vssvl_imm(ptr %0, ptr %1) {732; CHECK-LABEL: vld2dnc_vssvl_imm:733; CHECK: # %bb.0:734; CHECK-NEXT: lea %s2, 256735; CHECK-NEXT: lvl %s2736; CHECK-NEXT: vld2d.nc %v0, 8, %s1737; CHECK-NEXT: vld2d.nc %v0, 8, %s0738; CHECK-NEXT: #APP739; CHECK-NEXT: vst %v0, 8, %s0740; CHECK-NEXT: #NO_APP741; CHECK-NEXT: b.l.t (, %s10)742 %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, ptr %1, i32 256)743 %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)744 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)745 ret void746}747 748; Function Attrs: nounwind749define void @vldu2d_vssl(ptr %0, i64 %1) {750; CHECK-LABEL: vldu2d_vssl:751; CHECK: # %bb.0:752; CHECK-NEXT: lea %s2, 256753; CHECK-NEXT: lvl %s2754; CHECK-NEXT: vldu2d %v0, %s1, %s0755; CHECK-NEXT: #APP756; CHECK-NEXT: vst %v0, %s1, %s0757; CHECK-NEXT: #NO_APP758; CHECK-NEXT: b.l.t (, %s10)759 %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, ptr %0, i32 256)760 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)761 ret void762}763 764; Function Attrs: nounwind readonly765declare <256 x double> @llvm.ve.vl.vldu2d.vssl(i64, ptr, i32)766 767; Function Attrs: nounwind768define void @vldu2d_vssvl(ptr %0, i64 %1, ptr %2) {769; CHECK-LABEL: vldu2d_vssvl:770; CHECK: # %bb.0:771; CHECK-NEXT: lea %s3, 256772; CHECK-NEXT: lvl %s3773; CHECK-NEXT: vldu2d %v0, %s1, %s2774; CHECK-NEXT: vldu2d %v0, %s1, %s0775; CHECK-NEXT: #APP776; CHECK-NEXT: vst %v0, %s1, %s0777; CHECK-NEXT: #NO_APP778; CHECK-NEXT: b.l.t (, %s10)779 %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, ptr %2, i32 256)780 %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)781 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)782 ret void783}784 785; Function Attrs: nounwind readonly786declare <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64, ptr, <256 x double>, i32)787 788; Function Attrs: nounwind789define void @vldu2d_vssl_imm(ptr %0) {790; CHECK-LABEL: vldu2d_vssl_imm:791; CHECK: # %bb.0:792; CHECK-NEXT: lea %s1, 256793; CHECK-NEXT: lvl %s1794; CHECK-NEXT: vldu2d %v0, 8, %s0795; CHECK-NEXT: #APP796; CHECK-NEXT: vst %v0, 8, %s0797; CHECK-NEXT: #NO_APP798; CHECK-NEXT: b.l.t (, %s10)799 %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, ptr %0, i32 256)800 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)801 ret void802}803 804; Function Attrs: nounwind805define void @vldu2d_vssvl_imm(ptr %0, ptr %1) {806; CHECK-LABEL: vldu2d_vssvl_imm:807; CHECK: # %bb.0:808; CHECK-NEXT: lea %s2, 256809; CHECK-NEXT: lvl %s2810; CHECK-NEXT: vldu2d %v0, 8, %s1811; CHECK-NEXT: vldu2d %v0, 8, %s0812; CHECK-NEXT: #APP813; CHECK-NEXT: vst %v0, 8, %s0814; CHECK-NEXT: #NO_APP815; CHECK-NEXT: b.l.t (, %s10)816 %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, ptr %1, i32 256)817 %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)818 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)819 ret void820}821 822; Function Attrs: nounwind823define void @vldu2dnc_vssl(ptr %0, i64 %1) {824; CHECK-LABEL: vldu2dnc_vssl:825; CHECK: # %bb.0:826; CHECK-NEXT: lea %s2, 256827; CHECK-NEXT: lvl %s2828; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0829; CHECK-NEXT: #APP830; CHECK-NEXT: vst %v0, %s1, %s0831; CHECK-NEXT: #NO_APP832; CHECK-NEXT: b.l.t (, %s10)833 %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, ptr %0, i32 256)834 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)835 ret void836}837 838; Function Attrs: nounwind readonly839declare <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64, ptr, i32)840 841; Function Attrs: nounwind842define void @vldu2dnc_vssvl(ptr %0, i64 %1, ptr %2) {843; CHECK-LABEL: vldu2dnc_vssvl:844; CHECK: # %bb.0:845; CHECK-NEXT: lea %s3, 256846; CHECK-NEXT: lvl %s3847; CHECK-NEXT: vldu2d.nc %v0, %s1, %s2848; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0849; CHECK-NEXT: #APP850; CHECK-NEXT: vst %v0, %s1, %s0851; CHECK-NEXT: #NO_APP852; CHECK-NEXT: b.l.t (, %s10)853 %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, ptr %2, i32 256)854 %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)855 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)856 ret void857}858 859; Function Attrs: nounwind readonly860declare <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64, ptr, <256 x double>, i32)861 862; Function Attrs: nounwind863define void @vldu2dnc_vssl_imm(ptr %0) {864; CHECK-LABEL: vldu2dnc_vssl_imm:865; CHECK: # %bb.0:866; CHECK-NEXT: lea %s1, 256867; CHECK-NEXT: lvl %s1868; CHECK-NEXT: vldu2d.nc %v0, 8, %s0869; CHECK-NEXT: #APP870; CHECK-NEXT: vst %v0, 8, %s0871; CHECK-NEXT: #NO_APP872; CHECK-NEXT: b.l.t (, %s10)873 %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, ptr %0, i32 256)874 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)875 ret void876}877 878; Function Attrs: nounwind879define void @vldu2dnc_vssvl_imm(ptr %0, ptr %1) {880; CHECK-LABEL: vldu2dnc_vssvl_imm:881; CHECK: # %bb.0:882; CHECK-NEXT: lea %s2, 256883; CHECK-NEXT: lvl %s2884; CHECK-NEXT: vldu2d.nc %v0, 8, %s1885; CHECK-NEXT: vldu2d.nc %v0, 8, %s0886; CHECK-NEXT: #APP887; CHECK-NEXT: vst %v0, 8, %s0888; CHECK-NEXT: #NO_APP889; CHECK-NEXT: b.l.t (, %s10)890 %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, ptr %1, i32 256)891 %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)892 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)893 ret void894}895 896; Function Attrs: nounwind897define void @vldl2dsx_vssl(ptr %0, i64 %1) {898; CHECK-LABEL: vldl2dsx_vssl:899; CHECK: # %bb.0:900; CHECK-NEXT: lea %s2, 256901; CHECK-NEXT: lvl %s2902; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0903; CHECK-NEXT: #APP904; CHECK-NEXT: vst %v0, %s1, %s0905; CHECK-NEXT: #NO_APP906; CHECK-NEXT: b.l.t (, %s10)907 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, ptr %0, i32 256)908 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)909 ret void910}911 912; Function Attrs: nounwind readonly913declare <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64, ptr, i32)914 915; Function Attrs: nounwind916define void @vldl2dsx_vssvl(ptr %0, i64 %1, ptr %2) {917; CHECK-LABEL: vldl2dsx_vssvl:918; CHECK: # %bb.0:919; CHECK-NEXT: lea %s3, 256920; CHECK-NEXT: lvl %s3921; CHECK-NEXT: vldl2d.sx %v0, %s1, %s2922; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0923; CHECK-NEXT: #APP924; CHECK-NEXT: vst %v0, %s1, %s0925; CHECK-NEXT: #NO_APP926; CHECK-NEXT: b.l.t (, %s10)927 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, ptr %2, i32 256)928 %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)929 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)930 ret void931}932 933; Function Attrs: nounwind readonly934declare <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64, ptr, <256 x double>, i32)935 936; Function Attrs: nounwind937define void @vldl2dsx_vssl_imm(ptr %0) {938; CHECK-LABEL: vldl2dsx_vssl_imm:939; CHECK: # %bb.0:940; CHECK-NEXT: lea %s1, 256941; CHECK-NEXT: lvl %s1942; CHECK-NEXT: vldl2d.sx %v0, 8, %s0943; CHECK-NEXT: #APP944; CHECK-NEXT: vst %v0, 8, %s0945; CHECK-NEXT: #NO_APP946; CHECK-NEXT: b.l.t (, %s10)947 %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, ptr %0, i32 256)948 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)949 ret void950}951 952; Function Attrs: nounwind953define void @vldl2dsx_vssvl_imm(ptr %0, ptr %1) {954; CHECK-LABEL: vldl2dsx_vssvl_imm:955; CHECK: # %bb.0:956; CHECK-NEXT: lea %s2, 256957; CHECK-NEXT: lvl %s2958; CHECK-NEXT: vldl2d.sx %v0, 8, %s1959; CHECK-NEXT: vldl2d.sx %v0, 8, %s0960; CHECK-NEXT: #APP961; CHECK-NEXT: vst %v0, 8, %s0962; CHECK-NEXT: #NO_APP963; CHECK-NEXT: b.l.t (, %s10)964 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, ptr %1, i32 256)965 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)966 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)967 ret void968}969 970; Function Attrs: nounwind971define void @vldl2dsxnc_vssl(ptr %0, i64 %1) {972; CHECK-LABEL: vldl2dsxnc_vssl:973; CHECK: # %bb.0:974; CHECK-NEXT: lea %s2, 256975; CHECK-NEXT: lvl %s2976; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0977; CHECK-NEXT: #APP978; CHECK-NEXT: vst %v0, %s1, %s0979; CHECK-NEXT: #NO_APP980; CHECK-NEXT: b.l.t (, %s10)981 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, ptr %0, i32 256)982 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)983 ret void984}985 986; Function Attrs: nounwind readonly987declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64, ptr, i32)988 989; Function Attrs: nounwind990define void @vldl2dsxnc_vssvl(ptr %0, i64 %1, ptr %2) {991; CHECK-LABEL: vldl2dsxnc_vssvl:992; CHECK: # %bb.0:993; CHECK-NEXT: lea %s3, 256994; CHECK-NEXT: lvl %s3995; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s2996; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0997; CHECK-NEXT: #APP998; CHECK-NEXT: vst %v0, %s1, %s0999; CHECK-NEXT: #NO_APP1000; CHECK-NEXT: b.l.t (, %s10)1001 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, ptr %2, i32 256)1002 %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)1003 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)1004 ret void1005}1006 1007; Function Attrs: nounwind readonly1008declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64, ptr, <256 x double>, i32)1009 1010; Function Attrs: nounwind1011define void @vldl2dsxnc_vssl_imm(ptr %0) {1012; CHECK-LABEL: vldl2dsxnc_vssl_imm:1013; CHECK: # %bb.0:1014; CHECK-NEXT: lea %s1, 2561015; CHECK-NEXT: lvl %s11016; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s01017; CHECK-NEXT: #APP1018; CHECK-NEXT: vst %v0, 8, %s01019; CHECK-NEXT: #NO_APP1020; CHECK-NEXT: b.l.t (, %s10)1021 %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, ptr %0, i32 256)1022 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)1023 ret void1024}1025 1026; Function Attrs: nounwind1027define void @vldl2dsxnc_vssvl_imm(ptr %0, ptr %1) {1028; CHECK-LABEL: vldl2dsxnc_vssvl_imm:1029; CHECK: # %bb.0:1030; CHECK-NEXT: lea %s2, 2561031; CHECK-NEXT: lvl %s21032; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s11033; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s01034; CHECK-NEXT: #APP1035; CHECK-NEXT: vst %v0, 8, %s01036; CHECK-NEXT: #NO_APP1037; CHECK-NEXT: b.l.t (, %s10)1038 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, ptr %1, i32 256)1039 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)1040 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)1041 ret void1042}1043 1044; Function Attrs: nounwind1045define void @vldl2dzx_vssl(ptr %0, i64 %1) {1046; CHECK-LABEL: vldl2dzx_vssl:1047; CHECK: # %bb.0:1048; CHECK-NEXT: lea %s2, 2561049; CHECK-NEXT: lvl %s21050; CHECK-NEXT: vldl2d.zx %v0, %s1, %s01051; CHECK-NEXT: #APP1052; CHECK-NEXT: vst %v0, %s1, %s01053; CHECK-NEXT: #NO_APP1054; CHECK-NEXT: b.l.t (, %s10)1055 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, ptr %0, i32 256)1056 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)1057 ret void1058}1059 1060; Function Attrs: nounwind readonly1061declare <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64, ptr, i32)1062 1063; Function Attrs: nounwind1064define void @vldl2dzx_vssvl(ptr %0, i64 %1, ptr %2) {1065; CHECK-LABEL: vldl2dzx_vssvl:1066; CHECK: # %bb.0:1067; CHECK-NEXT: lea %s3, 2561068; CHECK-NEXT: lvl %s31069; CHECK-NEXT: vldl2d.zx %v0, %s1, %s21070; CHECK-NEXT: vldl2d.zx %v0, %s1, %s01071; CHECK-NEXT: #APP1072; CHECK-NEXT: vst %v0, %s1, %s01073; CHECK-NEXT: #NO_APP1074; CHECK-NEXT: b.l.t (, %s10)1075 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, ptr %2, i32 256)1076 %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)1077 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)1078 ret void1079}1080 1081; Function Attrs: nounwind readonly1082declare <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64, ptr, <256 x double>, i32)1083 1084; Function Attrs: nounwind1085define void @vldl2dzx_vssl_imm(ptr %0) {1086; CHECK-LABEL: vldl2dzx_vssl_imm:1087; CHECK: # %bb.0:1088; CHECK-NEXT: lea %s1, 2561089; CHECK-NEXT: lvl %s11090; CHECK-NEXT: vldl2d.zx %v0, 8, %s01091; CHECK-NEXT: #APP1092; CHECK-NEXT: vst %v0, 8, %s01093; CHECK-NEXT: #NO_APP1094; CHECK-NEXT: b.l.t (, %s10)1095 %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, ptr %0, i32 256)1096 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)1097 ret void1098}1099 1100; Function Attrs: nounwind1101define void @vldl2dzx_vssvl_imm(ptr %0, ptr %1) {1102; CHECK-LABEL: vldl2dzx_vssvl_imm:1103; CHECK: # %bb.0:1104; CHECK-NEXT: lea %s2, 2561105; CHECK-NEXT: lvl %s21106; CHECK-NEXT: vldl2d.zx %v0, 8, %s11107; CHECK-NEXT: vldl2d.zx %v0, 8, %s01108; CHECK-NEXT: #APP1109; CHECK-NEXT: vst %v0, 8, %s01110; CHECK-NEXT: #NO_APP1111; CHECK-NEXT: b.l.t (, %s10)1112 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, ptr %1, i32 256)1113 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)1114 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)1115 ret void1116}1117 1118; Function Attrs: nounwind1119define void @vldl2dzxnc_vssl(ptr %0, i64 %1) {1120; CHECK-LABEL: vldl2dzxnc_vssl:1121; CHECK: # %bb.0:1122; CHECK-NEXT: lea %s2, 2561123; CHECK-NEXT: lvl %s21124; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s01125; CHECK-NEXT: #APP1126; CHECK-NEXT: vst %v0, %s1, %s01127; CHECK-NEXT: #NO_APP1128; CHECK-NEXT: b.l.t (, %s10)1129 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, ptr %0, i32 256)1130 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %3, ptr %0, i64 %1)1131 ret void1132}1133 1134; Function Attrs: nounwind readonly1135declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64, ptr, i32)1136 1137; Function Attrs: nounwind1138define void @vldl2dzxnc_vssvl(ptr %0, i64 %1, ptr %2) {1139; CHECK-LABEL: vldl2dzxnc_vssvl:1140; CHECK: # %bb.0:1141; CHECK-NEXT: lea %s3, 2561142; CHECK-NEXT: lvl %s31143; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s21144; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s01145; CHECK-NEXT: #APP1146; CHECK-NEXT: vst %v0, %s1, %s01147; CHECK-NEXT: #NO_APP1148; CHECK-NEXT: b.l.t (, %s10)1149 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, ptr %2, i32 256)1150 %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, ptr %0, <256 x double> %4, i32 256)1151 tail call void asm sideeffect "vst ${0:v}, $2, $1", "v,r,r"(<256 x double> %5, ptr %0, i64 %1)1152 ret void1153}1154 1155; Function Attrs: nounwind readonly1156declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64, ptr, <256 x double>, i32)1157 1158; Function Attrs: nounwind1159define void @vldl2dzxnc_vssl_imm(ptr %0) {1160; CHECK-LABEL: vldl2dzxnc_vssl_imm:1161; CHECK: # %bb.0:1162; CHECK-NEXT: lea %s1, 2561163; CHECK-NEXT: lvl %s11164; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s01165; CHECK-NEXT: #APP1166; CHECK-NEXT: vst %v0, 8, %s01167; CHECK-NEXT: #NO_APP1168; CHECK-NEXT: b.l.t (, %s10)1169 %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, ptr %0, i32 256)1170 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %2, ptr %0)1171 ret void1172}1173 1174; Function Attrs: nounwind1175define void @vldl2dzxnc_vssvl_imm(ptr %0, ptr %1) {1176; CHECK-LABEL: vldl2dzxnc_vssvl_imm:1177; CHECK: # %bb.0:1178; CHECK-NEXT: lea %s2, 2561179; CHECK-NEXT: lvl %s21180; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s11181; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s01182; CHECK-NEXT: #APP1183; CHECK-NEXT: vst %v0, 8, %s01184; CHECK-NEXT: #NO_APP1185; CHECK-NEXT: b.l.t (, %s10)1186 %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, ptr %1, i32 256)1187 %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, ptr %0, <256 x double> %3, i32 256)1188 tail call void asm sideeffect "vst ${0:v}, 8, $1", "v,r"(<256 x double> %4, ptr %0)1189 ret void1190}1191