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1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector floating reciprocal intrinsic instructions4;;;5;;; Note:6;;; We test VRCP*vl, VRCP*vl_v, PVRCP*vl, and PVRCP*vl_v instructions.7 8; Function Attrs: nounwind readnone9define fastcc <256 x double> @vrcpd_vvl(<256 x double> %0) {10; CHECK-LABEL: vrcpd_vvl:11; CHECK: # %bb.0:12; CHECK-NEXT: lea %s0, 25613; CHECK-NEXT: lvl %s014; CHECK-NEXT: vrcp.d %v0, %v015; CHECK-NEXT: b.l.t (, %s10)16 %2 = tail call fast <256 x double> @llvm.ve.vl.vrcpd.vvl(<256 x double> %0, i32 256)17 ret <256 x double> %218}19 20; Function Attrs: nounwind readnone21declare <256 x double> @llvm.ve.vl.vrcpd.vvl(<256 x double>, i32)22 23; Function Attrs: nounwind readnone24define fastcc <256 x double> @vrcpd_vvvl(<256 x double> %0, <256 x double> %1) {25; CHECK-LABEL: vrcpd_vvvl:26; CHECK: # %bb.0:27; CHECK-NEXT: lea %s0, 12828; CHECK-NEXT: lvl %s029; CHECK-NEXT: vrcp.d %v1, %v030; CHECK-NEXT: lea %s16, 25631; CHECK-NEXT: lvl %s1632; CHECK-NEXT: vor %v0, (0)1, %v133; CHECK-NEXT: b.l.t (, %s10)34 %3 = tail call fast <256 x double> @llvm.ve.vl.vrcpd.vvvl(<256 x double> %0, <256 x double> %1, i32 128)35 ret <256 x double> %336}37 38; Function Attrs: nounwind readnone39declare <256 x double> @llvm.ve.vl.vrcpd.vvvl(<256 x double>, <256 x double>, i32)40 41; Function Attrs: nounwind readnone42define fastcc <256 x double> @vrcps_vvl(<256 x double> %0) {43; CHECK-LABEL: vrcps_vvl:44; CHECK: # %bb.0:45; CHECK-NEXT: lea %s0, 25646; CHECK-NEXT: lvl %s047; CHECK-NEXT: vrcp.s %v0, %v048; CHECK-NEXT: b.l.t (, %s10)49 %2 = tail call fast <256 x double> @llvm.ve.vl.vrcps.vvl(<256 x double> %0, i32 256)50 ret <256 x double> %251}52 53; Function Attrs: nounwind readnone54declare <256 x double> @llvm.ve.vl.vrcps.vvl(<256 x double>, i32)55 56; Function Attrs: nounwind readnone57define fastcc <256 x double> @vrcps_vvvl(<256 x double> %0, <256 x double> %1) {58; CHECK-LABEL: vrcps_vvvl:59; CHECK: # %bb.0:60; CHECK-NEXT: lea %s0, 12861; CHECK-NEXT: lvl %s062; CHECK-NEXT: vrcp.s %v1, %v063; CHECK-NEXT: lea %s16, 25664; CHECK-NEXT: lvl %s1665; CHECK-NEXT: vor %v0, (0)1, %v166; CHECK-NEXT: b.l.t (, %s10)67 %3 = tail call fast <256 x double> @llvm.ve.vl.vrcps.vvvl(<256 x double> %0, <256 x double> %1, i32 128)68 ret <256 x double> %369}70 71; Function Attrs: nounwind readnone72declare <256 x double> @llvm.ve.vl.vrcps.vvvl(<256 x double>, <256 x double>, i32)73 74; Function Attrs: nounwind readnone75define fastcc <256 x double> @pvrcp_vvl(<256 x double> %0) {76; CHECK-LABEL: pvrcp_vvl:77; CHECK: # %bb.0:78; CHECK-NEXT: lea %s0, 25679; CHECK-NEXT: lvl %s080; CHECK-NEXT: pvrcp %v0, %v081; CHECK-NEXT: b.l.t (, %s10)82 %2 = tail call fast <256 x double> @llvm.ve.vl.pvrcp.vvl(<256 x double> %0, i32 256)83 ret <256 x double> %284}85 86; Function Attrs: nounwind readnone87declare <256 x double> @llvm.ve.vl.pvrcp.vvl(<256 x double>, i32)88 89; Function Attrs: nounwind readnone90define fastcc <256 x double> @pvrcp_vvvl(<256 x double> %0, <256 x double> %1) {91; CHECK-LABEL: pvrcp_vvvl:92; CHECK: # %bb.0:93; CHECK-NEXT: lea %s0, 12894; CHECK-NEXT: lvl %s095; CHECK-NEXT: pvrcp %v1, %v096; CHECK-NEXT: lea %s16, 25697; CHECK-NEXT: lvl %s1698; CHECK-NEXT: vor %v0, (0)1, %v199; CHECK-NEXT: b.l.t (, %s10)100 %3 = tail call fast <256 x double> @llvm.ve.vl.pvrcp.vvvl(<256 x double> %0, <256 x double> %1, i32 128)101 ret <256 x double> %3102}103 104; Function Attrs: nounwind readnone105declare <256 x double> @llvm.ve.vl.pvrcp.vvvl(<256 x double>, <256 x double>, i32)106