37 lines · plain
1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector reduction or intrinsic instructions4;;;5;;; Note:6;;; We test VROR*vl and VROR*vml instructions.7 8; Function Attrs: nounwind readnone9define fastcc <256 x double> @vror_vvl(<256 x double> %0) {10; CHECK-LABEL: vror_vvl:11; CHECK: # %bb.0:12; CHECK-NEXT: lea %s0, 25613; CHECK-NEXT: lvl %s014; CHECK-NEXT: vror %v0, %v015; CHECK-NEXT: b.l.t (, %s10)16 %2 = tail call fast <256 x double> @llvm.ve.vl.vror.vvl(<256 x double> %0, i32 256)17 ret <256 x double> %218}19 20; Function Attrs: nounwind readnone21declare <256 x double> @llvm.ve.vl.vror.vvl(<256 x double>, i32)22 23; Function Attrs: nounwind readnone24define fastcc <256 x double> @vror_vvml(<256 x double> %0, <256 x i1> %1) {25; CHECK-LABEL: vror_vvml:26; CHECK: # %bb.0:27; CHECK-NEXT: lea %s0, 25628; CHECK-NEXT: lvl %s029; CHECK-NEXT: vror %v0, %v0, %vm130; CHECK-NEXT: b.l.t (, %s10)31 %3 = tail call fast <256 x double> @llvm.ve.vl.vror.vvml(<256 x double> %0, <256 x i1> %1, i32 256)32 ret <256 x double> %333}34 35; Function Attrs: nounwind readnone36declare <256 x double> @llvm.ve.vl.vror.vvml(<256 x double>, <256 x i1>, i32)37