1388 lines · plain
1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector scatter intrinsic instructions4;;;5;;; Note:6;;; We test VSC*vrrvl, VSC*vrzvl, VSC*virvl, VSC*vizvl, VSC*vrrvml,7;;; VSC*vrzvml, VSC*virvml, and VSC*vizvml instructions.8 9; Function Attrs: nounwind writeonly10define fastcc void @vsc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {11; CHECK-LABEL: vsc_vvssl:12; CHECK: # %bb.0:13; CHECK-NEXT: lea %s2, 25614; CHECK-NEXT: lvl %s215; CHECK-NEXT: vsc %v0, %v1, %s0, %s116; CHECK-NEXT: b.l.t (, %s10)17 tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)18 ret void19}20 21; Function Attrs: nounwind writeonly22declare void @llvm.ve.vl.vsc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)23 24; Function Attrs: nounwind writeonly25define fastcc void @vsc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {26; CHECK-LABEL: vsc_vvssl_imm_1:27; CHECK: # %bb.0:28; CHECK-NEXT: lea %s1, 25629; CHECK-NEXT: lvl %s130; CHECK-NEXT: vsc %v0, %v1, %s0, 031; CHECK-NEXT: b.l.t (, %s10)32 tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)33 ret void34}35 36; Function Attrs: nounwind writeonly37define fastcc void @vsc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {38; CHECK-LABEL: vsc_vvssl_imm_2:39; CHECK: # %bb.0:40; CHECK-NEXT: lea %s1, 25641; CHECK-NEXT: lvl %s142; CHECK-NEXT: vsc %v0, %v1, 8, %s043; CHECK-NEXT: b.l.t (, %s10)44 tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)45 ret void46}47 48; Function Attrs: nounwind writeonly49define fastcc void @vsc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {50; CHECK-LABEL: vsc_vvssl_imm_3:51; CHECK: # %bb.0:52; CHECK-NEXT: lea %s0, 25653; CHECK-NEXT: lvl %s054; CHECK-NEXT: vsc %v0, %v1, 8, 055; CHECK-NEXT: b.l.t (, %s10)56 tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)57 ret void58}59 60; Function Attrs: nounwind writeonly61define fastcc void @vsc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {62; CHECK-LABEL: vsc_vvssml:63; CHECK: # %bb.0:64; CHECK-NEXT: lea %s2, 25665; CHECK-NEXT: lvl %s266; CHECK-NEXT: vsc %v0, %v1, %s0, %s1, %vm167; CHECK-NEXT: b.l.t (, %s10)68 tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)69 ret void70}71 72; Function Attrs: nounwind writeonly73declare void @llvm.ve.vl.vsc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)74 75; Function Attrs: nounwind writeonly76define fastcc void @vsc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {77; CHECK-LABEL: vsc_vvssml_imm_1:78; CHECK: # %bb.0:79; CHECK-NEXT: lea %s1, 25680; CHECK-NEXT: lvl %s181; CHECK-NEXT: vsc %v0, %v1, %s0, 0, %vm182; CHECK-NEXT: b.l.t (, %s10)83 tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)84 ret void85}86 87; Function Attrs: nounwind writeonly88define fastcc void @vsc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {89; CHECK-LABEL: vsc_vvssml_imm_2:90; CHECK: # %bb.0:91; CHECK-NEXT: lea %s1, 25692; CHECK-NEXT: lvl %s193; CHECK-NEXT: vsc %v0, %v1, 8, %s0, %vm194; CHECK-NEXT: b.l.t (, %s10)95 tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)96 ret void97}98 99; Function Attrs: nounwind writeonly100define fastcc void @vsc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {101; CHECK-LABEL: vsc_vvssml_imm_3:102; CHECK: # %bb.0:103; CHECK-NEXT: lea %s0, 256104; CHECK-NEXT: lvl %s0105; CHECK-NEXT: vsc %v0, %v1, 8, 0, %vm1106; CHECK-NEXT: b.l.t (, %s10)107 tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)108 ret void109}110 111; Function Attrs: nounwind writeonly112define fastcc void @vsc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {113; CHECK-LABEL: vsc_vvssl_no_imm_1:114; CHECK: # %bb.0:115; CHECK-NEXT: lea %s1, 256116; CHECK-NEXT: or %s2, 8, (0)1117; CHECK-NEXT: lvl %s1118; CHECK-NEXT: vsc %v0, %v1, %s0, %s2119; CHECK-NEXT: b.l.t (, %s10)120 tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)121 ret void122}123 124; Function Attrs: nounwind writeonly125define fastcc void @vscnc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {126; CHECK-LABEL: vscnc_vvssl:127; CHECK: # %bb.0:128; CHECK-NEXT: lea %s2, 256129; CHECK-NEXT: lvl %s2130; CHECK-NEXT: vsc.nc %v0, %v1, %s0, %s1131; CHECK-NEXT: b.l.t (, %s10)132 tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)133 ret void134}135 136; Function Attrs: nounwind writeonly137declare void @llvm.ve.vl.vscnc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)138 139; Function Attrs: nounwind writeonly140define fastcc void @vscnc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {141; CHECK-LABEL: vscnc_vvssl_imm_1:142; CHECK: # %bb.0:143; CHECK-NEXT: lea %s1, 256144; CHECK-NEXT: lvl %s1145; CHECK-NEXT: vsc.nc %v0, %v1, %s0, 0146; CHECK-NEXT: b.l.t (, %s10)147 tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)148 ret void149}150 151; Function Attrs: nounwind writeonly152define fastcc void @vscnc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {153; CHECK-LABEL: vscnc_vvssl_imm_2:154; CHECK: # %bb.0:155; CHECK-NEXT: lea %s1, 256156; CHECK-NEXT: lvl %s1157; CHECK-NEXT: vsc.nc %v0, %v1, 8, %s0158; CHECK-NEXT: b.l.t (, %s10)159 tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)160 ret void161}162 163; Function Attrs: nounwind writeonly164define fastcc void @vscnc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {165; CHECK-LABEL: vscnc_vvssl_imm_3:166; CHECK: # %bb.0:167; CHECK-NEXT: lea %s0, 256168; CHECK-NEXT: lvl %s0169; CHECK-NEXT: vsc.nc %v0, %v1, 8, 0170; CHECK-NEXT: b.l.t (, %s10)171 tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)172 ret void173}174 175; Function Attrs: nounwind writeonly176define fastcc void @vscnc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {177; CHECK-LABEL: vscnc_vvssml:178; CHECK: # %bb.0:179; CHECK-NEXT: lea %s2, 256180; CHECK-NEXT: lvl %s2181; CHECK-NEXT: vsc.nc %v0, %v1, %s0, %s1, %vm1182; CHECK-NEXT: b.l.t (, %s10)183 tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)184 ret void185}186 187; Function Attrs: nounwind writeonly188declare void @llvm.ve.vl.vscnc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)189 190; Function Attrs: nounwind writeonly191define fastcc void @vscnc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {192; CHECK-LABEL: vscnc_vvssml_imm_1:193; CHECK: # %bb.0:194; CHECK-NEXT: lea %s1, 256195; CHECK-NEXT: lvl %s1196; CHECK-NEXT: vsc.nc %v0, %v1, %s0, 0, %vm1197; CHECK-NEXT: b.l.t (, %s10)198 tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)199 ret void200}201 202; Function Attrs: nounwind writeonly203define fastcc void @vscnc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {204; CHECK-LABEL: vscnc_vvssml_imm_2:205; CHECK: # %bb.0:206; CHECK-NEXT: lea %s1, 256207; CHECK-NEXT: lvl %s1208; CHECK-NEXT: vsc.nc %v0, %v1, 8, %s0, %vm1209; CHECK-NEXT: b.l.t (, %s10)210 tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)211 ret void212}213 214; Function Attrs: nounwind writeonly215define fastcc void @vscnc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {216; CHECK-LABEL: vscnc_vvssml_imm_3:217; CHECK: # %bb.0:218; CHECK-NEXT: lea %s0, 256219; CHECK-NEXT: lvl %s0220; CHECK-NEXT: vsc.nc %v0, %v1, 8, 0, %vm1221; CHECK-NEXT: b.l.t (, %s10)222 tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)223 ret void224}225 226; Function Attrs: nounwind writeonly227define fastcc void @vscnc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {228; CHECK-LABEL: vscnc_vvssl_no_imm_1:229; CHECK: # %bb.0:230; CHECK-NEXT: lea %s1, 256231; CHECK-NEXT: or %s2, 8, (0)1232; CHECK-NEXT: lvl %s1233; CHECK-NEXT: vsc.nc %v0, %v1, %s0, %s2234; CHECK-NEXT: b.l.t (, %s10)235 tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)236 ret void237}238 239; Function Attrs: nounwind writeonly240define fastcc void @vscot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {241; CHECK-LABEL: vscot_vvssl:242; CHECK: # %bb.0:243; CHECK-NEXT: lea %s2, 256244; CHECK-NEXT: lvl %s2245; CHECK-NEXT: vsc.ot %v0, %v1, %s0, %s1246; CHECK-NEXT: b.l.t (, %s10)247 tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)248 ret void249}250 251; Function Attrs: nounwind writeonly252declare void @llvm.ve.vl.vscot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)253 254; Function Attrs: nounwind writeonly255define fastcc void @vscot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {256; CHECK-LABEL: vscot_vvssl_imm_1:257; CHECK: # %bb.0:258; CHECK-NEXT: lea %s1, 256259; CHECK-NEXT: lvl %s1260; CHECK-NEXT: vsc.ot %v0, %v1, %s0, 0261; CHECK-NEXT: b.l.t (, %s10)262 tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)263 ret void264}265 266; Function Attrs: nounwind writeonly267define fastcc void @vscot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {268; CHECK-LABEL: vscot_vvssl_imm_2:269; CHECK: # %bb.0:270; CHECK-NEXT: lea %s1, 256271; CHECK-NEXT: lvl %s1272; CHECK-NEXT: vsc.ot %v0, %v1, 8, %s0273; CHECK-NEXT: b.l.t (, %s10)274 tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)275 ret void276}277 278; Function Attrs: nounwind writeonly279define fastcc void @vscot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {280; CHECK-LABEL: vscot_vvssl_imm_3:281; CHECK: # %bb.0:282; CHECK-NEXT: lea %s0, 256283; CHECK-NEXT: lvl %s0284; CHECK-NEXT: vsc.ot %v0, %v1, 8, 0285; CHECK-NEXT: b.l.t (, %s10)286 tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)287 ret void288}289 290; Function Attrs: nounwind writeonly291define fastcc void @vscot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {292; CHECK-LABEL: vscot_vvssml:293; CHECK: # %bb.0:294; CHECK-NEXT: lea %s2, 256295; CHECK-NEXT: lvl %s2296; CHECK-NEXT: vsc.ot %v0, %v1, %s0, %s1, %vm1297; CHECK-NEXT: b.l.t (, %s10)298 tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)299 ret void300}301 302; Function Attrs: nounwind writeonly303declare void @llvm.ve.vl.vscot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)304 305; Function Attrs: nounwind writeonly306define fastcc void @vscot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {307; CHECK-LABEL: vscot_vvssml_imm_1:308; CHECK: # %bb.0:309; CHECK-NEXT: lea %s1, 256310; CHECK-NEXT: lvl %s1311; CHECK-NEXT: vsc.ot %v0, %v1, %s0, 0, %vm1312; CHECK-NEXT: b.l.t (, %s10)313 tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)314 ret void315}316 317; Function Attrs: nounwind writeonly318define fastcc void @vscot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {319; CHECK-LABEL: vscot_vvssml_imm_2:320; CHECK: # %bb.0:321; CHECK-NEXT: lea %s1, 256322; CHECK-NEXT: lvl %s1323; CHECK-NEXT: vsc.ot %v0, %v1, 8, %s0, %vm1324; CHECK-NEXT: b.l.t (, %s10)325 tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)326 ret void327}328 329; Function Attrs: nounwind writeonly330define fastcc void @vscot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {331; CHECK-LABEL: vscot_vvssml_imm_3:332; CHECK: # %bb.0:333; CHECK-NEXT: lea %s0, 256334; CHECK-NEXT: lvl %s0335; CHECK-NEXT: vsc.ot %v0, %v1, 8, 0, %vm1336; CHECK-NEXT: b.l.t (, %s10)337 tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)338 ret void339}340 341; Function Attrs: nounwind writeonly342define fastcc void @vscot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {343; CHECK-LABEL: vscot_vvssl_no_imm_1:344; CHECK: # %bb.0:345; CHECK-NEXT: lea %s1, 256346; CHECK-NEXT: or %s2, 8, (0)1347; CHECK-NEXT: lvl %s1348; CHECK-NEXT: vsc.ot %v0, %v1, %s0, %s2349; CHECK-NEXT: b.l.t (, %s10)350 tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)351 ret void352}353 354; Function Attrs: nounwind writeonly355define fastcc void @vscncot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {356; CHECK-LABEL: vscncot_vvssl:357; CHECK: # %bb.0:358; CHECK-NEXT: lea %s2, 256359; CHECK-NEXT: lvl %s2360; CHECK-NEXT: vsc.nc.ot %v0, %v1, %s0, %s1361; CHECK-NEXT: b.l.t (, %s10)362 tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)363 ret void364}365 366; Function Attrs: nounwind writeonly367declare void @llvm.ve.vl.vscncot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)368 369; Function Attrs: nounwind writeonly370define fastcc void @vscncot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {371; CHECK-LABEL: vscncot_vvssl_imm_1:372; CHECK: # %bb.0:373; CHECK-NEXT: lea %s1, 256374; CHECK-NEXT: lvl %s1375; CHECK-NEXT: vsc.nc.ot %v0, %v1, %s0, 0376; CHECK-NEXT: b.l.t (, %s10)377 tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)378 ret void379}380 381; Function Attrs: nounwind writeonly382define fastcc void @vscncot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {383; CHECK-LABEL: vscncot_vvssl_imm_2:384; CHECK: # %bb.0:385; CHECK-NEXT: lea %s1, 256386; CHECK-NEXT: lvl %s1387; CHECK-NEXT: vsc.nc.ot %v0, %v1, 8, %s0388; CHECK-NEXT: b.l.t (, %s10)389 tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)390 ret void391}392 393; Function Attrs: nounwind writeonly394define fastcc void @vscncot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {395; CHECK-LABEL: vscncot_vvssl_imm_3:396; CHECK: # %bb.0:397; CHECK-NEXT: lea %s0, 256398; CHECK-NEXT: lvl %s0399; CHECK-NEXT: vsc.nc.ot %v0, %v1, 8, 0400; CHECK-NEXT: b.l.t (, %s10)401 tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)402 ret void403}404 405; Function Attrs: nounwind writeonly406define fastcc void @vscncot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {407; CHECK-LABEL: vscncot_vvssml:408; CHECK: # %bb.0:409; CHECK-NEXT: lea %s2, 256410; CHECK-NEXT: lvl %s2411; CHECK-NEXT: vsc.nc.ot %v0, %v1, %s0, %s1, %vm1412; CHECK-NEXT: b.l.t (, %s10)413 tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)414 ret void415}416 417; Function Attrs: nounwind writeonly418declare void @llvm.ve.vl.vscncot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)419 420; Function Attrs: nounwind writeonly421define fastcc void @vscncot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {422; CHECK-LABEL: vscncot_vvssml_imm_1:423; CHECK: # %bb.0:424; CHECK-NEXT: lea %s1, 256425; CHECK-NEXT: lvl %s1426; CHECK-NEXT: vsc.nc.ot %v0, %v1, %s0, 0, %vm1427; CHECK-NEXT: b.l.t (, %s10)428 tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)429 ret void430}431 432; Function Attrs: nounwind writeonly433define fastcc void @vscncot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {434; CHECK-LABEL: vscncot_vvssml_imm_2:435; CHECK: # %bb.0:436; CHECK-NEXT: lea %s1, 256437; CHECK-NEXT: lvl %s1438; CHECK-NEXT: vsc.nc.ot %v0, %v1, 8, %s0, %vm1439; CHECK-NEXT: b.l.t (, %s10)440 tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)441 ret void442}443 444; Function Attrs: nounwind writeonly445define fastcc void @vscncot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {446; CHECK-LABEL: vscncot_vvssml_imm_3:447; CHECK: # %bb.0:448; CHECK-NEXT: lea %s0, 256449; CHECK-NEXT: lvl %s0450; CHECK-NEXT: vsc.nc.ot %v0, %v1, 8, 0, %vm1451; CHECK-NEXT: b.l.t (, %s10)452 tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)453 ret void454}455 456; Function Attrs: nounwind writeonly457define fastcc void @vscncot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {458; CHECK-LABEL: vscncot_vvssl_no_imm_1:459; CHECK: # %bb.0:460; CHECK-NEXT: lea %s1, 256461; CHECK-NEXT: or %s2, 8, (0)1462; CHECK-NEXT: lvl %s1463; CHECK-NEXT: vsc.nc.ot %v0, %v1, %s0, %s2464; CHECK-NEXT: b.l.t (, %s10)465 tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)466 ret void467}468 469; Function Attrs: nounwind writeonly470define fastcc void @vscu_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {471; CHECK-LABEL: vscu_vvssl:472; CHECK: # %bb.0:473; CHECK-NEXT: lea %s2, 256474; CHECK-NEXT: lvl %s2475; CHECK-NEXT: vscu %v0, %v1, %s0, %s1476; CHECK-NEXT: b.l.t (, %s10)477 tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)478 ret void479}480 481; Function Attrs: nounwind writeonly482declare void @llvm.ve.vl.vscu.vvssl(<256 x double>, <256 x double>, i64, i64, i32)483 484; Function Attrs: nounwind writeonly485define fastcc void @vscu_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {486; CHECK-LABEL: vscu_vvssl_imm_1:487; CHECK: # %bb.0:488; CHECK-NEXT: lea %s1, 256489; CHECK-NEXT: lvl %s1490; CHECK-NEXT: vscu %v0, %v1, %s0, 0491; CHECK-NEXT: b.l.t (, %s10)492 tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)493 ret void494}495 496; Function Attrs: nounwind writeonly497define fastcc void @vscu_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {498; CHECK-LABEL: vscu_vvssl_imm_2:499; CHECK: # %bb.0:500; CHECK-NEXT: lea %s1, 256501; CHECK-NEXT: lvl %s1502; CHECK-NEXT: vscu %v0, %v1, 8, %s0503; CHECK-NEXT: b.l.t (, %s10)504 tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)505 ret void506}507 508; Function Attrs: nounwind writeonly509define fastcc void @vscu_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {510; CHECK-LABEL: vscu_vvssl_imm_3:511; CHECK: # %bb.0:512; CHECK-NEXT: lea %s0, 256513; CHECK-NEXT: lvl %s0514; CHECK-NEXT: vscu %v0, %v1, 8, 0515; CHECK-NEXT: b.l.t (, %s10)516 tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)517 ret void518}519 520; Function Attrs: nounwind writeonly521define fastcc void @vscu_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {522; CHECK-LABEL: vscu_vvssml:523; CHECK: # %bb.0:524; CHECK-NEXT: lea %s2, 256525; CHECK-NEXT: lvl %s2526; CHECK-NEXT: vscu %v0, %v1, %s0, %s1, %vm1527; CHECK-NEXT: b.l.t (, %s10)528 tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)529 ret void530}531 532; Function Attrs: nounwind writeonly533declare void @llvm.ve.vl.vscu.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)534 535; Function Attrs: nounwind writeonly536define fastcc void @vscu_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {537; CHECK-LABEL: vscu_vvssml_imm_1:538; CHECK: # %bb.0:539; CHECK-NEXT: lea %s1, 256540; CHECK-NEXT: lvl %s1541; CHECK-NEXT: vscu %v0, %v1, %s0, 0, %vm1542; CHECK-NEXT: b.l.t (, %s10)543 tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)544 ret void545}546 547; Function Attrs: nounwind writeonly548define fastcc void @vscu_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {549; CHECK-LABEL: vscu_vvssml_imm_2:550; CHECK: # %bb.0:551; CHECK-NEXT: lea %s1, 256552; CHECK-NEXT: lvl %s1553; CHECK-NEXT: vscu %v0, %v1, 8, %s0, %vm1554; CHECK-NEXT: b.l.t (, %s10)555 tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)556 ret void557}558 559; Function Attrs: nounwind writeonly560define fastcc void @vscu_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {561; CHECK-LABEL: vscu_vvssml_imm_3:562; CHECK: # %bb.0:563; CHECK-NEXT: lea %s0, 256564; CHECK-NEXT: lvl %s0565; CHECK-NEXT: vscu %v0, %v1, 8, 0, %vm1566; CHECK-NEXT: b.l.t (, %s10)567 tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)568 ret void569}570 571; Function Attrs: nounwind writeonly572define fastcc void @vscu_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {573; CHECK-LABEL: vscu_vvssl_no_imm_1:574; CHECK: # %bb.0:575; CHECK-NEXT: lea %s1, 256576; CHECK-NEXT: or %s2, 8, (0)1577; CHECK-NEXT: lvl %s1578; CHECK-NEXT: vscu %v0, %v1, %s0, %s2579; CHECK-NEXT: b.l.t (, %s10)580 tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)581 ret void582}583 584; Function Attrs: nounwind writeonly585define fastcc void @vscunc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {586; CHECK-LABEL: vscunc_vvssl:587; CHECK: # %bb.0:588; CHECK-NEXT: lea %s2, 256589; CHECK-NEXT: lvl %s2590; CHECK-NEXT: vscu.nc %v0, %v1, %s0, %s1591; CHECK-NEXT: b.l.t (, %s10)592 tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)593 ret void594}595 596; Function Attrs: nounwind writeonly597declare void @llvm.ve.vl.vscunc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)598 599; Function Attrs: nounwind writeonly600define fastcc void @vscunc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {601; CHECK-LABEL: vscunc_vvssl_imm_1:602; CHECK: # %bb.0:603; CHECK-NEXT: lea %s1, 256604; CHECK-NEXT: lvl %s1605; CHECK-NEXT: vscu.nc %v0, %v1, %s0, 0606; CHECK-NEXT: b.l.t (, %s10)607 tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)608 ret void609}610 611; Function Attrs: nounwind writeonly612define fastcc void @vscunc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {613; CHECK-LABEL: vscunc_vvssl_imm_2:614; CHECK: # %bb.0:615; CHECK-NEXT: lea %s1, 256616; CHECK-NEXT: lvl %s1617; CHECK-NEXT: vscu.nc %v0, %v1, 8, %s0618; CHECK-NEXT: b.l.t (, %s10)619 tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)620 ret void621}622 623; Function Attrs: nounwind writeonly624define fastcc void @vscunc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {625; CHECK-LABEL: vscunc_vvssl_imm_3:626; CHECK: # %bb.0:627; CHECK-NEXT: lea %s0, 256628; CHECK-NEXT: lvl %s0629; CHECK-NEXT: vscu.nc %v0, %v1, 8, 0630; CHECK-NEXT: b.l.t (, %s10)631 tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)632 ret void633}634 635; Function Attrs: nounwind writeonly636define fastcc void @vscunc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {637; CHECK-LABEL: vscunc_vvssml:638; CHECK: # %bb.0:639; CHECK-NEXT: lea %s2, 256640; CHECK-NEXT: lvl %s2641; CHECK-NEXT: vscu.nc %v0, %v1, %s0, %s1, %vm1642; CHECK-NEXT: b.l.t (, %s10)643 tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)644 ret void645}646 647; Function Attrs: nounwind writeonly648declare void @llvm.ve.vl.vscunc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)649 650; Function Attrs: nounwind writeonly651define fastcc void @vscunc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {652; CHECK-LABEL: vscunc_vvssml_imm_1:653; CHECK: # %bb.0:654; CHECK-NEXT: lea %s1, 256655; CHECK-NEXT: lvl %s1656; CHECK-NEXT: vscu.nc %v0, %v1, %s0, 0, %vm1657; CHECK-NEXT: b.l.t (, %s10)658 tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)659 ret void660}661 662; Function Attrs: nounwind writeonly663define fastcc void @vscunc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {664; CHECK-LABEL: vscunc_vvssml_imm_2:665; CHECK: # %bb.0:666; CHECK-NEXT: lea %s1, 256667; CHECK-NEXT: lvl %s1668; CHECK-NEXT: vscu.nc %v0, %v1, 8, %s0, %vm1669; CHECK-NEXT: b.l.t (, %s10)670 tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)671 ret void672}673 674; Function Attrs: nounwind writeonly675define fastcc void @vscunc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {676; CHECK-LABEL: vscunc_vvssml_imm_3:677; CHECK: # %bb.0:678; CHECK-NEXT: lea %s0, 256679; CHECK-NEXT: lvl %s0680; CHECK-NEXT: vscu.nc %v0, %v1, 8, 0, %vm1681; CHECK-NEXT: b.l.t (, %s10)682 tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)683 ret void684}685 686; Function Attrs: nounwind writeonly687define fastcc void @vscunc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {688; CHECK-LABEL: vscunc_vvssl_no_imm_1:689; CHECK: # %bb.0:690; CHECK-NEXT: lea %s1, 256691; CHECK-NEXT: or %s2, 8, (0)1692; CHECK-NEXT: lvl %s1693; CHECK-NEXT: vscu.nc %v0, %v1, %s0, %s2694; CHECK-NEXT: b.l.t (, %s10)695 tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)696 ret void697}698 699; Function Attrs: nounwind writeonly700define fastcc void @vscuot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {701; CHECK-LABEL: vscuot_vvssl:702; CHECK: # %bb.0:703; CHECK-NEXT: lea %s2, 256704; CHECK-NEXT: lvl %s2705; CHECK-NEXT: vscu.ot %v0, %v1, %s0, %s1706; CHECK-NEXT: b.l.t (, %s10)707 tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)708 ret void709}710 711; Function Attrs: nounwind writeonly712declare void @llvm.ve.vl.vscuot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)713 714; Function Attrs: nounwind writeonly715define fastcc void @vscuot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {716; CHECK-LABEL: vscuot_vvssl_imm_1:717; CHECK: # %bb.0:718; CHECK-NEXT: lea %s1, 256719; CHECK-NEXT: lvl %s1720; CHECK-NEXT: vscu.ot %v0, %v1, %s0, 0721; CHECK-NEXT: b.l.t (, %s10)722 tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)723 ret void724}725 726; Function Attrs: nounwind writeonly727define fastcc void @vscuot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {728; CHECK-LABEL: vscuot_vvssl_imm_2:729; CHECK: # %bb.0:730; CHECK-NEXT: lea %s1, 256731; CHECK-NEXT: lvl %s1732; CHECK-NEXT: vscu.ot %v0, %v1, 8, %s0733; CHECK-NEXT: b.l.t (, %s10)734 tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)735 ret void736}737 738; Function Attrs: nounwind writeonly739define fastcc void @vscuot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {740; CHECK-LABEL: vscuot_vvssl_imm_3:741; CHECK: # %bb.0:742; CHECK-NEXT: lea %s0, 256743; CHECK-NEXT: lvl %s0744; CHECK-NEXT: vscu.ot %v0, %v1, 8, 0745; CHECK-NEXT: b.l.t (, %s10)746 tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)747 ret void748}749 750; Function Attrs: nounwind writeonly751define fastcc void @vscuot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {752; CHECK-LABEL: vscuot_vvssml:753; CHECK: # %bb.0:754; CHECK-NEXT: lea %s2, 256755; CHECK-NEXT: lvl %s2756; CHECK-NEXT: vscu.ot %v0, %v1, %s0, %s1, %vm1757; CHECK-NEXT: b.l.t (, %s10)758 tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)759 ret void760}761 762; Function Attrs: nounwind writeonly763declare void @llvm.ve.vl.vscuot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)764 765; Function Attrs: nounwind writeonly766define fastcc void @vscuot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {767; CHECK-LABEL: vscuot_vvssml_imm_1:768; CHECK: # %bb.0:769; CHECK-NEXT: lea %s1, 256770; CHECK-NEXT: lvl %s1771; CHECK-NEXT: vscu.ot %v0, %v1, %s0, 0, %vm1772; CHECK-NEXT: b.l.t (, %s10)773 tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)774 ret void775}776 777; Function Attrs: nounwind writeonly778define fastcc void @vscuot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {779; CHECK-LABEL: vscuot_vvssml_imm_2:780; CHECK: # %bb.0:781; CHECK-NEXT: lea %s1, 256782; CHECK-NEXT: lvl %s1783; CHECK-NEXT: vscu.ot %v0, %v1, 8, %s0, %vm1784; CHECK-NEXT: b.l.t (, %s10)785 tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)786 ret void787}788 789; Function Attrs: nounwind writeonly790define fastcc void @vscuot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {791; CHECK-LABEL: vscuot_vvssml_imm_3:792; CHECK: # %bb.0:793; CHECK-NEXT: lea %s0, 256794; CHECK-NEXT: lvl %s0795; CHECK-NEXT: vscu.ot %v0, %v1, 8, 0, %vm1796; CHECK-NEXT: b.l.t (, %s10)797 tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)798 ret void799}800 801; Function Attrs: nounwind writeonly802define fastcc void @vscuot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {803; CHECK-LABEL: vscuot_vvssl_no_imm_1:804; CHECK: # %bb.0:805; CHECK-NEXT: lea %s1, 256806; CHECK-NEXT: or %s2, 8, (0)1807; CHECK-NEXT: lvl %s1808; CHECK-NEXT: vscu.ot %v0, %v1, %s0, %s2809; CHECK-NEXT: b.l.t (, %s10)810 tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)811 ret void812}813 814; Function Attrs: nounwind writeonly815define fastcc void @vscuncot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {816; CHECK-LABEL: vscuncot_vvssl:817; CHECK: # %bb.0:818; CHECK-NEXT: lea %s2, 256819; CHECK-NEXT: lvl %s2820; CHECK-NEXT: vscu.nc.ot %v0, %v1, %s0, %s1821; CHECK-NEXT: b.l.t (, %s10)822 tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)823 ret void824}825 826; Function Attrs: nounwind writeonly827declare void @llvm.ve.vl.vscuncot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)828 829; Function Attrs: nounwind writeonly830define fastcc void @vscuncot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {831; CHECK-LABEL: vscuncot_vvssl_imm_1:832; CHECK: # %bb.0:833; CHECK-NEXT: lea %s1, 256834; CHECK-NEXT: lvl %s1835; CHECK-NEXT: vscu.nc.ot %v0, %v1, %s0, 0836; CHECK-NEXT: b.l.t (, %s10)837 tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)838 ret void839}840 841; Function Attrs: nounwind writeonly842define fastcc void @vscuncot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {843; CHECK-LABEL: vscuncot_vvssl_imm_2:844; CHECK: # %bb.0:845; CHECK-NEXT: lea %s1, 256846; CHECK-NEXT: lvl %s1847; CHECK-NEXT: vscu.nc.ot %v0, %v1, 8, %s0848; CHECK-NEXT: b.l.t (, %s10)849 tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)850 ret void851}852 853; Function Attrs: nounwind writeonly854define fastcc void @vscuncot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {855; CHECK-LABEL: vscuncot_vvssl_imm_3:856; CHECK: # %bb.0:857; CHECK-NEXT: lea %s0, 256858; CHECK-NEXT: lvl %s0859; CHECK-NEXT: vscu.nc.ot %v0, %v1, 8, 0860; CHECK-NEXT: b.l.t (, %s10)861 tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)862 ret void863}864 865; Function Attrs: nounwind writeonly866define fastcc void @vscuncot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {867; CHECK-LABEL: vscuncot_vvssml:868; CHECK: # %bb.0:869; CHECK-NEXT: lea %s2, 256870; CHECK-NEXT: lvl %s2871; CHECK-NEXT: vscu.nc.ot %v0, %v1, %s0, %s1, %vm1872; CHECK-NEXT: b.l.t (, %s10)873 tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)874 ret void875}876 877; Function Attrs: nounwind writeonly878declare void @llvm.ve.vl.vscuncot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)879 880; Function Attrs: nounwind writeonly881define fastcc void @vscuncot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {882; CHECK-LABEL: vscuncot_vvssml_imm_1:883; CHECK: # %bb.0:884; CHECK-NEXT: lea %s1, 256885; CHECK-NEXT: lvl %s1886; CHECK-NEXT: vscu.nc.ot %v0, %v1, %s0, 0, %vm1887; CHECK-NEXT: b.l.t (, %s10)888 tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)889 ret void890}891 892; Function Attrs: nounwind writeonly893define fastcc void @vscuncot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {894; CHECK-LABEL: vscuncot_vvssml_imm_2:895; CHECK: # %bb.0:896; CHECK-NEXT: lea %s1, 256897; CHECK-NEXT: lvl %s1898; CHECK-NEXT: vscu.nc.ot %v0, %v1, 8, %s0, %vm1899; CHECK-NEXT: b.l.t (, %s10)900 tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)901 ret void902}903 904; Function Attrs: nounwind writeonly905define fastcc void @vscuncot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {906; CHECK-LABEL: vscuncot_vvssml_imm_3:907; CHECK: # %bb.0:908; CHECK-NEXT: lea %s0, 256909; CHECK-NEXT: lvl %s0910; CHECK-NEXT: vscu.nc.ot %v0, %v1, 8, 0, %vm1911; CHECK-NEXT: b.l.t (, %s10)912 tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)913 ret void914}915 916; Function Attrs: nounwind writeonly917define fastcc void @vscuncot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {918; CHECK-LABEL: vscuncot_vvssl_no_imm_1:919; CHECK: # %bb.0:920; CHECK-NEXT: lea %s1, 256921; CHECK-NEXT: or %s2, 8, (0)1922; CHECK-NEXT: lvl %s1923; CHECK-NEXT: vscu.nc.ot %v0, %v1, %s0, %s2924; CHECK-NEXT: b.l.t (, %s10)925 tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)926 ret void927}928 929; Function Attrs: nounwind writeonly930define fastcc void @vscl_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {931; CHECK-LABEL: vscl_vvssl:932; CHECK: # %bb.0:933; CHECK-NEXT: lea %s2, 256934; CHECK-NEXT: lvl %s2935; CHECK-NEXT: vscl %v0, %v1, %s0, %s1936; CHECK-NEXT: b.l.t (, %s10)937 tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)938 ret void939}940 941; Function Attrs: nounwind writeonly942declare void @llvm.ve.vl.vscl.vvssl(<256 x double>, <256 x double>, i64, i64, i32)943 944; Function Attrs: nounwind writeonly945define fastcc void @vscl_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {946; CHECK-LABEL: vscl_vvssl_imm_1:947; CHECK: # %bb.0:948; CHECK-NEXT: lea %s1, 256949; CHECK-NEXT: lvl %s1950; CHECK-NEXT: vscl %v0, %v1, %s0, 0951; CHECK-NEXT: b.l.t (, %s10)952 tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)953 ret void954}955 956; Function Attrs: nounwind writeonly957define fastcc void @vscl_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {958; CHECK-LABEL: vscl_vvssl_imm_2:959; CHECK: # %bb.0:960; CHECK-NEXT: lea %s1, 256961; CHECK-NEXT: lvl %s1962; CHECK-NEXT: vscl %v0, %v1, 8, %s0963; CHECK-NEXT: b.l.t (, %s10)964 tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)965 ret void966}967 968; Function Attrs: nounwind writeonly969define fastcc void @vscl_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {970; CHECK-LABEL: vscl_vvssl_imm_3:971; CHECK: # %bb.0:972; CHECK-NEXT: lea %s0, 256973; CHECK-NEXT: lvl %s0974; CHECK-NEXT: vscl %v0, %v1, 8, 0975; CHECK-NEXT: b.l.t (, %s10)976 tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)977 ret void978}979 980; Function Attrs: nounwind writeonly981define fastcc void @vscl_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {982; CHECK-LABEL: vscl_vvssml:983; CHECK: # %bb.0:984; CHECK-NEXT: lea %s2, 256985; CHECK-NEXT: lvl %s2986; CHECK-NEXT: vscl %v0, %v1, %s0, %s1, %vm1987; CHECK-NEXT: b.l.t (, %s10)988 tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)989 ret void990}991 992; Function Attrs: nounwind writeonly993declare void @llvm.ve.vl.vscl.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)994 995; Function Attrs: nounwind writeonly996define fastcc void @vscl_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {997; CHECK-LABEL: vscl_vvssml_imm_1:998; CHECK: # %bb.0:999; CHECK-NEXT: lea %s1, 2561000; CHECK-NEXT: lvl %s11001; CHECK-NEXT: vscl %v0, %v1, %s0, 0, %vm11002; CHECK-NEXT: b.l.t (, %s10)1003 tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)1004 ret void1005}1006 1007; Function Attrs: nounwind writeonly1008define fastcc void @vscl_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1009; CHECK-LABEL: vscl_vvssml_imm_2:1010; CHECK: # %bb.0:1011; CHECK-NEXT: lea %s1, 2561012; CHECK-NEXT: lvl %s11013; CHECK-NEXT: vscl %v0, %v1, 8, %s0, %vm11014; CHECK-NEXT: b.l.t (, %s10)1015 tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)1016 ret void1017}1018 1019; Function Attrs: nounwind writeonly1020define fastcc void @vscl_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {1021; CHECK-LABEL: vscl_vvssml_imm_3:1022; CHECK: # %bb.0:1023; CHECK-NEXT: lea %s0, 2561024; CHECK-NEXT: lvl %s01025; CHECK-NEXT: vscl %v0, %v1, 8, 0, %vm11026; CHECK-NEXT: b.l.t (, %s10)1027 tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)1028 ret void1029}1030 1031; Function Attrs: nounwind writeonly1032define fastcc void @vscl_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1033; CHECK-LABEL: vscl_vvssl_no_imm_1:1034; CHECK: # %bb.0:1035; CHECK-NEXT: lea %s1, 2561036; CHECK-NEXT: or %s2, 8, (0)11037; CHECK-NEXT: lvl %s11038; CHECK-NEXT: vscl %v0, %v1, %s0, %s21039; CHECK-NEXT: b.l.t (, %s10)1040 tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)1041 ret void1042}1043 1044; Function Attrs: nounwind writeonly1045define fastcc void @vsclnc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {1046; CHECK-LABEL: vsclnc_vvssl:1047; CHECK: # %bb.0:1048; CHECK-NEXT: lea %s2, 2561049; CHECK-NEXT: lvl %s21050; CHECK-NEXT: vscl.nc %v0, %v1, %s0, %s11051; CHECK-NEXT: b.l.t (, %s10)1052 tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)1053 ret void1054}1055 1056; Function Attrs: nounwind writeonly1057declare void @llvm.ve.vl.vsclnc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)1058 1059; Function Attrs: nounwind writeonly1060define fastcc void @vsclnc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1061; CHECK-LABEL: vsclnc_vvssl_imm_1:1062; CHECK: # %bb.0:1063; CHECK-NEXT: lea %s1, 2561064; CHECK-NEXT: lvl %s11065; CHECK-NEXT: vscl.nc %v0, %v1, %s0, 01066; CHECK-NEXT: b.l.t (, %s10)1067 tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)1068 ret void1069}1070 1071; Function Attrs: nounwind writeonly1072define fastcc void @vsclnc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {1073; CHECK-LABEL: vsclnc_vvssl_imm_2:1074; CHECK: # %bb.0:1075; CHECK-NEXT: lea %s1, 2561076; CHECK-NEXT: lvl %s11077; CHECK-NEXT: vscl.nc %v0, %v1, 8, %s01078; CHECK-NEXT: b.l.t (, %s10)1079 tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)1080 ret void1081}1082 1083; Function Attrs: nounwind writeonly1084define fastcc void @vsclnc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {1085; CHECK-LABEL: vsclnc_vvssl_imm_3:1086; CHECK: # %bb.0:1087; CHECK-NEXT: lea %s0, 2561088; CHECK-NEXT: lvl %s01089; CHECK-NEXT: vscl.nc %v0, %v1, 8, 01090; CHECK-NEXT: b.l.t (, %s10)1091 tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)1092 ret void1093}1094 1095; Function Attrs: nounwind writeonly1096define fastcc void @vsclnc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {1097; CHECK-LABEL: vsclnc_vvssml:1098; CHECK: # %bb.0:1099; CHECK-NEXT: lea %s2, 2561100; CHECK-NEXT: lvl %s21101; CHECK-NEXT: vscl.nc %v0, %v1, %s0, %s1, %vm11102; CHECK-NEXT: b.l.t (, %s10)1103 tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)1104 ret void1105}1106 1107; Function Attrs: nounwind writeonly1108declare void @llvm.ve.vl.vsclnc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)1109 1110; Function Attrs: nounwind writeonly1111define fastcc void @vsclnc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1112; CHECK-LABEL: vsclnc_vvssml_imm_1:1113; CHECK: # %bb.0:1114; CHECK-NEXT: lea %s1, 2561115; CHECK-NEXT: lvl %s11116; CHECK-NEXT: vscl.nc %v0, %v1, %s0, 0, %vm11117; CHECK-NEXT: b.l.t (, %s10)1118 tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)1119 ret void1120}1121 1122; Function Attrs: nounwind writeonly1123define fastcc void @vsclnc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1124; CHECK-LABEL: vsclnc_vvssml_imm_2:1125; CHECK: # %bb.0:1126; CHECK-NEXT: lea %s1, 2561127; CHECK-NEXT: lvl %s11128; CHECK-NEXT: vscl.nc %v0, %v1, 8, %s0, %vm11129; CHECK-NEXT: b.l.t (, %s10)1130 tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)1131 ret void1132}1133 1134; Function Attrs: nounwind writeonly1135define fastcc void @vsclnc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {1136; CHECK-LABEL: vsclnc_vvssml_imm_3:1137; CHECK: # %bb.0:1138; CHECK-NEXT: lea %s0, 2561139; CHECK-NEXT: lvl %s01140; CHECK-NEXT: vscl.nc %v0, %v1, 8, 0, %vm11141; CHECK-NEXT: b.l.t (, %s10)1142 tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)1143 ret void1144}1145 1146; Function Attrs: nounwind writeonly1147define fastcc void @vsclnc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1148; CHECK-LABEL: vsclnc_vvssl_no_imm_1:1149; CHECK: # %bb.0:1150; CHECK-NEXT: lea %s1, 2561151; CHECK-NEXT: or %s2, 8, (0)11152; CHECK-NEXT: lvl %s11153; CHECK-NEXT: vscl.nc %v0, %v1, %s0, %s21154; CHECK-NEXT: b.l.t (, %s10)1155 tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)1156 ret void1157}1158 1159; Function Attrs: nounwind writeonly1160define fastcc void @vsclot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {1161; CHECK-LABEL: vsclot_vvssl:1162; CHECK: # %bb.0:1163; CHECK-NEXT: lea %s2, 2561164; CHECK-NEXT: lvl %s21165; CHECK-NEXT: vscl.ot %v0, %v1, %s0, %s11166; CHECK-NEXT: b.l.t (, %s10)1167 tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)1168 ret void1169}1170 1171; Function Attrs: nounwind writeonly1172declare void @llvm.ve.vl.vsclot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)1173 1174; Function Attrs: nounwind writeonly1175define fastcc void @vsclot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1176; CHECK-LABEL: vsclot_vvssl_imm_1:1177; CHECK: # %bb.0:1178; CHECK-NEXT: lea %s1, 2561179; CHECK-NEXT: lvl %s11180; CHECK-NEXT: vscl.ot %v0, %v1, %s0, 01181; CHECK-NEXT: b.l.t (, %s10)1182 tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)1183 ret void1184}1185 1186; Function Attrs: nounwind writeonly1187define fastcc void @vsclot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {1188; CHECK-LABEL: vsclot_vvssl_imm_2:1189; CHECK: # %bb.0:1190; CHECK-NEXT: lea %s1, 2561191; CHECK-NEXT: lvl %s11192; CHECK-NEXT: vscl.ot %v0, %v1, 8, %s01193; CHECK-NEXT: b.l.t (, %s10)1194 tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)1195 ret void1196}1197 1198; Function Attrs: nounwind writeonly1199define fastcc void @vsclot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {1200; CHECK-LABEL: vsclot_vvssl_imm_3:1201; CHECK: # %bb.0:1202; CHECK-NEXT: lea %s0, 2561203; CHECK-NEXT: lvl %s01204; CHECK-NEXT: vscl.ot %v0, %v1, 8, 01205; CHECK-NEXT: b.l.t (, %s10)1206 tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)1207 ret void1208}1209 1210; Function Attrs: nounwind writeonly1211define fastcc void @vsclot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {1212; CHECK-LABEL: vsclot_vvssml:1213; CHECK: # %bb.0:1214; CHECK-NEXT: lea %s2, 2561215; CHECK-NEXT: lvl %s21216; CHECK-NEXT: vscl.ot %v0, %v1, %s0, %s1, %vm11217; CHECK-NEXT: b.l.t (, %s10)1218 tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)1219 ret void1220}1221 1222; Function Attrs: nounwind writeonly1223declare void @llvm.ve.vl.vsclot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)1224 1225; Function Attrs: nounwind writeonly1226define fastcc void @vsclot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1227; CHECK-LABEL: vsclot_vvssml_imm_1:1228; CHECK: # %bb.0:1229; CHECK-NEXT: lea %s1, 2561230; CHECK-NEXT: lvl %s11231; CHECK-NEXT: vscl.ot %v0, %v1, %s0, 0, %vm11232; CHECK-NEXT: b.l.t (, %s10)1233 tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)1234 ret void1235}1236 1237; Function Attrs: nounwind writeonly1238define fastcc void @vsclot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1239; CHECK-LABEL: vsclot_vvssml_imm_2:1240; CHECK: # %bb.0:1241; CHECK-NEXT: lea %s1, 2561242; CHECK-NEXT: lvl %s11243; CHECK-NEXT: vscl.ot %v0, %v1, 8, %s0, %vm11244; CHECK-NEXT: b.l.t (, %s10)1245 tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)1246 ret void1247}1248 1249; Function Attrs: nounwind writeonly1250define fastcc void @vsclot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {1251; CHECK-LABEL: vsclot_vvssml_imm_3:1252; CHECK: # %bb.0:1253; CHECK-NEXT: lea %s0, 2561254; CHECK-NEXT: lvl %s01255; CHECK-NEXT: vscl.ot %v0, %v1, 8, 0, %vm11256; CHECK-NEXT: b.l.t (, %s10)1257 tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)1258 ret void1259}1260 1261; Function Attrs: nounwind writeonly1262define fastcc void @vsclot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1263; CHECK-LABEL: vsclot_vvssl_no_imm_1:1264; CHECK: # %bb.0:1265; CHECK-NEXT: lea %s1, 2561266; CHECK-NEXT: or %s2, 8, (0)11267; CHECK-NEXT: lvl %s11268; CHECK-NEXT: vscl.ot %v0, %v1, %s0, %s21269; CHECK-NEXT: b.l.t (, %s10)1270 tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)1271 ret void1272}1273 1274; Function Attrs: nounwind writeonly1275define fastcc void @vsclncot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {1276; CHECK-LABEL: vsclncot_vvssl:1277; CHECK: # %bb.0:1278; CHECK-NEXT: lea %s2, 2561279; CHECK-NEXT: lvl %s21280; CHECK-NEXT: vscl.nc.ot %v0, %v1, %s0, %s11281; CHECK-NEXT: b.l.t (, %s10)1282 tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)1283 ret void1284}1285 1286; Function Attrs: nounwind writeonly1287declare void @llvm.ve.vl.vsclncot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)1288 1289; Function Attrs: nounwind writeonly1290define fastcc void @vsclncot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1291; CHECK-LABEL: vsclncot_vvssl_imm_1:1292; CHECK: # %bb.0:1293; CHECK-NEXT: lea %s1, 2561294; CHECK-NEXT: lvl %s11295; CHECK-NEXT: vscl.nc.ot %v0, %v1, %s0, 01296; CHECK-NEXT: b.l.t (, %s10)1297 tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)1298 ret void1299}1300 1301; Function Attrs: nounwind writeonly1302define fastcc void @vsclncot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {1303; CHECK-LABEL: vsclncot_vvssl_imm_2:1304; CHECK: # %bb.0:1305; CHECK-NEXT: lea %s1, 2561306; CHECK-NEXT: lvl %s11307; CHECK-NEXT: vscl.nc.ot %v0, %v1, 8, %s01308; CHECK-NEXT: b.l.t (, %s10)1309 tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)1310 ret void1311}1312 1313; Function Attrs: nounwind writeonly1314define fastcc void @vsclncot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {1315; CHECK-LABEL: vsclncot_vvssl_imm_3:1316; CHECK: # %bb.0:1317; CHECK-NEXT: lea %s0, 2561318; CHECK-NEXT: lvl %s01319; CHECK-NEXT: vscl.nc.ot %v0, %v1, 8, 01320; CHECK-NEXT: b.l.t (, %s10)1321 tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)1322 ret void1323}1324 1325; Function Attrs: nounwind writeonly1326define fastcc void @vsclncot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {1327; CHECK-LABEL: vsclncot_vvssml:1328; CHECK: # %bb.0:1329; CHECK-NEXT: lea %s2, 2561330; CHECK-NEXT: lvl %s21331; CHECK-NEXT: vscl.nc.ot %v0, %v1, %s0, %s1, %vm11332; CHECK-NEXT: b.l.t (, %s10)1333 tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)1334 ret void1335}1336 1337; Function Attrs: nounwind writeonly1338declare void @llvm.ve.vl.vsclncot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)1339 1340; Function Attrs: nounwind writeonly1341define fastcc void @vsclncot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1342; CHECK-LABEL: vsclncot_vvssml_imm_1:1343; CHECK: # %bb.0:1344; CHECK-NEXT: lea %s1, 2561345; CHECK-NEXT: lvl %s11346; CHECK-NEXT: vscl.nc.ot %v0, %v1, %s0, 0, %vm11347; CHECK-NEXT: b.l.t (, %s10)1348 tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)1349 ret void1350}1351 1352; Function Attrs: nounwind writeonly1353define fastcc void @vsclncot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {1354; CHECK-LABEL: vsclncot_vvssml_imm_2:1355; CHECK: # %bb.0:1356; CHECK-NEXT: lea %s1, 2561357; CHECK-NEXT: lvl %s11358; CHECK-NEXT: vscl.nc.ot %v0, %v1, 8, %s0, %vm11359; CHECK-NEXT: b.l.t (, %s10)1360 tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)1361 ret void1362}1363 1364; Function Attrs: nounwind writeonly1365define fastcc void @vsclncot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {1366; CHECK-LABEL: vsclncot_vvssml_imm_3:1367; CHECK: # %bb.0:1368; CHECK-NEXT: lea %s0, 2561369; CHECK-NEXT: lvl %s01370; CHECK-NEXT: vscl.nc.ot %v0, %v1, 8, 0, %vm11371; CHECK-NEXT: b.l.t (, %s10)1372 tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)1373 ret void1374}1375 1376; Function Attrs: nounwind writeonly1377define fastcc void @vsclncot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {1378; CHECK-LABEL: vsclncot_vvssl_no_imm_1:1379; CHECK: # %bb.0:1380; CHECK-NEXT: lea %s1, 2561381; CHECK-NEXT: or %s2, 8, (0)11382; CHECK-NEXT: lvl %s11383; CHECK-NEXT: vscl.nc.ot %v0, %v1, %s0, %s21384; CHECK-NEXT: b.l.t (, %s10)1385 tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)1386 ret void1387}1388