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1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector shift left and add intrinsic instructions4;;;5;;; Note:6;;; We test VSFA*vrrl, VSFA*vrrl_v, VSFA*virl, VSFA*virl_v, VSFA*vrrml_v, and7;;; VSFA*virml_v instructions.8 9; Function Attrs: nounwind readnone10define fastcc <256 x double> @vsfa_vvssl(<256 x double> %0, i64 %1, i64 %2) {11; CHECK-LABEL: vsfa_vvssl:12; CHECK: # %bb.0:13; CHECK-NEXT: lea %s2, 25614; CHECK-NEXT: lvl %s215; CHECK-NEXT: vsfa %v0, %v0, %s0, %s116; CHECK-NEXT: b.l.t (, %s10)17 %4 = tail call fast <256 x double> @llvm.ve.vl.vsfa.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)18 ret <256 x double> %419}20 21; Function Attrs: nounwind readnone22declare <256 x double> @llvm.ve.vl.vsfa.vvssl(<256 x double>, i64, i64, i32)23 24; Function Attrs: nounwind readnone25define fastcc <256 x double> @vsfa_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {26; CHECK-LABEL: vsfa_vvssvl:27; CHECK: # %bb.0:28; CHECK-NEXT: lea %s2, 12829; CHECK-NEXT: lvl %s230; CHECK-NEXT: vsfa %v1, %v0, %s0, %s131; CHECK-NEXT: lea %s16, 25632; CHECK-NEXT: lvl %s1633; CHECK-NEXT: vor %v0, (0)1, %v134; CHECK-NEXT: b.l.t (, %s10)35 %5 = tail call fast <256 x double> @llvm.ve.vl.vsfa.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)36 ret <256 x double> %537}38 39; Function Attrs: nounwind readnone40declare <256 x double> @llvm.ve.vl.vsfa.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)41 42; Function Attrs: nounwind readnone43define fastcc <256 x double> @vsfa_vvssl_imm(<256 x double> %0, i64 %1) {44; CHECK-LABEL: vsfa_vvssl_imm:45; CHECK: # %bb.0:46; CHECK-NEXT: lea %s1, 25647; CHECK-NEXT: lvl %s148; CHECK-NEXT: vsfa %v0, %v0, 8, %s049; CHECK-NEXT: b.l.t (, %s10)50 %3 = tail call fast <256 x double> @llvm.ve.vl.vsfa.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)51 ret <256 x double> %352}53 54; Function Attrs: nounwind readnone55define fastcc <256 x double> @vsfa_vvssvl_imm(<256 x double> %0, i64 %1, <256 x double> %2) {56; CHECK-LABEL: vsfa_vvssvl_imm:57; CHECK: # %bb.0:58; CHECK-NEXT: lea %s1, 12859; CHECK-NEXT: lvl %s160; CHECK-NEXT: vsfa %v1, %v0, 8, %s061; CHECK-NEXT: lea %s16, 25662; CHECK-NEXT: lvl %s1663; CHECK-NEXT: vor %v0, (0)1, %v164; CHECK-NEXT: b.l.t (, %s10)65 %4 = tail call fast <256 x double> @llvm.ve.vl.vsfa.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)66 ret <256 x double> %467}68 69; Function Attrs: nounwind readnone70define fastcc <256 x double> @vsfa_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {71; CHECK-LABEL: vsfa_vvssmvl:72; CHECK: # %bb.0:73; CHECK-NEXT: lea %s2, 12874; CHECK-NEXT: lvl %s275; CHECK-NEXT: vsfa %v1, %v0, %s0, %s1, %vm176; CHECK-NEXT: lea %s16, 25677; CHECK-NEXT: lvl %s1678; CHECK-NEXT: vor %v0, (0)1, %v179; CHECK-NEXT: b.l.t (, %s10)80 %6 = tail call fast <256 x double> @llvm.ve.vl.vsfa.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)81 ret <256 x double> %682}83 84; Function Attrs: nounwind readnone85declare <256 x double> @llvm.ve.vl.vsfa.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)86 87; Function Attrs: nounwind readnone88define fastcc <256 x double> @vsfa_vvssmvl_imm(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {89; CHECK-LABEL: vsfa_vvssmvl_imm:90; CHECK: # %bb.0:91; CHECK-NEXT: lea %s1, 12892; CHECK-NEXT: lvl %s193; CHECK-NEXT: vsfa %v1, %v0, 8, %s0, %vm194; CHECK-NEXT: lea %s16, 25695; CHECK-NEXT: lvl %s1696; CHECK-NEXT: vor %v0, (0)1, %v197; CHECK-NEXT: b.l.t (, %s10)98 %5 = tail call fast <256 x double> @llvm.ve.vl.vsfa.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)99 ret <256 x double> %5100}101