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1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s2 3;;; Test vector shift left logical intrinsic instructions4;;;5;;; Note:6;;; We test VSLL*vvl, VSLL*vvl_v, VSLL*vrl, VSLL*vrl_v, VSLL*vil, VSLL*vil_v,7;;; VSLL*vvml_v, VSLL*vrml_v, VSLL*viml_v, PVSLL*vvl, PVSLL*vvl_v, PVSLL*vrl,8;;; PVSLL*vrl_v, PVSLL*vvml_v, and PVSLL*vrml_v instructions.9 10; Function Attrs: nounwind readnone11define fastcc <256 x double> @vsll_vvvl(<256 x double> %0, <256 x double> %1) {12; CHECK-LABEL: vsll_vvvl:13; CHECK: # %bb.0:14; CHECK-NEXT: lea %s0, 25615; CHECK-NEXT: lvl %s016; CHECK-NEXT: vsll %v0, %v0, %v117; CHECK-NEXT: b.l.t (, %s10)18 %3 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvvl(<256 x double> %0, <256 x double> %1, i32 256)19 ret <256 x double> %320}21 22; Function Attrs: nounwind readnone23declare <256 x double> @llvm.ve.vl.vsll.vvvl(<256 x double>, <256 x double>, i32)24 25; Function Attrs: nounwind readnone26define fastcc <256 x double> @vsll_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {27; CHECK-LABEL: vsll_vvvvl:28; CHECK: # %bb.0:29; CHECK-NEXT: lea %s0, 12830; CHECK-NEXT: lvl %s031; CHECK-NEXT: vsll %v2, %v0, %v132; CHECK-NEXT: lea %s16, 25633; CHECK-NEXT: lvl %s1634; CHECK-NEXT: vor %v0, (0)1, %v235; CHECK-NEXT: b.l.t (, %s10)36 %4 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)37 ret <256 x double> %438}39 40; Function Attrs: nounwind readnone41declare <256 x double> @llvm.ve.vl.vsll.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)42 43; Function Attrs: nounwind readnone44define fastcc <256 x double> @vsll_vvsl(<256 x double> %0, i64 %1) {45; CHECK-LABEL: vsll_vvsl:46; CHECK: # %bb.0:47; CHECK-NEXT: lea %s1, 25648; CHECK-NEXT: lvl %s149; CHECK-NEXT: vsll %v0, %v0, %s050; CHECK-NEXT: b.l.t (, %s10)51 %3 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsl(<256 x double> %0, i64 %1, i32 256)52 ret <256 x double> %353}54 55; Function Attrs: nounwind readnone56declare <256 x double> @llvm.ve.vl.vsll.vvsl(<256 x double>, i64, i32)57 58; Function Attrs: nounwind readnone59define fastcc <256 x double> @vsll_vvsvl(<256 x double> %0, i64 %1, <256 x double> %2) {60; CHECK-LABEL: vsll_vvsvl:61; CHECK: # %bb.0:62; CHECK-NEXT: lea %s1, 12863; CHECK-NEXT: lvl %s164; CHECK-NEXT: vsll %v1, %v0, %s065; CHECK-NEXT: lea %s16, 25666; CHECK-NEXT: lvl %s1667; CHECK-NEXT: vor %v0, (0)1, %v168; CHECK-NEXT: b.l.t (, %s10)69 %4 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsvl(<256 x double> %0, i64 %1, <256 x double> %2, i32 128)70 ret <256 x double> %471}72 73; Function Attrs: nounwind readnone74declare <256 x double> @llvm.ve.vl.vsll.vvsvl(<256 x double>, i64, <256 x double>, i32)75 76; Function Attrs: nounwind readnone77define fastcc <256 x double> @vsll_vvsl_imm(<256 x double> %0) {78; CHECK-LABEL: vsll_vvsl_imm:79; CHECK: # %bb.0:80; CHECK-NEXT: lea %s0, 25681; CHECK-NEXT: lvl %s082; CHECK-NEXT: vsll %v0, %v0, 883; CHECK-NEXT: b.l.t (, %s10)84 %2 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsl(<256 x double> %0, i64 8, i32 256)85 ret <256 x double> %286}87 88; Function Attrs: nounwind readnone89define fastcc <256 x double> @vsll_vvsvl_imm(<256 x double> %0, <256 x double> %1) {90; CHECK-LABEL: vsll_vvsvl_imm:91; CHECK: # %bb.0:92; CHECK-NEXT: lea %s0, 12893; CHECK-NEXT: lvl %s094; CHECK-NEXT: vsll %v1, %v0, 895; CHECK-NEXT: lea %s16, 25696; CHECK-NEXT: lvl %s1697; CHECK-NEXT: vor %v0, (0)1, %v198; CHECK-NEXT: b.l.t (, %s10)99 %3 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsvl(<256 x double> %0, i64 8, <256 x double> %1, i32 128)100 ret <256 x double> %3101}102 103; Function Attrs: nounwind readnone104define fastcc <256 x double> @vsll_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {105; CHECK-LABEL: vsll_vvvmvl:106; CHECK: # %bb.0:107; CHECK-NEXT: lea %s0, 128108; CHECK-NEXT: lvl %s0109; CHECK-NEXT: vsll %v2, %v0, %v1, %vm1110; CHECK-NEXT: lea %s16, 256111; CHECK-NEXT: lvl %s16112; CHECK-NEXT: vor %v0, (0)1, %v2113; CHECK-NEXT: b.l.t (, %s10)114 %5 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)115 ret <256 x double> %5116}117 118; Function Attrs: nounwind readnone119declare <256 x double> @llvm.ve.vl.vsll.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)120 121; Function Attrs: nounwind readnone122define fastcc <256 x double> @vsll_vvsmvl(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {123; CHECK-LABEL: vsll_vvsmvl:124; CHECK: # %bb.0:125; CHECK-NEXT: lea %s1, 128126; CHECK-NEXT: lvl %s1127; CHECK-NEXT: vsll %v1, %v0, %s0, %vm1128; CHECK-NEXT: lea %s16, 256129; CHECK-NEXT: lvl %s16130; CHECK-NEXT: vor %v0, (0)1, %v1131; CHECK-NEXT: b.l.t (, %s10)132 %5 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsmvl(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)133 ret <256 x double> %5134}135 136; Function Attrs: nounwind readnone137declare <256 x double> @llvm.ve.vl.vsll.vvsmvl(<256 x double>, i64, <256 x i1>, <256 x double>, i32)138 139; Function Attrs: nounwind readnone140define fastcc <256 x double> @vsll_vvsmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {141; CHECK-LABEL: vsll_vvsmvl_imm:142; CHECK: # %bb.0:143; CHECK-NEXT: lea %s0, 128144; CHECK-NEXT: lvl %s0145; CHECK-NEXT: vsll %v1, %v0, 8, %vm1146; CHECK-NEXT: lea %s16, 256147; CHECK-NEXT: lvl %s16148; CHECK-NEXT: vor %v0, (0)1, %v1149; CHECK-NEXT: b.l.t (, %s10)150 %4 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsmvl(<256 x double> %0, i64 8, <256 x i1> %1, <256 x double> %2, i32 128)151 ret <256 x double> %4152}153 154; Function Attrs: nounwind readnone155define fastcc <256 x double> @pvsll_vvvl(<256 x double> %0, <256 x double> %1) {156; CHECK-LABEL: pvsll_vvvl:157; CHECK: # %bb.0:158; CHECK-NEXT: lea %s0, 256159; CHECK-NEXT: lvl %s0160; CHECK-NEXT: pvsll %v0, %v0, %v1161; CHECK-NEXT: b.l.t (, %s10)162 %3 = tail call fast <256 x double> @llvm.ve.vl.pvsll.vvvl(<256 x double> %0, <256 x double> %1, i32 256)163 ret <256 x double> %3164}165 166; Function Attrs: nounwind readnone167declare <256 x double> @llvm.ve.vl.pvsll.vvvl(<256 x double>, <256 x double>, i32)168 169; Function Attrs: nounwind readnone170define fastcc <256 x double> @pvsll_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {171; CHECK-LABEL: pvsll_vvvvl:172; CHECK: # %bb.0:173; CHECK-NEXT: lea %s0, 128174; CHECK-NEXT: lvl %s0175; CHECK-NEXT: pvsll %v2, %v0, %v1176; CHECK-NEXT: lea %s16, 256177; CHECK-NEXT: lvl %s16178; CHECK-NEXT: vor %v0, (0)1, %v2179; CHECK-NEXT: b.l.t (, %s10)180 %4 = tail call fast <256 x double> @llvm.ve.vl.pvsll.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)181 ret <256 x double> %4182}183 184; Function Attrs: nounwind readnone185declare <256 x double> @llvm.ve.vl.pvsll.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)186 187; Function Attrs: nounwind readnone188define fastcc <256 x double> @pvsll_vvsl(<256 x double> %0, i64 %1) {189; CHECK-LABEL: pvsll_vvsl:190; CHECK: # %bb.0:191; CHECK-NEXT: lea %s1, 256192; CHECK-NEXT: lvl %s1193; CHECK-NEXT: pvsll %v0, %v0, %s0194; CHECK-NEXT: b.l.t (, %s10)195 %3 = tail call fast <256 x double> @llvm.ve.vl.pvsll.vvsl(<256 x double> %0, i64 %1, i32 256)196 ret <256 x double> %3197}198 199; Function Attrs: nounwind readnone200declare <256 x double> @llvm.ve.vl.pvsll.vvsl(<256 x double>, i64, i32)201 202; Function Attrs: nounwind readnone203define fastcc <256 x double> @pvsll_vvsvl(<256 x double> %0, i64 %1, <256 x double> %2) {204; CHECK-LABEL: pvsll_vvsvl:205; CHECK: # %bb.0:206; CHECK-NEXT: lea %s1, 128207; CHECK-NEXT: lvl %s1208; CHECK-NEXT: pvsll %v1, %v0, %s0209; CHECK-NEXT: lea %s16, 256210; CHECK-NEXT: lvl %s16211; CHECK-NEXT: vor %v0, (0)1, %v1212; CHECK-NEXT: b.l.t (, %s10)213 %4 = tail call fast <256 x double> @llvm.ve.vl.pvsll.vvsvl(<256 x double> %0, i64 %1, <256 x double> %2, i32 128)214 ret <256 x double> %4215}216 217; Function Attrs: nounwind readnone218declare <256 x double> @llvm.ve.vl.pvsll.vvsvl(<256 x double>, i64, <256 x double>, i32)219 220; Function Attrs: nounwind readnone221define fastcc <256 x double> @pvsll_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {222; CHECK-LABEL: pvsll_vvvMvl:223; CHECK: # %bb.0:224; CHECK-NEXT: lea %s0, 128225; CHECK-NEXT: lvl %s0226; CHECK-NEXT: pvsll %v2, %v0, %v1, %vm2227; CHECK-NEXT: lea %s16, 256228; CHECK-NEXT: lvl %s16229; CHECK-NEXT: vor %v0, (0)1, %v2230; CHECK-NEXT: b.l.t (, %s10)231 %5 = tail call fast <256 x double> @llvm.ve.vl.pvsll.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)232 ret <256 x double> %5233}234 235; Function Attrs: nounwind readnone236declare <256 x double> @llvm.ve.vl.pvsll.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)237 238; Function Attrs: nounwind readnone239define fastcc <256 x double> @pvsll_vvsMvl(<256 x double> %0, i64 %1, <512 x i1> %2, <256 x double> %3) {240; CHECK-LABEL: pvsll_vvsMvl:241; CHECK: # %bb.0:242; CHECK-NEXT: lea %s1, 128243; CHECK-NEXT: lvl %s1244; CHECK-NEXT: pvsll %v1, %v0, %s0, %vm2245; CHECK-NEXT: lea %s16, 256246; CHECK-NEXT: lvl %s16247; CHECK-NEXT: vor %v0, (0)1, %v1248; CHECK-NEXT: b.l.t (, %s10)249 %5 = tail call fast <256 x double> @llvm.ve.vl.pvsll.vvsMvl(<256 x double> %0, i64 %1, <512 x i1> %2, <256 x double> %3, i32 128)250 ret <256 x double> %5251}252 253; Function Attrs: nounwind readnone254declare <256 x double> @llvm.ve.vl.pvsll.vvsMvl(<256 x double>, i64, <512 x i1>, <256 x double>, i32)255