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1; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s2 3 4;;; <256 x i64>5 6define fastcc <256 x i64> @insert_rr_v256i64(i32 signext %idx, i64 %s) {7; CHECK-LABEL: insert_rr_v256i64:8; CHECK: # %bb.0:9; CHECK-NEXT: and %s0, %s0, (32)010; CHECK-NEXT: lsv %v0(%s0), %s111; CHECK-NEXT: b.l.t (, %s10)12 %ret = insertelement <256 x i64> undef, i64 %s, i32 %idx13 ret <256 x i64> %ret14}15 16define fastcc <256 x i64> @insert_ri7_v256i64(i64 %s) {17; CHECK-LABEL: insert_ri7_v256i64:18; CHECK: # %bb.0:19; CHECK-NEXT: lsv %v0(127), %s020; CHECK-NEXT: b.l.t (, %s10)21 %ret = insertelement <256 x i64> undef, i64 %s, i32 12722 ret <256 x i64> %ret23}24 25define fastcc <256 x i64> @insert_ri8_v256i64(i64 %s) {26; CHECK-LABEL: insert_ri8_v256i64:27; CHECK: # %bb.0:28; CHECK-NEXT: lea %s1, 12829; CHECK-NEXT: lsv %v0(%s1), %s030; CHECK-NEXT: b.l.t (, %s10)31 %ret = insertelement <256 x i64> undef, i64 %s, i32 12832 ret <256 x i64> %ret33}34 35define fastcc <512 x i64> @insert_ri_v512i64(i64 %s) {36; CHECK-LABEL: insert_ri_v512i64:37; CHECK: # %bb.0:38; CHECK-NEXT: lsv %v1(116), %s039; CHECK-NEXT: b.l.t (, %s10)40 %ret = insertelement <512 x i64> undef, i64 %s, i32 37241 ret <512 x i64> %ret42}43 44;;; <256 x i32>45 46define fastcc <256 x i32> @insert_rr_v256i32(i32 signext %idx, i32 signext %s) {47; CHECK-LABEL: insert_rr_v256i32:48; CHECK: # %bb.0:49; CHECK-NEXT: and %s1, %s1, (32)050; CHECK-NEXT: and %s0, %s0, (32)051; CHECK-NEXT: lsv %v0(%s0), %s152; CHECK-NEXT: b.l.t (, %s10)53 %ret = insertelement <256 x i32> undef, i32 %s, i32 %idx54 ret <256 x i32> %ret55}56 57define fastcc <256 x i32> @insert_ri7_v256i32(i32 signext %s) {58; CHECK-LABEL: insert_ri7_v256i32:59; CHECK: # %bb.0:60; CHECK-NEXT: and %s0, %s0, (32)061; CHECK-NEXT: lsv %v0(127), %s062; CHECK-NEXT: b.l.t (, %s10)63 %ret = insertelement <256 x i32> undef, i32 %s, i32 12764 ret <256 x i32> %ret65}66 67define fastcc <256 x i32> @insert_ri8_v256i32(i32 signext %s) {68; CHECK-LABEL: insert_ri8_v256i32:69; CHECK: # %bb.0:70; CHECK-NEXT: and %s0, %s0, (32)071; CHECK-NEXT: lea %s1, 12872; CHECK-NEXT: lsv %v0(%s1), %s073; CHECK-NEXT: b.l.t (, %s10)74 %ret = insertelement <256 x i32> undef, i32 %s, i32 12875 ret <256 x i32> %ret76}77 78define fastcc <512 x i32> @insert_ri_v512i32(i32 signext %s) {79; CHECK-LABEL: insert_ri_v512i32:80; CHECK: # %bb.0:81; CHECK-NEXT: lea %s1, 18682; CHECK-NEXT: lvs %s2, %v0(%s1)83; CHECK-NEXT: and %s2, %s2, (32)084; CHECK-NEXT: sll %s0, %s0, 3285; CHECK-NEXT: or %s0, %s2, %s086; CHECK-NEXT: lsv %v0(%s1), %s087; CHECK-NEXT: b.l.t (, %s10)88 %ret = insertelement <512 x i32> undef, i32 %s, i32 37289 ret <512 x i32> %ret90}91 92define fastcc <512 x i32> @insert_rr_v512i32(i32 signext %idx, i32 signext %s) {93; CHECK-LABEL: insert_rr_v512i32:94; CHECK: # %bb.0:95; CHECK-NEXT: and %s1, %s1, (32)096; CHECK-NEXT: nnd %s2, %s0, (63)097; CHECK-NEXT: sla.w.sx %s2, %s2, 598; CHECK-NEXT: sll %s1, %s1, %s299; CHECK-NEXT: lea %s3, -2100; CHECK-NEXT: and %s3, %s3, (32)0101; CHECK-NEXT: and %s0, %s0, %s3102; CHECK-NEXT: srl %s0, %s0, 1103; CHECK-NEXT: lvs %s3, %v0(%s0)104; CHECK-NEXT: srl %s2, (32)1, %s2105; CHECK-NEXT: and %s2, %s3, %s2106; CHECK-NEXT: or %s1, %s2, %s1107; CHECK-NEXT: lsv %v0(%s0), %s1108; CHECK-NEXT: b.l.t (, %s10)109 %ret = insertelement <512 x i32> undef, i32 %s, i32 %idx110 ret <512 x i32> %ret111}112 113;;; <256 x double>114 115define fastcc <256 x double> @insert_rr_v256f64(i32 signext %idx, double %s) {116; CHECK-LABEL: insert_rr_v256f64:117; CHECK: # %bb.0:118; CHECK-NEXT: and %s0, %s0, (32)0119; CHECK-NEXT: lsv %v0(%s0), %s1120; CHECK-NEXT: b.l.t (, %s10)121 %ret = insertelement <256 x double> undef, double %s, i32 %idx122 ret <256 x double> %ret123}124 125define fastcc <256 x double> @insert_ri7_v256f64(double %s) {126; CHECK-LABEL: insert_ri7_v256f64:127; CHECK: # %bb.0:128; CHECK-NEXT: lsv %v0(127), %s0129; CHECK-NEXT: b.l.t (, %s10)130 %ret = insertelement <256 x double> undef, double %s, i32 127131 ret <256 x double> %ret132}133 134define fastcc <256 x double> @insert_ri8_v256f64(double %s) {135; CHECK-LABEL: insert_ri8_v256f64:136; CHECK: # %bb.0:137; CHECK-NEXT: lea %s1, 128138; CHECK-NEXT: lsv %v0(%s1), %s0139; CHECK-NEXT: b.l.t (, %s10)140 %ret = insertelement <256 x double> undef, double %s, i32 128141 ret <256 x double> %ret142}143 144define fastcc <512 x double> @insert_ri_v512f64(double %s) {145; CHECK-LABEL: insert_ri_v512f64:146; CHECK: # %bb.0:147; CHECK-NEXT: lsv %v1(116), %s0148; CHECK-NEXT: b.l.t (, %s10)149 %ret = insertelement <512 x double> undef, double %s, i32 372150 ret <512 x double> %ret151}152 153;;; <256 x float>154 155define fastcc <256 x float> @insert_rr_v256f32(i32 signext %idx, float %s) {156; CHECK-LABEL: insert_rr_v256f32:157; CHECK: # %bb.0:158; CHECK-NEXT: and %s0, %s0, (32)0159; CHECK-NEXT: lsv %v0(%s0), %s1160; CHECK-NEXT: b.l.t (, %s10)161 %ret = insertelement <256 x float> undef, float %s, i32 %idx162 ret <256 x float> %ret163}164 165define fastcc <256 x float> @insert_ri7_v256f32(float %s) {166; CHECK-LABEL: insert_ri7_v256f32:167; CHECK: # %bb.0:168; CHECK-NEXT: lsv %v0(127), %s0169; CHECK-NEXT: b.l.t (, %s10)170 %ret = insertelement <256 x float> undef, float %s, i32 127171 ret <256 x float> %ret172}173 174define fastcc <256 x float> @insert_ri8_v256f32(float %s) {175; CHECK-LABEL: insert_ri8_v256f32:176; CHECK: # %bb.0:177; CHECK-NEXT: lea %s1, 128178; CHECK-NEXT: lsv %v0(%s1), %s0179; CHECK-NEXT: b.l.t (, %s10)180 %ret = insertelement <256 x float> undef, float %s, i32 128181 ret <256 x float> %ret182}183 184define fastcc <512 x float> @insert_ri_v512f32(float %s) {185; CHECK-LABEL: insert_ri_v512f32:186; CHECK: # %bb.0:187; CHECK-NEXT: sra.l %s0, %s0, 32188; CHECK-NEXT: lea %s1, 186189; CHECK-NEXT: lvs %s2, %v0(%s1)190; CHECK-NEXT: and %s2, %s2, (32)0191; CHECK-NEXT: sll %s0, %s0, 32192; CHECK-NEXT: or %s0, %s2, %s0193; CHECK-NEXT: lsv %v0(%s1), %s0194; CHECK-NEXT: b.l.t (, %s10)195 %ret = insertelement <512 x float> undef, float %s, i32 372196 ret <512 x float> %ret197}198 199define fastcc <512 x float> @insert_rr_v512f32(i32 signext %idx, float %s) {200; CHECK-LABEL: insert_rr_v512f32:201; CHECK: # %bb.0:202; CHECK-NEXT: sra.l %s1, %s1, 32203; CHECK-NEXT: lea %s2, -2204; CHECK-NEXT: and %s2, %s2, (32)0205; CHECK-NEXT: and %s2, %s0, %s2206; CHECK-NEXT: srl %s2, %s2, 1207; CHECK-NEXT: lvs %s3, %v0(%s2)208; CHECK-NEXT: nnd %s0, %s0, (63)0209; CHECK-NEXT: sla.w.sx %s0, %s0, 5210; CHECK-NEXT: srl %s4, (32)1, %s0211; CHECK-NEXT: and %s3, %s3, %s4212; CHECK-NEXT: adds.w.zx %s1, %s1, (0)1213; CHECK-NEXT: sll %s0, %s1, %s0214; CHECK-NEXT: or %s0, %s3, %s0215; CHECK-NEXT: lsv %v0(%s2), %s0216; CHECK-NEXT: b.l.t (, %s10)217 %ret = insertelement <512 x float> undef, float %s, i32 %idx218 ret <512 x float> %ret219}220