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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x float> @llvm.fma.v256f32(<256 x float>, <256 x float>, <256 x float>)5 6define fastcc <256 x float> @test_vec_fma_v256f32_vvv(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2) {7; CHECK-LABEL: test_vec_fma_v256f32_vvv:8; CHECK: # %bb.0:9; CHECK-NEXT: lea %s0, 25610; CHECK-NEXT: lvl %s011; CHECK-NEXT: vfmad.s %v0, %v2, %v0, %v112; CHECK-NEXT: b.l.t (, %s10)13 %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)14 ret <256 x float> %r015}16 17define fastcc <256 x float> @test_vec_fma_v256f32_rvv(float %s0, <256 x float> %i1, <256 x float> %i2) {18; CHECK-LABEL: test_vec_fma_v256f32_rvv:19; CHECK: # %bb.0:20; CHECK-NEXT: lea %s1, 25621; CHECK-NEXT: lvl %s122; CHECK-NEXT: vfmad.s %v0, %v1, %s0, %v023; CHECK-NEXT: b.l.t (, %s10)24 %xins = insertelement <256 x float> undef, float %s0, i32 025 %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer26 %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)27 ret <256 x float> %r028}29 30define fastcc <256 x float> @test_vec_fma_v256f32_vrv(<256 x float> %i0, float %s1, <256 x float> %i2) {31; CHECK-LABEL: test_vec_fma_v256f32_vrv:32; CHECK: # %bb.0:33; CHECK-NEXT: lea %s1, 25634; CHECK-NEXT: lvl %s135; CHECK-NEXT: vfmad.s %v0, %v1, %s0, %v036; CHECK-NEXT: b.l.t (, %s10)37 %yins = insertelement <256 x float> undef, float %s1, i32 038 %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer39 %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)40 ret <256 x float> %r041}42 43define fastcc <256 x float> @test_vec_fma_v256f32_vvr(<256 x float> %i0, <256 x float> %i1, float %s2) {44; CHECK-LABEL: test_vec_fma_v256f32_vvr:45; CHECK: # %bb.0:46; CHECK-NEXT: lea %s1, 25647; CHECK-NEXT: lvl %s148; CHECK-NEXT: vfmad.s %v0, %s0, %v0, %v149; CHECK-NEXT: b.l.t (, %s10)50 %zins = insertelement <256 x float> undef, float %s2, i32 051 %i2 = shufflevector <256 x float> %zins, <256 x float> undef, <256 x i32> zeroinitializer52 %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)53 ret <256 x float> %r054}55 56declare <256 x double> @llvm.fma.v256f64(<256 x double>, <256 x double>, <256 x double>)57 58define fastcc <256 x double> @test_vec_fma_v256f64_vvv(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2) {59; CHECK-LABEL: test_vec_fma_v256f64_vvv:60; CHECK: # %bb.0:61; CHECK-NEXT: lea %s0, 25662; CHECK-NEXT: lvl %s063; CHECK-NEXT: vfmad.d %v0, %v2, %v0, %v164; CHECK-NEXT: b.l.t (, %s10)65 %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)66 ret <256 x double> %r067}68 69define fastcc <256 x double> @test_vec_fma_v256f64_rvv(double %s0, <256 x double> %i1, <256 x double> %i2) {70; CHECK-LABEL: test_vec_fma_v256f64_rvv:71; CHECK: # %bb.0:72; CHECK-NEXT: lea %s1, 25673; CHECK-NEXT: lvl %s174; CHECK-NEXT: vfmad.d %v0, %v1, %s0, %v075; CHECK-NEXT: b.l.t (, %s10)76 %xins = insertelement <256 x double> undef, double %s0, i32 077 %i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer78 %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)79 ret <256 x double> %r080}81 82define fastcc <256 x double> @test_vec_fma_v256f64_vrv(<256 x double> %i0, double %s1, <256 x double> %i2) {83; CHECK-LABEL: test_vec_fma_v256f64_vrv:84; CHECK: # %bb.0:85; CHECK-NEXT: lea %s1, 25686; CHECK-NEXT: lvl %s187; CHECK-NEXT: vfmad.d %v0, %v1, %s0, %v088; CHECK-NEXT: b.l.t (, %s10)89 %yins = insertelement <256 x double> undef, double %s1, i32 090 %i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer91 %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)92 ret <256 x double> %r093}94 95define fastcc <256 x double> @test_vec_fma_v256f64_vvr(<256 x double> %i0, <256 x double> %i1, double %s2) {96; CHECK-LABEL: test_vec_fma_v256f64_vvr:97; CHECK: # %bb.0:98; CHECK-NEXT: lea %s1, 25699; CHECK-NEXT: lvl %s1100; CHECK-NEXT: vfmad.d %v0, %s0, %v0, %v1101; CHECK-NEXT: b.l.t (, %s10)102 %zins = insertelement <256 x double> undef, double %s2, i32 0103 %i2 = shufflevector <256 x double> %zins, <256 x double> undef, <256 x i32> zeroinitializer104 %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)105 ret <256 x double> %r0106}107