128 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s3 4declare <128 x double> @llvm.masked.load.v128f64.p0(ptr %0, i32 immarg %1, <128 x i1> %2, <128 x double> %3) #05 6; TODO: Custom widen by lowering to vvp_load in ReplaceNodeResult7; Function Attrs: nounwind8; define fastcc <128 x double> @vec_mload_v128f64(ptr %P, <128 x i1> %M) {9; %r = call <128 x double> @llvm.masked.load.v128f64.p0(ptr %P, i32 16, <128 x i1> %M, <128 x double> undef)10; ret <128 x double> %r11; }12 13 14declare <256 x double> @llvm.masked.load.v256f64.p0(ptr %0, i32 immarg %1, <256 x i1> %2, <256 x double> %3) #015 16; Function Attrs: nounwind17define fastcc <256 x double> @vec_mload_v256f64(ptr %P, <256 x i1> %M) {18; CHECK-LABEL: vec_mload_v256f64:19; CHECK: # %bb.0:20; CHECK-NEXT: lea %s1, 25621; CHECK-NEXT: lvl %s122; CHECK-NEXT: vseq %v023; CHECK-NEXT: vmulu.l %v0, 8, %v0, %vm124; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm125; CHECK-NEXT: vgt %v0, %v0, 0, 0, %vm126; CHECK-NEXT: b.l.t (, %s10)27 %r = call <256 x double> @llvm.masked.load.v256f64.p0(ptr %P, i32 16, <256 x i1> %M, <256 x double> undef)28 ret <256 x double> %r29}30 31; Function Attrs: nounwind32define fastcc <256 x double> @vec_load_v256f64(ptr %P) {33; CHECK-LABEL: vec_load_v256f64:34; CHECK: # %bb.0:35; CHECK-NEXT: lea %s1, 25636; CHECK-NEXT: lvl %s137; CHECK-NEXT: vld %v0, 8, %s038; CHECK-NEXT: b.l.t (, %s10)39 %r = load <256 x double>, ptr %P, align 440 ret <256 x double> %r41}42 43; Function Attrs: nounwind44define fastcc <256 x double> @vec_mload_pt_v256f64(ptr %P, <256 x double> %PT, <256 x i1> %M) {45; CHECK-LABEL: vec_mload_pt_v256f64:46; CHECK: # %bb.0:47; CHECK-NEXT: lea %s1, 25648; CHECK-NEXT: lvl %s149; CHECK-NEXT: vseq %v150; CHECK-NEXT: vmulu.l %v1, 8, %v1, %vm151; CHECK-NEXT: vaddu.l %v1, %s0, %v1, %vm152; CHECK-NEXT: vgt %v1, %v1, 0, 0, %vm153; CHECK-NEXT: vmrg %v0, %v0, %v1, %vm154; CHECK-NEXT: b.l.t (, %s10)55 %r = call <256 x double> @llvm.masked.load.v256f64.p0(ptr %P, i32 16, <256 x i1> %M, <256 x double> %PT)56 ret <256 x double> %r57}58 59 60declare <256 x float> @llvm.masked.load.v256f32.p0(ptr %0, i32 immarg %1, <256 x i1> %2, <256 x float> %3) #061 62; Function Attrs: nounwind63define fastcc <256 x float> @vec_mload_v256f32(ptr %P, <256 x i1> %M) {64; CHECK-LABEL: vec_mload_v256f32:65; CHECK: # %bb.0:66; CHECK-NEXT: lea %s1, 25667; CHECK-NEXT: lvl %s168; CHECK-NEXT: vseq %v069; CHECK-NEXT: vmulu.l %v0, 4, %v0, %vm170; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm171; CHECK-NEXT: vgtu %v0, %v0, 0, 0, %vm172; CHECK-NEXT: b.l.t (, %s10)73 %r = call <256 x float> @llvm.masked.load.v256f32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x float> undef)74 ret <256 x float> %r75}76 77; Function Attrs: nounwind78define fastcc <256 x float> @vec_mload_pt_v256f32(ptr %P, <256 x float> %PT, <256 x i1> %M) {79; CHECK-LABEL: vec_mload_pt_v256f32:80; CHECK: # %bb.0:81; CHECK-NEXT: lea %s1, 25682; CHECK-NEXT: lvl %s183; CHECK-NEXT: vseq %v184; CHECK-NEXT: vmulu.l %v1, 4, %v1, %vm185; CHECK-NEXT: vaddu.l %v1, %s0, %v1, %vm186; CHECK-NEXT: vgtu %v1, %v1, 0, 0, %vm187; CHECK-NEXT: vmrg %v0, %v0, %v1, %vm188; CHECK-NEXT: b.l.t (, %s10)89 %r = call <256 x float> @llvm.masked.load.v256f32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x float> %PT)90 ret <256 x float> %r91}92 93 94declare <256 x i32> @llvm.masked.load.v256i32.p0(ptr %0, i32 immarg %1, <256 x i1> %2, <256 x i32> %3) #095 96; Function Attrs: nounwind97define fastcc <256 x i32> @vec_mload_v256i32(ptr %P, <256 x i1> %M) {98; CHECK-LABEL: vec_mload_v256i32:99; CHECK: # %bb.0:100; CHECK-NEXT: lea %s1, 256101; CHECK-NEXT: lvl %s1102; CHECK-NEXT: vseq %v0103; CHECK-NEXT: vmulu.l %v0, 4, %v0, %vm1104; CHECK-NEXT: vaddu.l %v0, %s0, %v0, %vm1105; CHECK-NEXT: vgtl.zx %v0, %v0, 0, 0, %vm1106; CHECK-NEXT: b.l.t (, %s10)107 %r = call <256 x i32> @llvm.masked.load.v256i32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x i32> undef)108 ret <256 x i32> %r109}110 111; Function Attrs: nounwind112define fastcc <256 x i32> @vec_mload_pt_v256i32(ptr %P, <256 x i32> %PT, <256 x i1> %M) {113; CHECK-LABEL: vec_mload_pt_v256i32:114; CHECK: # %bb.0:115; CHECK-NEXT: lea %s1, 256116; CHECK-NEXT: lvl %s1117; CHECK-NEXT: vseq %v1118; CHECK-NEXT: vmulu.l %v1, 4, %v1, %vm1119; CHECK-NEXT: vaddu.l %v1, %s0, %v1, %vm1120; CHECK-NEXT: vgtl.zx %v1, %v1, 0, 0, %vm1121; CHECK-NEXT: vmrg %v0, %v0, %v1, %vm1122; CHECK-NEXT: b.l.t (, %s10)123 %r = call <256 x i32> @llvm.masked.load.v256i32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x i32> %PT)124 ret <256 x i32> %r125}126 127attributes #0 = { argmemonly nounwind readonly willreturn }128