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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s3 4declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>)5 6define fastcc i64 @vec_reduce_xor_v256i64(<256 x i64> %v) {7; CHECK-LABEL: vec_reduce_xor_v256i64:8; CHECK: # %bb.0:9; CHECK-NEXT: lea %s0, 25610; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx011; CHECK-NEXT: lvl %s012; CHECK-NEXT: vrxor %v0, %v013; CHECK-NEXT: lvs %s0, %v0(0)14; CHECK-NEXT: b.l.t (, %s10)15 %r = call i64 @llvm.vector.reduce.xor.v256i64( <256 x i64> %v)16 ret i64 %r17}18 19declare i32 @llvm.vector.reduce.xor.v256i32(<256 x i32>)20 21define fastcc i32 @vec_reduce_xor_v256i32(<256 x i32> %v) {22; CHECK-LABEL: vec_reduce_xor_v256i32:23; CHECK: # %bb.0:24; CHECK-NEXT: lea %s0, 25625; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx026; CHECK-NEXT: lvl %s027; CHECK-NEXT: vrxor %v0, %v028; CHECK-NEXT: lvs %s0, %v0(0)29; CHECK-NEXT: or %s1, 0, %s030; CHECK-NEXT: # implicit-def: $sx031; CHECK-NEXT: or %s0, 0, %s132; CHECK-NEXT: b.l.t (, %s10)33 %r = call i32 @llvm.vector.reduce.xor.v256i32( <256 x i32> %v)34 ret i32 %r35}36