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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x i32> @llvm.vec.select.v256i32(<256 x i1>, <256 x i32>, <256 x i32>, i32)5 6define fastcc <256 x i32> @test_vec_select_v256i32_vv(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m) {7; CHECK-LABEL: test_vec_select_v256i32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: lea %s0, 25610; CHECK-NEXT: lvl %s011; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm112; CHECK-NEXT: lea %s16, 25613; CHECK-NEXT: lvl %s1614; CHECK-NEXT: vor %v0, (0)1, %v115; CHECK-NEXT: b.l.t (, %s10)16 %r0 = select <256 x i1> %m, <256 x i32> %i0, <256 x i32> %i117 ret <256 x i32> %r018}19 20define fastcc <256 x i32> @test_vec_select_v256i32_vr(<256 x i32> %i0, i32 %s1, <256 x i1> %m) {21; CHECK-LABEL: test_vec_select_v256i32_vr:22; CHECK: # %bb.0:23; CHECK-NEXT: and %s0, %s0, (32)024; CHECK-NEXT: lea %s1, 25625; CHECK-NEXT: lvl %s126; CHECK-NEXT: vbrd %v1, %s027; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm128; CHECK-NEXT: lea %s16, 25629; CHECK-NEXT: lvl %s1630; CHECK-NEXT: vor %v0, (0)1, %v131; CHECK-NEXT: b.l.t (, %s10)32 %xins = insertelement <256 x i32> undef, i32 %s1, i32 033 %i1 = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer34 %r0 = select <256 x i1> %m, <256 x i32> %i0, <256 x i32> %i135 ret <256 x i32> %r036}37 38declare <256 x float> @llvm.vec.select.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)39 40define fastcc <256 x float> @test_vec_select_v256f32_vv(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m) {41; CHECK-LABEL: test_vec_select_v256f32_vv:42; CHECK: # %bb.0:43; CHECK-NEXT: lea %s0, 25644; CHECK-NEXT: lvl %s045; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm146; CHECK-NEXT: lea %s16, 25647; CHECK-NEXT: lvl %s1648; CHECK-NEXT: vor %v0, (0)1, %v149; CHECK-NEXT: b.l.t (, %s10)50 %r0 = select <256 x i1> %m, <256 x float> %i0, <256 x float> %i151 ret <256 x float> %r052}53 54define fastcc <256 x float> @test_vec_select_v256f32_vr(<256 x float> %i0, float %s1, <256 x i1> %m) {55; CHECK-LABEL: test_vec_select_v256f32_vr:56; CHECK: # %bb.0:57; CHECK-NEXT: lea %s1, 25658; CHECK-NEXT: lvl %s159; CHECK-NEXT: vbrd %v1, %s060; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm161; CHECK-NEXT: lea %s16, 25662; CHECK-NEXT: lvl %s1663; CHECK-NEXT: vor %v0, (0)1, %v164; CHECK-NEXT: b.l.t (, %s10)65 %xins = insertelement <256 x float> undef, float %s1, i32 066 %i1 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer67 %r0 = select <256 x i1> %m, <256 x float> %i0, <256 x float> %i168 ret <256 x float> %r069}70 71declare <256 x double> @llvm.vec.select.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)72 73define fastcc <256 x double> @test_vec_select_v256f64_vv(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m) {74; CHECK-LABEL: test_vec_select_v256f64_vv:75; CHECK: # %bb.0:76; CHECK-NEXT: lea %s0, 25677; CHECK-NEXT: lvl %s078; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm179; CHECK-NEXT: lea %s16, 25680; CHECK-NEXT: lvl %s1681; CHECK-NEXT: vor %v0, (0)1, %v182; CHECK-NEXT: b.l.t (, %s10)83 %r0 = select <256 x i1> %m, <256 x double> %i0, <256 x double> %i184 ret <256 x double> %r085}86 87define fastcc <256 x double> @test_vec_select_v256f64_vr(<256 x double> %i0, double %s1, <256 x i1> %m) {88; CHECK-LABEL: test_vec_select_v256f64_vr:89; CHECK: # %bb.0:90; CHECK-NEXT: lea %s1, 25691; CHECK-NEXT: lvl %s192; CHECK-NEXT: vbrd %v1, %s093; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm194; CHECK-NEXT: lea %s16, 25695; CHECK-NEXT: lvl %s1696; CHECK-NEXT: vor %v0, (0)1, %v197; CHECK-NEXT: b.l.t (, %s10)98 %xins = insertelement <256 x double> undef, double %s1, i32 099 %i1 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer100 %r0 = select <256 x i1> %m, <256 x double> %i0, <256 x double> %i1101 ret <256 x double> %r0102}103 104declare <256 x i64> @llvm.vec.select.v256i64(<256 x i1>, <256 x i64>, <256 x i64>, i32)105 106define fastcc <256 x i64> @test_vec_select_v256i64_vv(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m) {107; CHECK-LABEL: test_vec_select_v256i64_vv:108; CHECK: # %bb.0:109; CHECK-NEXT: lea %s0, 256110; CHECK-NEXT: lvl %s0111; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm1112; CHECK-NEXT: lea %s16, 256113; CHECK-NEXT: lvl %s16114; CHECK-NEXT: vor %v0, (0)1, %v1115; CHECK-NEXT: b.l.t (, %s10)116 %r0 = select <256 x i1> %m, <256 x i64> %i0, <256 x i64> %i1117 ret <256 x i64> %r0118}119 120define fastcc <256 x i64> @test_vec_select_v256i64_vr(<256 x i64> %i0, i64 %s1, <256 x i1> %m) {121; CHECK-LABEL: test_vec_select_v256i64_vr:122; CHECK: # %bb.0:123; CHECK-NEXT: lea %s1, 256124; CHECK-NEXT: lvl %s1125; CHECK-NEXT: vbrd %v1, %s0126; CHECK-NEXT: vmrg %v1, %v1, %v0, %vm1127; CHECK-NEXT: lea %s16, 256128; CHECK-NEXT: lvl %s16129; CHECK-NEXT: vor %v0, (0)1, %v1130; CHECK-NEXT: b.l.t (, %s10)131 %xins = insertelement <256 x i64> undef, i64 %s1, i32 0132 %i1 = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer133 %r0 = select <256 x i1> %m, <256 x i64> %i0, <256 x i64> %i1134 ret <256 x i64> %r0135}136