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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)5declare <256 x float> @llvm.vp.fma.v256f32(<256 x float>, <256 x float>, <256 x float>, <256 x i1>, i32)6 7define fastcc <256 x float> @test_vp_fma_v256f32_vvv_merge(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {8; CHECK-LABEL: test_vp_fma_v256f32_vvv_merge:9; CHECK: # %bb.0:10; CHECK-NEXT: and %s0, %s0, (32)011; CHECK-NEXT: lvl %s012; CHECK-NEXT: vfmad.s %v3, %v2, %v0, %v1, %vm113; CHECK-NEXT: lea %s16, 25614; CHECK-NEXT: lvl %s1615; CHECK-NEXT: vor %v0, (0)1, %v316; CHECK-NEXT: b.l.t (, %s10)17 %vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)18 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)19 ret <256 x float> %r020}21 22define fastcc <256 x float> @test_vp_fma_v256f32_rvv_merge(float %s0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {23; CHECK-LABEL: test_vp_fma_v256f32_rvv_merge:24; CHECK: # %bb.0:25; CHECK-NEXT: and %s1, %s1, (32)026; CHECK-NEXT: lvl %s127; CHECK-NEXT: vfmad.s %v2, %v1, %s0, %v0, %vm128; CHECK-NEXT: lea %s16, 25629; CHECK-NEXT: lvl %s1630; CHECK-NEXT: vor %v0, (0)1, %v231; CHECK-NEXT: b.l.t (, %s10)32 %xins = insertelement <256 x float> undef, float %s0, i32 033 %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer34 %vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)35 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)36 ret <256 x float> %r037}38 39define fastcc <256 x float> @test_vp_fma_v256f32_vrv_merge(<256 x float> %i0, float %s1, <256 x float> %i2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {40; CHECK-LABEL: test_vp_fma_v256f32_vrv_merge:41; CHECK: # %bb.0:42; CHECK-NEXT: and %s1, %s1, (32)043; CHECK-NEXT: lvl %s144; CHECK-NEXT: vfmad.s %v2, %v1, %s0, %v0, %vm145; CHECK-NEXT: lea %s16, 25646; CHECK-NEXT: lvl %s1647; CHECK-NEXT: vor %v0, (0)1, %v248; CHECK-NEXT: b.l.t (, %s10)49 %yins = insertelement <256 x float> undef, float %s1, i32 050 %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer51 %vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)52 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)53 ret <256 x float> %r054}55 56define fastcc <256 x float> @test_vp_fma_v256f32_vvr_merge(<256 x float> %i0, <256 x float> %i1, float %s2, <256 x i1> %m, i32 %n, <256 x float> %passthru) {57; CHECK-LABEL: test_vp_fma_v256f32_vvr_merge:58; CHECK: # %bb.0:59; CHECK-NEXT: and %s1, %s1, (32)060; CHECK-NEXT: lvl %s161; CHECK-NEXT: vfmad.s %v2, %s0, %v0, %v1, %vm162; CHECK-NEXT: lea %s16, 25663; CHECK-NEXT: lvl %s1664; CHECK-NEXT: vor %v0, (0)1, %v265; CHECK-NEXT: b.l.t (, %s10)66 %zins = insertelement <256 x float> undef, float %s2, i32 067 %i2 = shufflevector <256 x float> %zins, <256 x float> undef, <256 x i32> zeroinitializer68 %vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2, <256 x i1> %m, i32 %n)69 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)70 ret <256 x float> %r071}72