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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x float> @llvm.vp.fsub.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)5 6define fastcc <256 x float> @test_vp_fsub_v256f32_vv(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {7; CHECK-LABEL: test_vp_fsub_v256f32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: and %s0, %s0, (32)010; CHECK-NEXT: lvl %s011; CHECK-NEXT: pvfsub.up %v0, %v0, %v1, %vm112; CHECK-NEXT: b.l.t (, %s10)13 %r0 = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)14 ret <256 x float> %r015}16 17define fastcc <256 x float> @test_vp_fsub_v256f32_rv(float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {18; CHECK-LABEL: test_vp_fsub_v256f32_rv:19; CHECK: # %bb.0:20; CHECK-NEXT: and %s1, %s1, (32)021; CHECK-NEXT: lvl %s122; CHECK-NEXT: pvfsub.up %v0, %s0, %v0, %vm123; CHECK-NEXT: b.l.t (, %s10)24 %xins = insertelement <256 x float> undef, float %s0, i32 025 %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer26 %r0 = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)27 ret <256 x float> %r028}29 30define fastcc <256 x float> @test_vp_fsub_v256f32_vr(<256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {31; CHECK-LABEL: test_vp_fsub_v256f32_vr:32; CHECK: # %bb.0:33; CHECK-NEXT: and %s1, %s1, (32)034; CHECK-NEXT: lea %s2, 25635; CHECK-NEXT: lvl %s236; CHECK-NEXT: vbrd %v1, %s037; CHECK-NEXT: lvl %s138; CHECK-NEXT: pvfsub.up %v0, %v0, %v1, %vm139; CHECK-NEXT: b.l.t (, %s10)40 %yins = insertelement <256 x float> undef, float %s1, i32 041 %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer42 %r0 = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)43 ret <256 x float> %r044}45 46 47declare <256 x double> @llvm.vp.fsub.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)48 49define fastcc <256 x double> @test_vp_fsub_v256f64_vv(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {50; CHECK-LABEL: test_vp_fsub_v256f64_vv:51; CHECK: # %bb.0:52; CHECK-NEXT: and %s0, %s0, (32)053; CHECK-NEXT: lvl %s054; CHECK-NEXT: vfsub.d %v0, %v0, %v1, %vm155; CHECK-NEXT: b.l.t (, %s10)56 %r0 = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)57 ret <256 x double> %r058}59 60define fastcc <256 x double> @test_vp_fsub_v256f64_rv(double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {61; CHECK-LABEL: test_vp_fsub_v256f64_rv:62; CHECK: # %bb.0:63; CHECK-NEXT: and %s1, %s1, (32)064; CHECK-NEXT: lvl %s165; CHECK-NEXT: vfsub.d %v0, %s0, %v0, %vm166; CHECK-NEXT: b.l.t (, %s10)67 %xins = insertelement <256 x double> undef, double %s0, i32 068 %i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer69 %r0 = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)70 ret <256 x double> %r071}72 73define fastcc <256 x double> @test_vp_fsub_v256f64_vr(<256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {74; CHECK-LABEL: test_vp_fsub_v256f64_vr:75; CHECK: # %bb.0:76; CHECK-NEXT: and %s1, %s1, (32)077; CHECK-NEXT: lea %s2, 25678; CHECK-NEXT: lvl %s279; CHECK-NEXT: vbrd %v1, %s080; CHECK-NEXT: lvl %s181; CHECK-NEXT: vfsub.d %v0, %v0, %v1, %vm182; CHECK-NEXT: b.l.t (, %s10)83 %yins = insertelement <256 x double> undef, double %s1, i32 084 %i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer85 %r0 = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)86 ret <256 x double> %r087}88