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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)5declare <256 x float> @llvm.vp.fsub.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)6 7define fastcc <256 x float> @test_vp_fsub_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {8; CHECK-LABEL: test_vp_fsub_v256f32_vv_merge:9; CHECK: # %bb.0:10; CHECK-NEXT: and %s0, %s0, (32)011; CHECK-NEXT: lvl %s012; CHECK-NEXT: pvfsub.up %v0, %v1, %v2, %vm113; CHECK-NEXT: b.l.t (, %s10)14 %vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)15 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)16 ret <256 x float> %r017}18 19define fastcc <256 x float> @test_vp_fsub_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {20; CHECK-LABEL: test_vp_fsub_v256f32_rv_merge:21; CHECK: # %bb.0:22; CHECK-NEXT: and %s1, %s1, (32)023; CHECK-NEXT: lvl %s124; CHECK-NEXT: pvfsub.up %v0, %s0, %v1, %vm125; CHECK-NEXT: b.l.t (, %s10)26 %xins = insertelement <256 x float> undef, float %s0, i32 027 %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer28 %vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)29 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)30 ret <256 x float> %r031}32 33define fastcc <256 x float> @test_vp_fsub_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {34; CHECK-LABEL: test_vp_fsub_v256f32_vr_merge:35; CHECK: # %bb.0:36; CHECK-NEXT: and %s1, %s1, (32)037; CHECK-NEXT: lea %s2, 25638; CHECK-NEXT: lvl %s239; CHECK-NEXT: vbrd %v2, %s040; CHECK-NEXT: lvl %s141; CHECK-NEXT: pvfsub.up %v0, %v1, %v2, %vm142; CHECK-NEXT: b.l.t (, %s10)43 %yins = insertelement <256 x float> undef, float %s1, i32 044 %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer45 %vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)46 %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)47 ret <256 x float> %r048}49 50 51declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)52declare <256 x double> @llvm.vp.fsub.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)53 54define fastcc <256 x double> @test_vp_fsub_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {55; CHECK-LABEL: test_vp_fsub_v256f64_vv_merge:56; CHECK: # %bb.0:57; CHECK-NEXT: and %s0, %s0, (32)058; CHECK-NEXT: lvl %s059; CHECK-NEXT: vfsub.d %v0, %v1, %v2, %vm160; CHECK-NEXT: b.l.t (, %s10)61 %vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)62 %r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)63 ret <256 x double> %r064}65 66define fastcc <256 x double> @test_vp_fsub_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {67; CHECK-LABEL: test_vp_fsub_v256f64_rv_merge:68; CHECK: # %bb.0:69; CHECK-NEXT: and %s1, %s1, (32)070; CHECK-NEXT: lvl %s171; CHECK-NEXT: vfsub.d %v0, %s0, %v1, %vm172; CHECK-NEXT: b.l.t (, %s10)73 %xins = insertelement <256 x double> undef, double %s0, i32 074 %i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer75 %vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)76 %r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)77 ret <256 x double> %r078}79 80define fastcc <256 x double> @test_vp_fsub_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {81; CHECK-LABEL: test_vp_fsub_v256f64_vr_merge:82; CHECK: # %bb.0:83; CHECK-NEXT: and %s1, %s1, (32)084; CHECK-NEXT: lea %s2, 25685; CHECK-NEXT: lvl %s286; CHECK-NEXT: vbrd %v2, %s087; CHECK-NEXT: lvl %s188; CHECK-NEXT: vfsub.d %v0, %v1, %v2, %vm189; CHECK-NEXT: b.l.t (, %s10)90 %yins = insertelement <256 x double> undef, double %s1, i32 091 %i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer92 %vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)93 %r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)94 ret <256 x double> %r095}96