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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s3 4declare <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)5 6define fastcc <256 x i32> @test_vp_sdiv_v256i32_vv(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {7; CHECK-LABEL: test_vp_sdiv_v256i32_vv:8; CHECK: # %bb.0:9; CHECK-NEXT: and %s0, %s0, (32)010; CHECK-NEXT: lvl %s011; CHECK-NEXT: vdivs.w.sx %v0, %v0, %v1, %vm112; CHECK-NEXT: b.l.t (, %s10)13 %r0 = call <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)14 ret <256 x i32> %r015}16 17define fastcc <256 x i32> @test_vp_sdiv_v256i32_rv(i32 %s0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {18; CHECK-LABEL: test_vp_sdiv_v256i32_rv:19; CHECK: # %bb.0:20; CHECK-NEXT: and %s1, %s1, (32)021; CHECK-NEXT: and %s0, %s0, (32)022; CHECK-NEXT: lvl %s123; CHECK-NEXT: vdivs.w.sx %v0, %s0, %v0, %vm124; CHECK-NEXT: b.l.t (, %s10)25 %xins = insertelement <256 x i32> undef, i32 %s0, i32 026 %i0 = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer27 %r0 = call <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)28 ret <256 x i32> %r029}30 31define fastcc <256 x i32> @test_vp_sdiv_v256i32_vr(<256 x i32> %i0, i32 %s1, <256 x i1> %m, i32 %n) {32; CHECK-LABEL: test_vp_sdiv_v256i32_vr:33; CHECK: # %bb.0:34; CHECK-NEXT: and %s1, %s1, (32)035; CHECK-NEXT: and %s0, %s0, (32)036; CHECK-NEXT: lvl %s137; CHECK-NEXT: vdivs.w.sx %v0, %v0, %s0, %vm138; CHECK-NEXT: b.l.t (, %s10)39 %yins = insertelement <256 x i32> undef, i32 %s1, i32 040 %i1 = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer41 %r0 = call <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)42 ret <256 x i32> %r043}44 45 46declare <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)47 48define fastcc <256 x i64> @test_vp_int_v256i64_vv(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {49; CHECK-LABEL: test_vp_int_v256i64_vv:50; CHECK: # %bb.0:51; CHECK-NEXT: and %s0, %s0, (32)052; CHECK-NEXT: lvl %s053; CHECK-NEXT: vdivs.l %v0, %v0, %v1, %vm154; CHECK-NEXT: b.l.t (, %s10)55 %r0 = call <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)56 ret <256 x i64> %r057}58 59define fastcc <256 x i64> @test_vp_sdiv_v256i64_rv(i64 %s0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {60; CHECK-LABEL: test_vp_sdiv_v256i64_rv:61; CHECK: # %bb.0:62; CHECK-NEXT: and %s1, %s1, (32)063; CHECK-NEXT: lvl %s164; CHECK-NEXT: vdivs.l %v0, %s0, %v0, %vm165; CHECK-NEXT: b.l.t (, %s10)66 %xins = insertelement <256 x i64> undef, i64 %s0, i32 067 %i0 = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer68 %r0 = call <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)69 ret <256 x i64> %r070}71 72define fastcc <256 x i64> @test_vp_sdiv_v256i64_vr(<256 x i64> %i0, i64 %s1, <256 x i1> %m, i32 %n) {73; CHECK-LABEL: test_vp_sdiv_v256i64_vr:74; CHECK: # %bb.0:75; CHECK-NEXT: and %s1, %s1, (32)076; CHECK-NEXT: lvl %s177; CHECK-NEXT: vdivs.l %v0, %v0, %s0, %vm178; CHECK-NEXT: b.l.t (, %s10)79 %yins = insertelement <256 x i64> undef, i64 %s1, i32 080 %i1 = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer81 %r0 = call <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)82 ret <256 x i64> %r083}84